US20130015502A1

US20130015502A1 - Structure and method for forming a light detecting diode and a light emitting diode on a silicon-on-insulator wafer backside

Info

Publication number: US20130015502A1
Application number: US13/179,948
Authority: US
Inventors: Benjamin A. Fox; Nathaniel J. Gibbs; Andrew B. Maki; David M. Onsongo; Trevor J. Timpane
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2011-07-11
Filing date: 2011-07-11
Publication date: 2013-01-17
Anticipated expiration: 2031-07-11
Also published as: US8354678B1

Abstract

A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.

Description

TECHNICAL FIELD

The present invention relates to light detecting diodes and light emitting diodes, and particularly to a structure and method for forming a light detecting diode and a light emitting diode on a silicon-on-insulator wafer backside.

BACKGROUND

Integrated circuit inputs and outputs are provided through controlled collapse chip connections (C4s). As integrated circuits become smaller, increasing the number of C4s that can be placed on the integrated circuits is becoming a challenge. The challenge arises because the number of inputs and outputs (port density) desired for integrated circuits is increasing, but wafer surface area that is available for forming the inputs and outputs is decreasing. Increasing port density for integrated circuits can increase the functionality provided by the integrated circuits.
One way to increase port density and provide additional high speed capable inputs and outputs for an integrated circuit is by forming light detecting diodes (i.e., photo-diodes) and light emitting diodes on a wafer. Traditionally, light detecting diodes and light emitting diodes, both also referred to as optical ports, are formed on a front-side of the wafer. In addition, back-end-of-line (BEOL) processing is performed to create BEOL metal wiring and dielectric levels, and C4 pads on the front-side of the wafer. The BEOL metal wiring and dielectric levels, and C4 pads integrate the light detecting diodes and the light emitting diodes with other circuitry (i.e., other semiconductor devices) on the front-side of the wafer. Although a semiconductor structure having light detecting diodes and light emitting diodes on the front-side of the wafer may provide a performance benefit over C4 pads, generally such a semiconductor structure does not completely address the challenge of how to increase port density as technological advancements continue to result in a decrease of available wafer surface area.
Moreover, BEOL processing requires the BEOL metal wiring and dielectric levels to be formed on top of the light detecting diodes, light emitting diodes, and other semiconductor devices that may be formed on the front-side of the wafer. The BEOL dielectric isolates the BEOL metal wiring from certain areas of the wafer. However, the BEOL dielectric can cause a decrease in performance of the semiconductor devices formed on the wafer. Specifically, the BEOL dielectric can cause attenuation of light signals being emitted or detected by the diodes, and the more the BEOL metal wiring the greater the attenuation of the light signals. The attenuation of the light signals described above can decrease the performance of light detecting and light emitting diodes. Accordingly, the challenge of forming a semiconductor structure having a light detecting diode and a light emitting diode that increases port density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes respectively, continues to persist. Reducing the attenuation can enhance the performance of the diodes and consequently integrated circuits that utilize the diodes.

SUMMARY

The present invention relates to a structure and method for forming a silicon-on-insulator wafer having a backside, wherein a light detecting diode and a light emitting diode are formed on the backside to increase port density and reduce attenuation of light signals that are emitted and detected by the diodes, respectively.
In one aspect, embodiments of the invention provide a diode structure with a silicon-on-insulator wafer, and a method for forming the diode structure with the silicon-on-insulator wafer. The silicon-on-insulator wafer is joined to a dielectric layer. An alignment marker is formed in the silicon-on-insulator wafer. A back-end-of-line metal wiring and dielectric level is formed on the silicon-on-insulator wafer. An alternating n-type and p-type doped region is formed on a backside of the silicon-on-insulator wafer, wherein the alternating n-type and p-type doped region includes an n-well cathode region, a first n-well ohmic contact region, a second n-well ohmic contact region, and an anode region. A group of through-silicon vias is formed that extend through the back-end-of-line metal wiring and dielectric level, the silicon-on-insulator wafer, and the dielectric layer. A group of contacts is formed that connect the group of through-silicon vias to the alternating n-type and p-type doped region.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The subject matter which is regarded as an embodiment of the present invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. One manner in which recited features of an embodiment of the present invention can be understood is by reference to the following detailed description of embodiments, taken in conjunction with the accompanying drawings in which:

FIGS. 1-7 are cross-sectional views of a silicon-on-insulator wafer having a front-side and a backside, which illustrate process steps for fabricating a light detecting diode and a light emitting diode on the backside according to one embodiment of the present invention.

The drawings are not necessarily to scale. The drawings, some of which are merely pictorial and schematic representations, are not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, “an alternative embodiment”, “another embodiment”, etc., indicate that the embodiment described may include a particular feature, element, structure, or characteristic, but every embodiment may not necessarily include the particular feature, element, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
In addition, it will be understood that when an element as a layer, region, dielectric, or substrate is referred to as being “on” or “over”, “disposed on”, “disposed over”, “deposited on”, or “deposited over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on”, “directly over”, or “disposed proximately to” another element, there are no intervening elements present. Furthermore, it will be understood that when an element as a layer region, dielectric, or substrate is referred to as being “adjacent to” or “disposed adjacent to” another element, it can be directly adjacent to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly adjacent to” another element, there are no intervening elements present. Moreover, it will be understood that when an element as a layer, region, dielectric, or substrate is referred to as being “on and adjacent to” or “disposed on and adjacent to” another element, it can be directly on and adjacent to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on and adjacent to” another element, there are no intervening elements present. Lastly, it will also be understood that when an element is referred to as being “connected”, “coupled”, “joined”, or “proximate” to another element, it can be directly connected, directly coupled, directly joined, or directly proximate to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected”, “directly coupled”, “directly joined”, or “directly proximate” to another element, there are no intervening elements present.
Embodiments of the present invention provide a silicon-on-insulator (SOI) wafer having a backside, wherein a light detecting diode and a light emitting diode are formed on the backside to increase port density and reduce attenuation of light signals that are emitted and detected by the diodes, respectively. Reducing the attenuation can enhance the performance of the diodes, and consequently integrated circuits that utilize the diodes.
FIG. 1 illustrates a cross-sectional view of SOI wafer 100. SOI wafer 100, having a front-side 105 and a backside 107, includes a first semiconductor layer 101, a buried insulator layer 102 formed on the first semiconductor layer, and a second semiconductor layer 103 formed on the buried insulator layer. First semiconductor layer 101 and second semiconductor layer 103 are substrates that can include silicon (e.g., single crystal silicon), but are not limited to only silicon based materials. For example, first semiconductor layer 101 and second semiconductor layer 103 may include germanium (Ge), silicon-carbon (Si_1-xC_x), or other group IV materials. Alternatively, first semiconductor layer 101 may include gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), or other group III/V materials. In addition, buried insulator layer 102 includes silicon dioxide (SiO₂), and the buried insulator layer can be formed in several ways not limited to: ion implantation of oxygen ions into first semiconductor layer 101, followed by a high temperature anneal, this process is commonly referred to as SIMOX (separation by oxygen implantation); bonding oxidized silicon with second semiconductor layer 103 followed by controlled thinning; or growing the second semiconductor layer directly on the insulator. Moreover, buried insulator layer 102 can have a thickness within the range of about 300 nm to 400 nm
FIG. 2 illustrates a cross-sectional view of SOI wafer 100 with dielectric layer 104 joined to the SOI wafer. Specifically, dielectric layer 104 can be either deposited or thermally grown proximate to first semiconductor layer 101. Low to medium temperature (ranging from about 400° C. to about 650° C.) deposition can be performed utilizing a chemical vapor deposition (CVD) technique, which is preferable for use in a semiconductor fabrication process where there is thermal budget sensitivity. Thermal budget sensitivity refers to a maximum allowed temperature the wafer can be exposed to due to prior process steps. However, where thermal budget is not a concern, thermal growth can be performed at higher temperatures (ranging from about 900° C. to about 1050° C.) in an appropriate O₂, N₂, H₂ambient. Thus, performing either CVD or thermal growth results in first semiconductor layer 101 being on dielectric layer 104. Dielectric layer 104 is primarily utilized to prevent defects from forming or adhering to first semiconductor layer 101, and provide insulation for the devices formed in subsequent process steps.
Moreover, dielectric layer 104 may include nitride, oxide, or a combination thereof. Nitride is typically utilized to mitigate the diffusion of conductive material (e.g., metal atoms) into the substrates of first semiconductor layer 101 and second semiconductor layer 103. Oxide is typically utilized for adhesion, stress balancing, and as a chemical mechanical planarization (CMP) stop. Shallow trench isolation (STI) openings 106 are formed through second semiconductor layer 103 utilizing reactive ion etching (RIE), selective to buried insulator layer 102. Semiconductor devices can be formed on second semiconductor layer 103, and STI openings 106 can be filled with dielectric material to electrically isolate the semiconductor devices from each other. Utilizing STI openings 106, filled with dielectric material, can mitigate unintended short circuiting, and minimize degradation of electrical characteristics of the semiconductor devices formed on second semiconductor layer 103.
FIG. 3 illustrates a cross-sectional view of SOI wafer 100 having an alignment mark 108 formed through second semiconductor layer 103, buried insulator layer 102, and first semiconductor layer 101. Alignment mark 108 may be, but is not limited to, a deep trench that is filled with a dielectric layer and a conductive material. Specifically, to form alignment mark 108 a first photoresist and/or hardmask layer (not shown) may be deposited on front-side 105. Subsequently, utilizing an etching/removal technique (e.g., anisotropic RIE), an opening for alignment mark 108 can be formed to extend through the first photoresist and/or hardmask layer, second semiconductor layer 103, buried insulator layer 102, and first semiconductor layer 101. The opening can be filled with an alignment mark dielectric layer 110 and conductive material 111. Alignment mark dielectric layer 110 can be deposited on and adjacent to the opening utilizing a CVD technique. Alignment mark dielectric layer 110 can include an oxide such as silicon dioxide (SiO₂), a nitride such as silicon nitride (SiN), or a combination thereof. Conductive material 111 can withstand the high thermal budgets associated with conventional complementary metal-oxide-semiconductor (CMOS) front-end-of-line (FEOL) processing. For example, conductive material 111 can include polysilicon, wherein the polysilicon may be deposited on an adjacent to alignment mark dielectric layer 110 utilizing a CVD technique. Moreover, alignment mark dielectric layer 110 can electrically isolate conductive material 111 from portions of first semiconductor layer 101 and second semiconductor layer 103, to mitigate short circuiting between semiconductor devices formed on front-side 105 and on backside 107, of SOI wafer 100.
Subsequently, CMP may be performed to remove the first photoresist and/or hardmask layer, alignment mark dielectric layer 110 and conductive material 111 selective to second semiconductor layer 103, wherein the alignment mark dielectric layer and the conductive material remain only in the opening created for alignment mark 108. Alignment mark 108 can have a length 112 that ranges from about 450 um to about 600 um, and a width 113 that ranges from about 15 um to about 20 um. Specifically, length 112 is about 150 um to 200 um less than the thickness of SOI wafer 100, and the minimum width 113 is constrained by the maximum aspect ratio made possible by the etching/removal process employed to form alignment mark 108. In addition, alignment mark 108 can be subsequently utilized as a point of reference for forming a light detecting and a light emitting diode on backside 107 of SOI wafer 100. Specifically, alignment mark 108 can be utilized to align semiconductor devices formed on backside 107 with semiconductor devices formed on front-side 105 of SOI wafer 100 to enable connection between these devices on either side of the wafer.
FIG. 4 illustrates additional semiconductors structures for forming a light detecting diode and a light emitting diode on backside 107 of SOI wafer 100. Thus, to form the light detecting diode and the light emitting diode on backside 107, a protective film 114 is deposited on front-side 105 of SOI wafer 100. Protective film 114 can include a spin-on photoresist or a nitride, which may be deposited utilizing techniques that include CVD, physical vapor deposition (PVD), or spin-on approaches. The protective film 114 is required to protect front-side 105, of SOI wafer 100, from defects or impurities while semiconductor devices on backside 107 are being fabricated. Alignment mark 108, which includes alignment mark dielectric layer 110 and conductive material 111, can be utilized as a point of reference to align the semiconductor devices formed on backside 107 with semiconductor devices formed on front-side 105. In the present embodiment, alignment mark 108 is utilized as a point of reference to determine where on backside 107 to perform ion implantation to create an alternating n-type and p-type doped region having p-n junctions for the light detecting diode and the light emitting diode. Specifically, an x-ray diffraction technique or a diffraction grating measurement can be performed to allow for alignment mark 108 to be detected and utilized for aligning semiconductor devices formed on SOI wafer 100.
To form the alternating n-type and p-type region for the light detecting diode and the light emitting diode on backside 107, a lightly doped n-well cathode region 200 is formed on backside 107 utilizing ion implantation of n-type dopants. The n-type dopants utilized to form n-well cathode region 200 can include, but are not limited to, phosphorus, arsenic, or antimony. However, in the present embodiment n-well cathode region 200 is formed utilizing a phosphorus implant having a dopant concentration engineered within the range of about 1×10¹⁶atoms per cm³to about 1×10¹⁸atoms per cm³. The length 208 of n-well cathode region 200 may be about 30um and the width 210 may be about 1 um. In addition, n-well cathode region 200 may have a depth, into the page, of about 30 um. In the present embodiment, n-well cathode region 200 has a rectangular-like shape. However, in another embodiment n-well cathode region 200 may have a circular-like shape to maximize p-n junction perimeter (i.e., perimeter of anode region 204).
Furthermore, ion implantation is utilized to form heavily doped first n-well ohmic contact region 202 and heavily doped second n-well ohmic contact region 203, within n-well cathode region 200. Specifically, n-well ohmic contact regions 202 and 203 are formed in n-well cathode region 200 on backside 107 utilizing ion implantation of n-type dopants, wherein the n-type dopants can include phosphorus, arsenic, or antimony. However, in the present embodiment n-well ohmic contact regions 202 and 203 are formed utilizing a phosphorus implant having a dopant concentration range of about 5×10¹⁹atoms per cm³to about 2×10²⁰atoms per cm³. The lengths 212 and 216 of n-well ohmic contact regions 202 and 203 respectively, may be about 0.5 um. Also, the widths 214 and 218 of n-well ohmic contact regions 202 and 203 respectively, may be about 0.5 um. Furthermore, n-well ohmic contact regions 202 and 203 may have a depth into the page of about 28 um. Thus, ohmic contact regions 202 and 203 are encompassed by n-well cathode region 200. In the present embodiment, ohmic contact regions 202 and 203 are separate rectangular bars placed within n-well cathode region 200. However, in another embodiment wherein n-well cathode region 200 has a circular-like shape, ohmic contact regions 202 and 203 would be joined forming a circular-like ring shape within the n-well cathode region.
In addition, a heavily doped p-type anode region 204 is formed in n-well cathode region 200. Specifically, anode region 204 is interposed between n-well ohmic contact regions 202 and 203. The spacing between anode region 204 and n-well ohmic contact regions 202 and 203 can be engineered/tuned for efficiency, however in the present embodiment anode region 204 is spaced about 0.5 um from each of the n-well ohmic contact regions. Ion implantation of p-type dopants is utilized to form anode region 204, wherein the p-type dopants can include, but are not limited to, boron, boron difluoride (BF2) or indium. However, in the present embodiment a BF2 implant is utilized having a dopant concentration range of about 5×10¹⁹atoms per cm³to about 2×10²⁰atoms per cm³. Moreover, n-well cathode region 200 separates anode region 204 from being directly connected to n-well ohmic contact regions 202 and 203. The length 220 of anode region 204 may be about 26 um, and the width 222 may be about 0.5 um having a depth into the page of about 28 um. Thus, anode region 204 is encompassed by n-well cathode region 200. Accordingly, the final alternating n-type and p-type doped region includes n-well cathode region 200, n-well ohmic contact regions 202 and 203, and anode region 204. In the present embodiment, anode region 204 is a rectangular bar placed within n-well cathode region 200. However, in another embodiment wherein n-well cathode region 200 has a circular-like shape, anode region 204 would also have a circular-like shape within the n-well cathode region, and the anode region would be surrounded by n-well ohmic contact regions 202 and 203 having a circular-like ring shape. After completing ion implantation on backside 107, protective film 114 may be removed by a wet etch or clean to clear the way for forming field effect transistors on front-side 105 of SOI wafer 100.
FIG. 5 illustrates the formation of field effect transistors (FETs) 120 on the front-side 105 of SOI wafer 100, but other circuit components that include resistors and capacitors may be formed on the front-side of the SOI wafer. After protective film 114 (shown in FIG. 4) has been removed, conventional or existing SOI processing can be performed. Thus, standard SOI FETs are formed, and STI openings 106 (shown in FIG. 4) are filled with a dielectric material 116 that can include an oxide or a nitride. STI openings 106 once filled are utilized to electrically isolate FETs 120 formed on front-side 105. Formation of FETs 120 and other semiconductor devices and circuit components on front-side 105 is part of FEOL processing. Subsequent to FEOL processing, back-end-of-line (BEOL) processing is performed to create BEOL metal wiring and dielectric levels 121 on front-side 105, and on and adjacent to FETs 120. BEOL metal wiring and dielectric levels 121 can provide a reliable electrical connection/path between FETs 120 and other the semiconductor devices and circuit components formed on front-side 105. Following BEOL processing on front-side 105, TSVs can be formed through BEOL metal wiring and dielectric levels 121, SOI wafer 100, and dielectric layer 104.
FIG. 6 illustrates the formation of patterned openings 122 and 123. Patterned openings 122 are utilized to create a group of TSVs, and patterned openings 123 clear the way for formation of a group of contacts. The group of TSVs includes first TSV 140, second TSV 141, and third TSV 142 (all shown in FIG. 7). The group of contacts includes first contact 150, second contact 151, and third contact 152 (all shown in FIG. 7). Contacts 150-152 electrically connect TSVs 140-142 to portions of the alternating n-type and p-type doped region on backside 107. TSVs 140-142 are interconnect structures that can electrically connect semiconductor devices and circuit components formed on front-side 105 to semiconductor devices and circuit components formed on backside 107.
To create TSVs 140-142 patterned openings 122 are formed. Moreover, to form patterned openings 122 a second photoresist and/or hardmask layer (not shown) may be deposited on BEOL metal wiring and dielectric levels 121. Subsequently, utilizing an etching/removal technique, patterned openings 122 can be formed to extend through the second photoresist and/or hardmask layer, BEOL metal wiring and dielectric levels 121, second semiconductor layer 103, buried insulator layer 102, first semiconductor layer 101, n-well cathode region 200, n-well ohmic contact regions 202 and 203 or anode region 204, and dielectric layer 104. In addition, a third photoresist and/or hardmask layer (not shown) may be deposited proximate to dielectric layer 104, and patterned openings 123 may be formed through the third photoresist and/or hardmask layer and the dielectric layer, selective to n-well ohmic contact regions 202 and 203 and anode region 204. The etching/removal technique utilized to create patterned openings 122 and 123 can include, but is not limited to, dry etching, plasma etching, or reactive ion etching (RIE). In the present embodiment, patterned openings 122 and 123 are created by performing an anisotropic RIE of BEOL metal wiring and dielectric levels 121, SOI wafer 100, and dielectric layer 104. Patterned openings 122 and 123 are created to clear the way for formation of TSVs 140-142 and contacts 150-152, respectively. After patterned openings 122 and 123 are created, CMP may be performed to remove the second photoresist and/or hardmask layer and third photoresist and/or hardmask layer.
FIG. 7 illustrates the formation of contacts 150-152 and TSVs 140-142, wherein the TSVs have a corresponding first end 143-145 respectively, and a corresponding second end 146-148 respectively. Patterned openings 122 (shown in FIG. 6) may be filled with a dielectric material and a conductive material to create the final structure of TSVs 140-142. Specifically, a dielectric layer 131 having a thickness of about 10 nm is deposited directly adjacent to sidewalls of patterned openings 122 utilizing a CVD technique. Dielectric layer 131 can include an oxide such as silicon dioxide, a nitride such as silicon nitride, or a combination thereof. Thus, dielectric layer 131 can electrically isolate conductive material subsequently formed inside patterned openings 122, from portions of first semiconductor layer 101 and second semiconductor layer 103 to mitigate short circuiting.
A diffusion bather layer 132 having a thickness of about 10 nm may be deposited directly adjacent to dielectric layer 131 utilizing a deposition technique that can include CVD, PVD, or atomic layer deposition (ALD). Diffusion barrier layer 132 can include tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), or other materials that are capable of mitigating conductive material (e.g., copper or aluminum) from diffusing into first semiconductor layer 101 and second semiconductor layer 103. Diffusion of conductive material into first semiconductor layer 101 and second semiconductor layer 103 can result in degradation of the electrical characteristics of any semiconductor devices formed on the first semiconductor layer and the second semiconductor layer.
After deposition of diffusion barrier layer 132, conductive material 133 can be deposited inside patterned openings 122 and adjacent to the diffusion barrier layer to fill the remaining unfilled portions of the patterned openings. Conductive material 133 can include, but is not limited to, copper or aluminum. Conductive material 133 can be deposited in patterned openings 122 utilizing deposition techniques that can include CVD, PVD, or spin-on approaches. Afterwards, a CMP process can be performed selective to BEOL metal wiring and dielectric levels 121, wherein dielectric layer 131, diffusion barrier layer 132, and conductive material 133 remain in patterned openings 122 after the CMP process is completed. The filled patterned openings 122 are referred to as TSVs. Thus, TSVs 140-142 can each have an aspect ratio that can range from about 25:1 to 35:1. Aspect ratio refers to the ratio of the depth of a TSV to the minimum lateral dimension of the TSV. TSVs 140-142 with high aspect ratios can help increase device density on SOI wafer 100, because such TSVs consume less surface area of the SOI wafer.
Following the formation of TSVs 140-142, contacts 150-152 are formed to provide an electrical connection between semiconductor devices fabricated on front-side 105 (e.g., FETs 120) and semiconductors devices fabricated on backside 107 (e.g., a light detecting diode and a light emitting diode). Specifically, first contact 150 is joined to dielectric layer 104, second end 146 of TSV 140, and first n-well ohmic contact region 202. Second contact 151 is joined to dielectric layer 104, second end 147 of TSV 141, and anode region 204. Lastly, third contact 152 is joined to dielectric layer 104, second end 148 of TSV 142, and second n-well ohmic contact region 203. Conductive material utilized to make contacts 150-152 can include, but is not limited to, copper or aluminum. Moreover, suitable deposition techniques such as ALD or CVD may be employed to form contacts 150-152.
After formation of contacts 150-152 the semiconductor device created on backside 107 of SOI wafer 100 can be utilized either as a light detecting diode or a light emitting diode, depending on the voltage applied through TSVs 140-142. For light emission p-n junctions 225 are reversed biased to the point of avalanche breakdown. For example, a voltage of about 9V can be applied to TSVs 140 and 142 that connect to n-well ohmic contact regions 202 and 203 respectively, and a voltage of about 0V can be applied through TSV 141 that connects to anode region 204 causing the semiconductor device formed on backside 107 to function as a light emitting diode. If the semiconductor device formed on backside 107 functions as a light emitting diode then current will flow from n-well cathode region 200 to anode region 204, which will result in light being emitted from p-n junctions 225. Alternatively, a voltage of about 5V (below avalanche breakdown) can be applied through TSVs 140 and 142 that connect to n-well ohmic contact regions 202 and 203 respectively, and a voltage of about 0V can be applied through TSV 141 that connects to anode region 204 causing the semiconductor device formed on backside 107 to function as a light detecting diode. If the semiconductor device formed on backside 107 functions as a light detecting diode then current will flow from n-well cathode region 200 to anode region 204, which will result in light being detected at p-n junctions 225. Performance of light detection mode can be increased by having an intrinsically doped region adjacent to anode region 204, wherein the intrinsically doped region separates the anode region from n-well cathode region 200.
Furthermore, those skilled in the art will note from the above description, that presented herein is a novel structure and method to form a light detecting diode and light emitting diode on the backside of an SOI wafer. Forming a light detecting diode and a light emitting diode on the backside of an SOI wafer can increase port density for an integrated circuit, and reduce attenuation of light signals being detected and emitted by the diodes respectively. Lastly, the foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed and, obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.

Claims

1. A diode structure, comprising:

a silicon-on-insulator wafer joined to a dielectric layer;

an alignment marker formed in the silicon-on-insulator wafer;

a back-end-of-line metal wiring and dielectric level formed on the silicon-on-insulator wafer;

an alternating n-type and p-type doped region formed on a backside of the silicon-on-insulator wafer, wherein the alternating n-type and p-type doped region includes an n-well cathode region, a first n-well ohmic contact region, a second n-well ohmic contact region, and an anode region;

a group of through-silicon vias that extend through the back-end-of-line metal wiring and dielectric level, the silicon-on-insulator wafer, and the dielectric layer; and

a group of contacts that connect the group of through-silicon vias to the alternating n-type and p-type doped region.

2. The diode structure of claim 1, wherein:

the silicon-on-insulator wafer comprises a first semiconductor layer, a buried insulator layer formed on the first semiconductor layer, a second semiconductor layer formed on the buried insulator layer; and

the back-end-of-line metal wiring and dielectric level is formed on the second semiconductor layer.

3. The diode structure of claim 2, wherein the first semiconductor layer and second semiconductor layer comprises germanium (Ge), silicon-carbon (Si_1-xC_x), other group IV materials, gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), or other group III/V materials.

4. The diode structure of claim 2, wherein:

the buried insulator layer comprises silicon dioxide (SiO₂);

the buried insulator layer is formed by ion implantation of oxygen ions into the first semiconductor layer; and

the buried insulator layer has a thickness within the range of about 300 nm to 400 nm

5. The diode structure of claim 1, wherein:

the alignment mark comprises an opening;

an alignment mark dielectric layer is deposited on and adjacent to the opening; and

a conductive material is deposited on and adjacent to the alignment mark dielectric layer.

6. The diode structure of claim 5, wherein:

the alignment mark dielectric layer includes nitride, oxide, or a combination thereof; and

the conductive material includes polysilicon.

7. The diode structure of claim 1, wherein:

the n-well cathode region, the first n-well ohmic contact region, and the second n-well ohmic contact region comprise n-type dopants that include, but are not limited to, phosphorus, arsenic, or antimony; and

the anode region comprises p-type dopants that include, but are not limited to, boron, boron difluoride (BF2) or indium.

8. The diode structure of claim 7, wherein:

the n-well cathode region has a dopant concentration within the range of about 1×10¹⁶atoms per cm³to about 1×10¹⁸atoms per cm³;

the first n-well ohmic contact region and the second n-well ohmic contact region each have a dopant concentration within the range of about 5×10¹⁹atoms per cm³to about 2×10²⁰atoms per cm³; and

the anode region has a dopant concentration within the range of about 5×10¹⁹atoms per cm³to about 2×10²⁰atoms per cm³.

9. The diode structure of claim 1, wherein:

the group of through-silicon vias comprises a first through-silicon via, a second through-silicon via, and a third through-silicon via;

the first through-silicon via, the second through-silicon via, and the third through-silicon via comprise a diffusion barrier layer and a conductive material; and

the group of contacts comprises a first contact, a second contact, and a third contact.

10. The diode structure of claim 9, wherein:

the first contact connects the first through-silicon via to the first n-well ohmic contact region, through a patterned opening formed in the dielectric layer selective to the first n-well ohmic contact region;

the second contact connects the second through-silicon via to the anode region, through a pair of patterned openings formed in the dielectric layer selective to the anode region; and

the third contact connects the third through-silicon via to the second n-well ohmic contact region, through a patterned opening formed in the dielectric layer selective to the second n-well ohmic contact region.

11. The diode structure of claim 9, wherein:

the diffusion barrier layer comprises tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), titanium (Ti), or titanium nitride (TiN) deposited utilizing a technique that includes CVD, physical vapor deposition (PVD), or atomic layer deposition (ALD); and

the conductive material comprises copper or aluminum.

12. A method of forming a diode structure, the method comprising:

forming a silicon-on-insulator wafer joined to a dielectric layer;

forming an alignment marker formed in the silicon-on-insulator wafer;

forming a back-end-of-line metal wiring and dielectric level on the silicon-on-insulator wafer;

forming an alternating n-type and p-type doped region on a backside of the silicon-on-insulator wafer, wherein the alternating n-type and p-type doped region includes an n-well cathode region, a first n-well ohmic contact region, a second n-well ohmic contact region, and an anode region;

forming a group of through-silicon vias that extend through the back-end-of-line metal wiring and dielectric level, the silicon-on-insulator wafer, and the dielectric layer; and

forming a group of contacts that connect the group of through-silicon vias to the alternating n-type and p-type doped region.

13. The method of claim 12, wherein:

14. The method of claim 13, wherein the first semiconductor layer and second semiconductor layer comprises germanium (Ge), silicon-carbon (Si_1-xC_x), other group IV materials, gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), or other group III/V materials.

15. The method of claim 13, wherein:

the buried insulator layer comprises silicon dioxide (SiO₂);

16. The method of claim 12, wherein:

the alignment mark comprises an opening;

an alignment mark dielectric layer deposited on and adjacent to the opening; and

a conductive material deposited on and adjacent to the alignment mark dielectric layer.

17. The method of claim 16, wherein:

the conductive material includes polysilicon.

18. The method of claim 12, wherein:

19. The method of claim 18, wherein:

20. The method of claim 12, wherein:

21. The method of claim 20, wherein:

22. The method of claim 20, wherein:

the conductive material comprises copper or aluminum.