US20120085733A1

US20120085733A1 - Self aligned triple patterning

Info

Publication number: US20120085733A1
Application number: US13/042,060
Authority: US
Inventors: Bencherki Mebarki; Hao Chen; Kedar Sapre; Anchuan Wang; Tushar Mandrekar; Jingmei Liang; Yongmei Chen; Christopher S. Ngai; Mehul Naik
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2010-10-07
Filing date: 2011-03-07
Publication date: 2012-04-12

Abstract

Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application is a nonprovisional of, and claims the benefit of the filing date of U.S. Provisional Patent Application No. 61/390,955, filed Oct. 7, 2010, entitled “SELF ALIGNED TRIPLE PATTERNING” by Bencherki Mebarki et al., the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

The application relates generally to substrate processing methods and particularly to process sequences which increase the density of features on the substrate.
Shrinking integrated circuits (ICs) may result in improved performance, increased capacity and/or reduced cost. Each device shrink requires more sophisticated techniques to form the features. Photolithography is commonly used to pattern features on a substrate. An exemplary feature is a line of a material which may be a metal, semiconductor or insulator. Linewidth is the width of the line and the spacing is the distance between adjacent lines. Pitch is defined as the distance between a same point on two neighboring lines. The pitch is equal to the sum of the linewidth and the spacing. Due to factors such as optics and light or radiation wavelength, however, photolithography techniques have a minimum pitch below which a particular photolithographic technique may not reliably form features. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction.
Self-aligned double patterning (SADP) is one method for extending the capabilities of photolithographic techniques beyond their supposed minimum pitch. Such a method is illustrated in FIGS. 1A-H. With reference to FIG. 1A, patterned features 102 are formed from sacrificial structural material above a dielectric layer 114 on a substrate 100 using standard photo-lithography and etching techniques. The patterned features are referred to as placeholders, mandrels or cores and have linewidths and/or spacings near the optical resolution of a photolithography system using a high-resolution photomask. As shown in FIG. 1B, a conformal layer 106 of hard mask material is subsequently deposited over cores 102. Hard mask spacers 108 are then formed on the sides of cores 102 by preferentially etching the hard mask material from the horizontal surfaces with an anisotropic spacer etch. The resulting structure is shown in FIG. 1C. Cores 102 may then be removed, leaving behind hard mask spacers 108 (FIG. 1D). At this point hard mask spacers 108 may be used as an etch mask for transferring the pattern to the dielectric layer 114 to form dielectric ribs 116, as shown in FIG. 1E. The hard mask spacers 108 are subsequently removed (FIG. 1F).
The density of the dielectric ribs 116 is twice that of the photo-lithographically patterned features 102, the pitch of dielectric ribs 116 is half the pitch of patterned features 102. A metal layer 130 is deposited over the dielectric ribs 116 and exposed portions of the substrate 100 (FIG. 1G) and subsequently etched back or polished to form metal lines 132 between the dielectric ribs 116 as shown in FIG. 1H.
Self-aligned double patterning processes like the one represented in FIG. 1 double the density of features compared to the photo-lithographically defined features. Multiple applications of SADP techniques involve multiple applications of conformal hard mask spacers to achieve triple and quadruple patterning. Multiple hard mask spacers give rise to process control challenges involving matching of the multiple thicknesses and other repeated process parameters. Thus, there is a need for techniques which further increase the density of features formed on a substrate while reducing process complexity.

BRIEF SUMMARY

Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern.
Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating various embodiments, are intended for purposes of illustration only and are not intended to necessarily limit the scope of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the nature and advantages of the invention may be realized by reference to the remaining portions of the specification and the drawings, presented below. The Figures are incorporated into the detailed description portion of the invention.

FIGS. 1A-H illustrate cross-sectional views representing a conventional self-aligned double patterning (SADP) process in accordance with the prior art;

FIG. 2 is a flowchart depicting steps associated with a self-aligned triple patterning process according to one embodiment of the invention;

FIGS. 3A-3C illustrate cross-sectional views representing a self-aligned triple patterning process according to an embodiment of the invention; and

FIGS. 4A-4B is a flowchart depicting steps associated with a self-aligned triple patterning process according to another embodiment of the invention.

In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

DETAILED DESCRIPTION

Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern.
In order to better understand and appreciate the invention, reference is made to FIG. 2, which is a flowchart depicting steps associated with a self-aligned double patterning process according to one embodiment of the invention, and FIGS. 3A-C, which illustrate cross-sectional views of a structure as it is formed by the steps set forth in FIG. 2. The method starts by forming a stack of flat layers over a substrate. The stack includes a flat spacer layer (step 202) denoted at MH1 in FIG. 3A. The stack further includes a core layer formed above the flat spacer layer (step 204) and a nitride layer on the core layer (formed in step 206). A bottom anti-reflective coating (BARC) layer is then formed over the nitride layer (step 208) before the stack of layers is patterned. The patterning (step 210) involves forming, exposing and developing a layer of photoresist above the stack of flat layers. The resulting structure is shown in the top cross-section schematic of FIG. 3A.
The stack of layers underlying the photoresist is patterned using one or more anisotropic etches to penetrate each of the four layers (step 212) and create the structure of the middle schematic of FIG. 3A. The flat spacer is at the bottom of each of the patterned stacks of layers. The flat spacer is selectively etched (step 214) to remove about two-thirds of the flat spacers as shown in the bottom schematic of FIG. 3A. The flat spacers are thinned by removing one third of the spacer material from each side. The core layer and nitride layers essentially retain their photolithographically defined boundaries and may be described as overhanging the thinned flat spacers.
A gapfill dielectric layer is flowably deposited (step 216) underneath the overhanging portions of the core and nitride features in order substantially avoid leaving voids. The gapfill dielectric layer is also flowed into the region between the patterned stacks and may extend above the features as shown in the top schematic of FIG. 3B. The flowably deposited gapfill dielectric hardens after deposition. The hardening may happen naturally or may be assisted by curing or annealing.
The gapfill dielectric layer is then anisotropically etched (step 218) back to about the bottom of the core features as shown in the middle of FIG. 3B. A conformal spacer layer is deposited (step 220) over the core features and on the regions between (also shown in the middle schematics of FIG. 3B). The conformal spacer layer is anisotropically etched (step 224) leaving two new spacers between each of the flat thinned spacers. The density of spacer features has been tripled relative to the density present before the deposition the conformal spacer layer. The anisotropic etch of the conformal spacer layer exposes the core, which can now be removed (step 226). The resulting structure is shown in the bottom schematic of FIG. 3B.
The gapfill dielectric layer is now anisotropically etched again (step 228) to expose the substrate and the substrate can be patterned with an anisotropic etch using the spacers and/or the residual portions of the gapfill dielectric layer as a pattern-defining mask. The patterned substrate is shown in FIG. 3C.
The process depicted in FIGS. 2 and 3 are exemplary and can be generalized in a number of ways. For example, the step of etching the gapfill dielectric may be an anisotropic etch which removes more gapfill dielectric material than shown in the schematic of FIG. 3B. The gapfill dielectric may even be etched to the substrate as shown in the middle schematic of FIG. 5A. The gaps are larger at this stage of the process which may make the anisotropic etch easier. The gapfill dielectric layer must be anisotropically etched in narrower gaps in the earlier embodiment of FIGS. 2 and 3. A conformal spacer layer is deposited as before and the spacer layer is anisotropically etched. In this example, there is no gapfill oxide in the gap between the two new spacers formed from the conformal spacer layer. As a consequence, it is not necessary to use an anisotropic etch to remove the silicon oxide. Once the remaining gapfill silicon oxide is removed, the spacers can be used to pattern the substrate as before.
The conformal spacer layers described herein may be a dielectric layer such as a silicon oxide layer deposited with processes such as SACVD. Specific examples of a suitable SACVD oxide film include HARP™ films available from Applied Materials and spacer oxide, deposited on an ACE SACVD deposition system also available from Applied Materials. Generally speaking, the flat spacer layer and/or the conformal spacer layer may be made from metal (e.g. tungsten or aluminum), polysilicon, silicon nitride or silicon oxide. The initial spacer layer is deposited as a flat layer so the thinned spacers created from the initial spacer layer may be referred to herein as thinned flat spacers. A flat layer is technically also a conformal layer but is not referred to a conformal layer herein in order to avoid confusion. As such, only one conformal spacer layer is present in self-aligned triple patterning sequence in embodiments of the invention.
The flat spacers are thinned in a controlled manner using an isotropic etch. The isotropic etch may be performed in a cycled etch process allowing relatively precise control of the amount of removed material. An exemplary cycled etch process may proceed by introducing gas(es) which react with a self-limiting portion of the flat spacers, producing solid residue which may then be sublimated by elevating the temperature of the substrate before continuing the cyclic etch process. The cyclic etch process is terminated after the desired amount of materials is reacted and sublimated to leave flat spacers of about one third the initial dimension. Alternatively, a wet spacer selective etch process may be used provided that the etch rate control is sufficient. The flat spacers and conformally deposited spacers described herein may be long compared with their lateral (narrower) dimension in order to define long trenches in the substrate.
As used herein, conformal coverage refers to providing a generally uniform layer of material on a surface in the same shape as the surface, i.e., the surface of the layer and the surface being covered are generally parallel. A person of skill in the art will recognize that the deposited material likely cannot be 100% conformal and thus the term “generally” allows for acceptable tolerances. The conformal layer may have sidewall thickness between about 32% and about 34% or between about 30% and about 36% of the width of cores. The lithographically defined pitch may be 90 nm in which case the width of the cores would be about 45 nm. Self-aligned triple patterning process described herein would then result in spacers of about 15 nm width and a final pitch of 30 nm. Similarly, a starting pitch of 60 nm would result in a tripled pitch of 20 nm and spacers of about 10 nm in width. These dimensions are simply examples and other dimensions may be used.
There is also considerable flexibility in the choice of materials used for the cores. Exemplary material systems may be helpful in explaining additional details of self-aligned triple patterning processes according to disclosed embodiments. In an embodiment, cores are a combination of amorphous carbon and hydrogen (hydrogenated amorphous carbon) while conformal layer is silicon oxide. The hydrogenated amorphous carbon film may be Advanced Patterning Film™ (APF) made by Applied Materials of Santa Clara, Calif. APF is described in U.S. Pat. No. 6,573,030, which issued on Jun. 3, 2003, and which is entirely incorporated by reference herein for all purposes. Hydrogenated amorphous carbon may have an atomic composition of between about 10 percent hydrogen to about 60 percent hydrogen. Either lower temperature (e.g., 300° C.) or higher temperature (e.g., 480° C.) APF films can be used where the temperature refers to the deposition temperature of the film. In some embodiments deposition of conformal dielectric layer is performed at or below the deposition temperature of the APF film to help ensure film stability.
The core-etch may involve ashing the amorphous carbon cores to remove them in step 226. Ashing may also be used as a portion of step 212 which involves the anisotropic removal of a portion of the heterogeneous film stack. Ashing is often done by introducing O₂or O₃into a plasma above the substrate to oxidize the amorphous carbon and pumping the by-products away. The ashing process can also involve halogen-containing gases. When silicon oxide is used for conformal layer, the oxygen content near the interface with the hydrogenated amorphous carbon film can cause premature ashing. This may compromise the physical integrity of the carbon-containing cores. To avoid premature ashing the deposition of silicon oxide may begin with a silicon-rich interface and transition to the normal stoichiometry of silicon oxide thereafter. The silicon rich interface has less oxygen content and suppresses premature ashing of the cores.
Etch process gases and etch rates are often similar for silicon nitride and silicon oxide. Removing a silicon nitride core while leaving a silicon oxide spacer (or vice versa) may require an exotic etch and probably not be a likely choice. However, polysilicon may be used for the cores in combination with silicon nitride or silicon oxide spacers. In embodiments, the core material may be polysilicon or hydrogenated amorphous carbon while the spacer material may be silicon nitride or silicon oxide. The thinned spacer and the additional spacers formed from the subsequently deposited conformal layer may be the same material in embodiments of the invention. In other embodiments, the two types of spacers are made from differing materials, each having a low etch rate for the anisotropic etch of the substrate (step 228).
The description above has been given to help illustrate the principles of the present invention. It is not intended to limit the scope of the invention in any way. A large variety of variants are apparent, which are encompassed within the scope of this invention. Polysilicon lines may be formed on cores of silicon nitride, silicon oxide or hydrogenated amorphous carbon. Also, while the invention has been described in detail and with reference to specific examples thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. These equivalents and alternatives are intended to be included within the scope of the present invention

Claims

1. A method of patterning a substrate, the method comprising:

forming a stack of flat layers on a substrate comprising the sequential steps of

forming a flat spacer layer over the substrate, and

forming a flat core layer over the flat spacer layer;

patterning the stack of flat layers to form flat spacers and cores spaced according to a lithographic pitch, wherein the width of the cores is about one half of the lithographic pitch;

selectively etching the flat spacers, wherein the flat spacers are thinned relative to the cores;

forming a dielectric layer on the patterned substrate, wherein the dielectric layer is flowable during formation;

solidifying the dielectric layer

anisotropically etching the dielectric layer to expose the sides of the cores;

forming a conformal spacer layer over the cores;

anisotropically etching the conformal spacer layer, wherein two conformal spacers are formed between an adjacent pair of flat spacers and wherein the two conformal spacers in combination with the flat spacers are horizontally spaced at about one third of the lithographic pitch; and

stripping away the cores.

2. The method of claim 1 further comprising anisotropically etching the dielectric layer to expose three regions of the substrate between the adjacent pair of flat spacers.

3. The method of claim 1 wherein the cores are spaced according to the lithographic pitch are formed at or near the optical resolution of a photolithography system using a high resolution photomask.

4. The method of claim 1 wherein a thickness of the conformal spacer layer is between about 30% and about 36% of the width of the cores.

5. The method of claim 1 further comprising the additional sequential steps of:

anisotropically etching the dielectric layer, after stripping away the cores, to expose the substrate; and

transferring the pattern defined by the flat spacers and the conformal spacers into the substrate, wherein the pitch of the transferred pattern is about one third of the lithographic pitch.

6. The method of claim 1 wherein the flat spacers and the conformal spacers are made from the same material.

7. The method of claim 1 wherein the flat spacers and the conformal spacers are made from different materials.

8. The method of claim 1 wherein the flat spacers comprise one of polysilicon, metal, silicon oxide or silicon nitride.

9. The method of claim 1 wherein the conformal spacers comprise one of polysilicon, metal, silicon oxide or silicon nitride.

10. The method of claim 1 wherein the cores comprises one of dspin-on carbon or APF®.

11. The method of claim 1 wherein the layer of sacrificial structural material comprises spin-on carbon.