US20110241172A1

US20110241172A1 - Charge Balance Techniques for Power Devices

Info

Publication number: US20110241172A1
Application number: US13/083,337
Authority: US
Inventors: Christopher Boguslaw Kocon
Original assignee: Individual
Current assignee: Semiconductor Components Industries LLC
Priority date: 2006-03-30
Filing date: 2011-04-08
Publication date: 2011-10-06
Also published as: CN101416315A; KR20090007327A; CN101416315B; WO2007117938A3; US20100006927A1; AT505584A2; KR101437698B1; US7592668B2; US20070228490A1; TWI455307B; JP2009532879A; WO2007117938A2; TW200802867A; US7936013B2; DE112007000803T5

Abstract

A silicon wafer includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 12/562,025, filed Sep. 17, 2009, which is a division of U.S. application Ser. No. 11/396,239, filed Mar. 30, 2006, now U.S. Pat. No. 7,592,668, the contents of which are incorporated herein by reference in their entirety for all purposes.

BACKGROUND

The present invention relates to semiconductor power device technology, and more particularly to charge balance techniques for semiconductor power devices.
A vertical semiconductor power device has a structure in which electrodes are arranged on two opposite planes. When the vertical power device is turned on, a drift current flows vertically in the device. When the vertical power device is turned off, due to a reverse bias voltage applied to the device, depletion regions extending in the horizontal and vertical directions are formed in the device. To obtain a high breakdown voltage, a drift layer disposed between the electrodes is formed of a material having high resistivity, and a thickness of the drift layer is increased. This, however, leads to an increase in the device on-resistance Rdson, which in turn reduces conductivity and the device switching speed, thereby degrading the performance of the device.
To address this issue, charge balance power devices with a drift layer comprising vertically extending n regions (n pillar) and p regions (p pillar) arranged in an alternating manner has been proposed. FIG. 1A is a layout diagram of such a device 100. Device 100 includes an active area 110 surrounded by a non-active perimeter region which includes a p ring 120 and an outer termination region 130. The perimeter p ring 120 has a rectangular shape with rounded corners. Termination region 130 may include similarly shaped alternating p and n rings, depending on the design. Active area 110 includes alternately arranged p pillars 110P and n pillars 110N extending vertically in the form of strips and terminating along the top and bottom at the perimeter ring 120. The physical structure of the alternating p and n pillars in the active area can be seen more clearly in FIG. 1B which shows a cross section view in array region 110 along line A-A′ in FIG. 1A.
The power device depicted in FIG. 1B is a conventional planar gate vertical MOSFET with a drift layer 16 comprising alternating p pillars 110P and n pillars 110N. Source metal 28 electrically contacts source regions 20 and well regions 18 along the top-side, and drain metal 14 electrically contacts drain region 12 along the bottom-side of the device. When the device is turned on, a current path is formed through the alternating conductivity type drift layer 16. The doping concentration and physical dimensions of the n and p pillars are designed to obtain charge balance between adjacent pillars thereby ensuring that drift layer 16 is fully depleted when the device is in the off state.
Returning back to FIG. 1A, to achieve a high breakdown voltage, the quantity of n charges in the n pillars and the quantity of p charges in p pillars must be balanced in both the active area 110 and at the interface between the active area and the non-active perimeter region. However, achieving charge balance at all interface regions, particularly along the top and bottom interface regions where the p and n pillars terminate into perimeter ring 120, as well as in the corner regions where the n and p pillars have varying lengths, is difficult because of the change in geometry of the various regions. This is more clearly illustrated in FIG. 1C which shows an enlarged view of the upper left corner of power device 100 in FIG. 1A.
In FIG. 1C, a unit cell in active area 110 is marked as S1. Active p pillar 111 (which is divided into a left half portion 111-1 and a right half portion 111-2) and active p pillar 113 (which is divided into left half portion 113-1 and right half portion 113-2) are separated by an n pillar 112. The sum (Qp1+Qp2) of the quantity of p charges Qp1 in the right half portion 111-2 of the active p pillar 111 and the quantity of p charges Qp2 in the left half portion 113-1 of the active p pillar 113 in unit cell 51 is equal to the quantity of n charges Qn1 in the active n pillar 112. An optimum breakdown voltage is thus achieved in all parts of active area 110 where such balance of charge is maintained.
As shown, the corner portion of the non-active perimeter region includes the perimeter p ring 120 and termination region 130 with n ring 131 and p ring 132 which are arranged in an alternating manner. Perimeter p ring 120 (which is divided into a lower half portion 121 and an upper half portion 122) and termination region p ring 132 (which is divided into lower half portion 132-1 and upper half portion 132-2) are separated by n ring 131. The sum (Qpt1+Qpe) of the quantity of p charges Qpt1 in the lower half portion 132-1 of p ring 132 and the quantity of p charges Qpe in the upper half portion 122 of ring 120 in unit cell S2 is equal to the quantity of n charges Qnt in n ring 131. An optimum breakdown voltage is thus achieved in all parts of the non-active perimeter region where such balance of charge is maintained.
However, because of geometrical limitations, the quantity of p charges and the quantity of n charges at the interface between the active area and the non-active perimeter region are unbalanced in many places. The absence of charge balance in these regions results in a deterioration of the breakdown characteristics of the device. Thus, there is a need for charge balance techniques which eliminate the prior art charge imbalance problems at the active area to non-active perimeter region interface, thereby leading to higher breakdown voltage ratings.

BRIEF SUMMARY

In accordance with an embodiment of the invention, a silicon wafer includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region.
In accordance with another embodiment of the invention, a silicon die includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from one edge of the silicon die to an opposing edge of the silicon die. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region.
In accordance with yet another embodiment of the invention, a method of forming a charge balance structure in a semiconductor die having a silicon region of first conductivity type includes forming a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from one edge of the silicon die to an opposing edge of the silicon die. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region.
In one embodiment, the forming step includes forming a plurality of trenches extending to the predetermined depth in the silicon region, the trenches extending from the one edge of the silicon die to the opposing edge of the silicon die, and filling the plurality of trenches with silicon material of the second conductivity type.
A further understanding of the nature and the advantages of the invention disclosed herein may be realized by reference to the remaining portions of the specification and the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a simplified layout diagram of a conventional charge balance power device;

FIG. 1B shows a cross section view along A-A′ line in the power device in FIG. 1C;

FIG. 1C shows an enlarged view of the upper left corner of the power device in FIG. 1A;

FIG. 2 shows a simplified layout diagram for charge balance power devices in accordance with an exemplary embodiment of the invention;

FIG. 3 shows a simplified layout diagram for charge balance power devices in accordance with another exemplary embodiment of the invention;

FIG. 4 shows a simplified layout diagram for charge balance power devices in accordance with yet another exemplary embodiment of the invention; and

FIGS. 5 and 6 show simplified cross section views of the non-active perimeter region wherein field plates are integrated with charge balance structures according to two exemplary embodiments of the invention.

DETAILED DESCRIPTION

FIGS. 2-4 show simplified layout diagrams of dies wherein improved charge balance techniques are implemented in accordance with three exemplary embodiments of the invention. These techniques advantageously eliminate the intricate design necessary to achieve charge balance at the transition region between the active area and its surrounding non-active perimeter region in prior art charge balance devices.
In FIG. 2, a die 200 housing a charge balance power device comprises an active area 202 wherein many active cells are formed, and a non-active perimeter region surrounding the active area. The non-active perimeter region is defined by the distance from the horizontal edges of active area 202 to corresponding edges of the die marked in FIG. 2 by letter X, and by the distance from the vertical edges of active area 202 to corresponding edges of the die marked in FIG. 2 by letter Y. In general, the term “active area” is used herein to identify the region of the device in which active cells capable of conducting current are formed, and the term “non-active perimeter region” is used to identify the region of the device in which non-conducting structures are formed.
Distances X and Y in FIGS. 2-4 are significantly exaggerated in order to more clearly show the charge balance technique in these figures (in practice, distances X and Y are significantly smaller than those shown in FIG. 2-4). Where the power device housed in die 200 is a MOSFET (e.g., similar to that in FIG. 1B), the boundary of active area marked in FIG. 2 by reference numeral 202 corresponds to the boundary of the well region in which the MOSFET cells are formed.
As shown in FIG. 2, vertically extending p pillars 210P and n pillars 210N are arranged in an alternating manner to thereby form a charge balance structure. In one embodiment, active p pillars 210P are formed by creating trenches in the silicon and filling them with p-type silicon using known techniques such as selective epitaxial growth (SEG). In general, the physical dimensions and doping concentration of the n and p pillars are optimized so as to obtain charge balance between adjacent pillars, similar to that described above in connection with unit cell S1 in FIG. 1C.
In FIG. 2, unlike conventional charge balance devices wherein the p and n pillars in the active area terminate at the boundary of the active area, the active p and n pillars extend through both the active area and the non-active perimeter region, as shown. This eliminates the charge balance concerns at the edges and corners of the active area, thus achieving perfect charge balance and breakdown characteristics while significantly simplifying the design of the device.
In one embodiment, distances X and Y are chosen to ensure full depletion outside the active area. In one embodiment wherein p pillars are formed by forming trenches in silicon, each of distances X and Y is equal to or greater than a depth of the p pillar trenches. While the vertical edges of active area 202 are shown in FIG. 2 to fall within n pillars, the active area could be expanded or contracted so that the vertical edges of the active area fall within p pillars. As such, there are no misalignment issues with respect to the edges of active area 202 and the pillars. In one embodiment, the starting wafer may include the p and n pillars as shown in FIG. 2, and the power device including its active area and other regions are formed using known manufacturing techniques.
FIG. 3 shows another embodiment which is similar to that in FIG. 2 except a discontinuity is formed in the vertically extending p pillars in each of the upper and lower non-active perimeter region. The discontinuities form a horizontally extending n strip 320N which breaks up each p pillar into two portions 310P-1 and 310P-2 as shown in the lower non-active perimeter region. The discontinuity in the p pillars disturbs the fields in the non-active perimeter region so as to reduce the fields along the silicon surface in this region. This helps improve the breakdown voltage in the non-active perimeter region.
In one embodiment, a spacing B from the edge of active area 302 to n strip 320N is determined based on the voltage rating of the power device, photo tool limitations, and other performance and design goals. In one embodiment, a smaller spacing B is used enabling finer field distribution adjustments. Once again, the dimensions in the non-active perimeter region (X, Y, B) are all exaggerated to more easily illustrate the various features of the invention.
FIG. 4 shows a variation of the FIG. 3 embodiment wherein multiple discontinuities are formed in each p pillar in each of the upper and lower non-active perimeter regions, thus forming multiple n strips 420N, 430N in these regions. Multiple discontinuities enable higher voltage ratings. As shown, outer strip 430N is wider than inner strip 420N. The considerations in selecting the widths of the N strips and the spacing therebetween are similar to those for conventional termination guard rings. In one embodiment, the n strips in FIGS. 3 and 4 are formed as follows. During the process of forming the p pillars, a mask is used to prevent formation of p pillars at the gap locations along the p pillars.
The techniques in FIGS. 2-4 may be combined with other edge termination techniques as needed. In particular, termination field plate techniques may be advantageously combined with the embodiments in FIGS. 2-4 to further reduce the fields at the silicon surfaces in the non-active perimeter region. Two examples of such combination are shown in FIGS. 5 and 6.
FIG. 5 shows a cross section view along a region of the die at an edge of the active area. In FIG. 5, the active area extends to the left of p-well 502, and the non-active perimeter region extends to the right of p-well 502. As in FIGS. 2-4 embodiment, p-pillars 510P and n-pillar 510N extend through both the active area and non-active perimeter region. As shown, p-pillars 510P terminate at a depth within N-epitaxial layer 512, and those portions of N-epitaxial layer 512 extending between p-pillars 510P form the n-pillars 510N of the charge balance structure. Floating p-type diffusion rings 504A-504C are formed in the non-active perimeter region and extend around the active region. As can be seen, the spacing between adjacent rings progressively increases in the direction away from the active region. A dielectric layer 506 insulates rings 504A-504C from overlying structures (not shown). P-well 502 may either be the last p-well of the active area or form part of the termination structure. In either case, p-well 502 would be electrically connected to the active p-well.
FIG. 6, similar to FIG. 5, shows a cross section view of a region of the die at an edge of the active area, with the active area extending to the left of p-well 602 and the termination region extending to the right of p-well 502. P-pillars 610P and n-pillar 610N extend through both the active and termination regions. As in the FIG. 5 embodiment, p-pillars 610P terminate at a depth within N-epitaxial layer 612, and those portions of N-epitaxial layer 612 extending between p-pillars 610P form the n-pillars 610N of the charge balance structure. In this embodiment however, a planar field plate structure is formed over the non-active perimeter region. The planar field plate structure includes a polysilicon layer 608 extending over the non-active perimeter region, and a metal contact layer 614 electrically connects polysilicon layer 608 to p-well 602. A dielectric layer 606 insulates the charge balance structure in the non-active perimeter region from the overlying polysilicon layer 608 and other structures not shown. As in the FIG. 5 embodiment, p-well 602 may either be the last p-well of the active area or form part of the termination structure. In either case, p-well 502 would be electrically connected to the active p-well.
While FIGS. 5 and 6 show two different edge termination techniques, these two techniques may be combined in a variety of ways. For example, in an alternate implementation of the FIG. 6 embodiment, a number of floating p-type diffusion rings are included in the non-active perimeter region in similar manner to that in FIG. 5 except that the p-type diffusion rings are placed to the left of field plate 608. As another example, in an alternate implementation of the FIG. 5 embodiment, a separate planar field plate is connected to each floating p-type diffusion ring 504A-504C.
The various charge balance techniques disclosed herein may be integrated with the vertical planar gate MOSFET cell structure shown in FIG. 1B, and other charge balance MOSFET varieties such as trench gate or shielded gate structures, as well as other charge balance power devices such as IGBTs, bipolar transistors, diodes and schottky devices. For example, the various embodiments of the present invention may be integrated with any of the devices shown for example, in FIGS. 14, 21-24, 28A-28D, 29A-29C, 61A, 62A, 62B, 63A of the above-referenced U.S. patent application Ser. No. 11/026,276, filed Dec. 29, 2004 which disclosure is incorporated herein by reference in its entirety for all purposes.
While the above provides a detailed description of various embodiments of the invention, many alternatives, modifications, and equivalents are possible. Also, it is to be understood that all numerical examples and material types provided herein to describe various embodiments are for illustrative purposes only and not intended to be limiting. For example, the polarity of various regions in the above-described embodiments can be reversed to obtain opposite type devices. For this and other reasons, therefore, the above description should not be taken as limiting the scope of the invention as defined by the claims.

Claims

1-18. (canceled)

19. A silicon wafer comprising:

a silicon region of first conductivity type; and

a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.

20. The silicon wafer of claim 19 wherein the first conductivity type is n type and second conductivity type is p type.

21. A silicon die comprising:

a silicon region of first conductivity type; and

a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from one edge of the silicon die to an opposing edge of the silicon die, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.

22. The silicon wafer of claim 21 wherein the first conductivity type is n type and second conductivity type is p type.

23. A method of forming a charge balance structure in a semiconductor die having a silicon region of first conductivity type, the method comprising:

forming a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from one edge of the silicon die to an opposing edge of the silicon die, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.

24. The silicon wafer of claim 23 wherein the forming step comprises:

forming a plurality of trenches extending to the predetermined depth in the silicon region, the trenches extending from the one edge of the silicon die to the opposing edge of the silicon die; and

filling the plurality of trenches with silicon material of the second conductivity type.

25. The method of claim 23 wherein the first conductivity type is n type and second conductivity type is p type.