US20100322018A1

US20100322018A1 - Temperature Compensation Circuit and Method for Sensing Memory

Info

Publication number: US20100322018A1
Application number: US12/870,313
Authority: US
Inventors: Wen-Chiao Ho; Ji-Yu Hung; Chun-Hsiung Hung; Shuo-Nan Hung
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2008-11-14
Filing date: 2010-08-27
Publication date: 2010-12-23
Anticipated expiration: 2028-11-14
Also published as: US20100124136A1; US7804729B2; US8208332B2

Abstract

A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.

Description

This application is a continuation application of co-pending U.S. application Ser. No. 12/271,022, filed on Nov. 14, 2008.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The invention relates in general to a temperature compensation circuit and a method for sensing memory, and more particularly to a temperature compensation circuit and method capable of decreasing the temperature influence.
2. Description of the Related Art
FIG. 1 (Prior Art) is a schematic illustration showing a conventional memory 100. The memory 100 includes a plurality of bit lines BL1 to BLm, a plurality of drain select switches, a plurality of memory cell strings and a plurality of source select switches. For example, the bit line BL1 corresponds to a drain select switch MD, memory cells 200 to 231 and a source select switch MS. The drain select switch MD is controlled by a control signal DS, the memory cells 200 to 231 are respectively controlled by word line signals WL0 to WL31, and the source select switch MS is controlled by a control signal SS.
FIG. 2 (Prior Art) shows a read timing chart of the conventional memory. At time T1, a read compare voltage, such as 3V, is applied to a word line WL_sel corresponding to a to-be-read target memory cell so that the data stored in the target memory cell can be determined. Meanwhile, a read pass voltage, such as 5V, is applied to a word line WL_unsel corresponding to other memory cells. At time T2, the control signal DS turns on the drain select switch MD to charge the bit line WL0 to about 0.7V and to make the voltage of the bit line WL0 become floating.
At time T3, the control signal SS controls the source select switch MS to turn on. If the target memory cell has a low threshold voltage, a discharge path is generated to lower the voltage of the bit line BL1. On the contrary, if the target memory cell has a high threshold voltage, the voltage of the bit line BL1 is held. So, at time T4, the voltage of the bit line BL1 is sensed. If the voltage of the bit line BL1 is still held at the voltage of 240, the target memory cell has the high threshold voltage; and if the voltage of the bit line BL1 is lowered to the voltage of 242, the target memory cell has the low threshold voltage. Consequently, it is possible to judge whether the data stored in the target memory cell is 0 or 1.
However, the memory cell current is associated with the temperature. With the change of the temperature, the discharging current I may be increased so that the voltage change of the bit line BL1 is increased. For example, when the target memory cell has the high threshold voltage, the voltage of the bit line BL1 is slightly lowered to the voltage of 244. When the target memory cell has the low threshold voltage, the voltage of the bit line BL1 is further lowered to the voltage of 246. Consequently, different bit line voltages at the sensing time T4 may cause the read window loss. FIG. 3 (Prior Art) is a graph showing a bit line voltage of a target memory cell of the conventional memory versus time. As shown in FIG. 3, the read window loss ΔV is caused if the sensing operation is performed at the same time T4 but different corresponding temperatures t1 and t2.

SUMMARY OF THE INVENTION

The invention is directed to a temperature compensation circuit and a method for sensing a memory, wherein an emulation cell array is employed to emulate the change of a memory cell current of a memory cell array associated with the temperature so that the temperature influence is reduced and the read window is improved.
According to a first aspect of the present invention, a compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.
According to a second aspect of the present invention, a compensation method applied to a compensation circuit is provided. The compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal and a second terminal and the emulation circuit is coupled to the first terminal of the comparator. The method includes the following steps. A reference voltage is provided to the second terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.
The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (Prior Art) is a schematic illustration showing a conventional memory.

FIG. 2 (Prior Art) shows a read timing chart of the conventional memory.

FIG. 3 (Prior Art) is a graph showing a bit line voltage of a target memory cell of the conventional memory versus time.

FIG. 4 is a schematic illustration showing a memory according to a preferred embodiment of the invention.

FIG. 5 is a circuit diagram showing a temperature compensation circuit according to the preferred embodiment of the invention.

FIG. 6 is a graph showing a bit line voltage of a target memory cell according to the preferred embodiment of the invention versus time.

FIG. 7 is a flow chart showing a temperature compensation method for sensing a memory according to the preferred embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention provides a temperature compensation circuit and method for sensing a memory, wherein an emulation cell array is employed to emulate the change of a memory cell current of a memory cell array associated with the temperature and to control the timing of a sense amplifier for sensing the memory cell array so that the temperature influence is reduced and the read window is improved.
FIG. 4 is a schematic illustration showing a memory 400 according to a preferred embodiment of the invention. The memory 400, such as a non-volatile memory or even a NAND type memory, includes a memory cell array 410, a sense amplifier 420 and a temperature compensation circuit 430. FIG. 5 is a circuit diagram showing the temperature compensation circuit 430 according to the preferred embodiment of the invention. Referring to FIG. 5, the temperature compensation circuit 430 includes a voltage generator 432, a comparator 434, a first switch SW1, a second switch SW2 and an emulation cell array 436.
In the temperature compensation circuit 430, the first switch SW1 is coupled to and between the voltage generator 432 and a first terminal (node A) of the comparator 434, the second switch SW2 is coupled to and between the first terminal (node A) of the comparator 434 and the emulation cell array 436. The emulation cell array 436 is independent from the memory cell array 410 or may be integrated in the memory cell array 410. The emulation cell array 436 includes a drain select switch MD, an emulation cell string and a source select switch MS, which are connected in series.
In the temperature compensation circuit 430, the voltage generator 432 provides a reference voltage Vref to a second terminal (node B) of the comparator 434. Then, when the drain select switch MD and the source select switch MS are not turned on, the first switch SW1 and the second switch SW2 are turned on, and the voltage generator 432 charges the first terminal (node A) of the comparator 434 to a predetermined voltage Vdis. The predetermined voltage Vdis is a constant voltage (e.g., 2V), which does not fluctuate as the temperature is changed.
Because the emulation cell array 436 is substantially for emulating the memory cell array 410, the load of the bit line mBL of the emulation cell array 436 is proportional to the load of the bit line BL of the memory cell array 410. In addition, both the cell currents thereof have the same change generated as the temperature is changed. According to
$I = \frac{\partial Q}{\partial t} = C \frac{\partial V}{\partial t},$
if the load of the bit line mBL is 10% that of the bit line BL, and the memory cell array need 0.1V bit line voltage difference for sensing, that means, the reference voltage Vref is equal to (Vdis−1) V. If the load of the bit line mBL is 50% that of the bit line BL, the reference voltage Vref is equal to (Vdis−0.2) V. That is, the difference voltage between the predetermined voltage Vdis and the reference voltage Vref is associated with a ratio of the load of the emulation cell array 436 to the load of the memory cell array 410.
Thereafter, the drain select switch MD and the source select switch MS are turned on, and the first switch SW1 is turned off so that the first terminal (node A) of the comparator 434 is discharged via a discharge path formed by the drain select switch MD, the emulation cell string and the source select switch MS. When the voltage of the first terminal (node A) of the comparator 434 is lower than the reference voltage Vref of the node B, the comparator 434 outputs a read timing control signal RTCS to control the sense amplifier 420 to sense the memory cell array 410.
In the temperature compensation circuit 430, the emulation cell array 436 emulates the memory cell array 410. So, both the cell currents thereof have the same change generated as the temperature is changed. If the temperature change lowers the cell current, then the time, during which the voltage of the node A is discharged from the predetermined voltage Vdis to the reference voltage Vref, is lengthened. That is, the comparator 434 outputs the read timing control signal RTCS more slowly to control the sense amplifier 420 to perform the sensing operation. On the contrary, if the temperature change increases the cell current, the voltage of the node A is discharged quicker, and the comparator 434 outputs the read timing control signal RTCS earlier. FIG. 6 is a graph showing a bit line voltage of a target memory cell according to the preferred embodiment of the invention versus time. As shown in FIG. 6, the sensing operations are performed at different temperatures t1 and t2 and in different times T4 and T4′. Consequently, the loss of the read window is not caused.
The invention also provides a temperature compensation method applied to a temperature compensation circuit. The temperature compensation circuit includes a voltage generator, a comparator and an emulation cell array. FIG. 7 is a flow chart showing a temperature compensation method for sensing a memory according to the preferred embodiment of the invention. In step S700, the voltage generator provides a reference voltage to a second terminal of the comparator. In step S710, the voltage generator charges a first terminal of the comparator to a predetermined voltage. In step S720, the first terminal of the comparator is discharged via the emulation cell array. In step S730, the comparator outputs a read timing control signal to control a sense amplifier to perform a sensing operation when the voltage of the first terminal of the comparator is lower than the reference voltage.
The operation principle of the temperature compensation method has been disclosed in the description corresponding to the memory 400, so detailed descriptions thereof will be omitted.
In the temperature compensation circuit and the temperature compensation method according to the embodiment of the invention, the emulation cell array is employed to emulate the change of the memory cell current of the memory cell array associated with the temperature and to control the sense amplifier to perform the sensing operations on the memory cell array at different temperatures and different timings. Consequently, it is possible to reduce the influence of the temperature on the cell current and to improve the read window of the memory.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims

1. A temperature compensation circuit, comprising:

a comparator having a first terminal and a second terminal, the second terminal for receiving a reference voltage; and

an emulation circuit coupled to the first terminal of the comparator,

wherein the emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.

2. The compensation circuit according to claim 1, wherein the comparator outputs the reading timing control signal at the first time spot if a current of the emulation circuit is decreased, or outputs the red timing control signal at the second time spot if the current of the emulation circuit is increased.

3. The compensation circuit according to claim 1, wherein the first terminal of the comparator receives a predetermined voltage, and the predetermined voltage is a constant voltage, which does not fluctuate as a temperature of the compensation circuit is changed.

4. The compensation circuit according to claim 3, wherein when a voltage of the first terminal of the comparator is discharged, via the emulation circuit, to be lower than the reference voltage, the comparator outputs the read timing control signal to control a sense amplifier to perform a sensing operation.

5. The compensation circuit according to claim 4, wherein the comparator outputs the read timing control signal to control the sense amplifier to read a memory cell array, and a difference voltage between the predetermined voltage and the reference voltage is associated with a ratio of a load of the emulation circuit to a load of the memory cell array.

6. The compensation circuit according to claim 5, wherein the emulation circuit is independent from the memory cell array.

7. The compensation circuit according to claim 5, wherein the emulation circuit is integrated in the memory cell array.

8. The compensation circuit according to claim 1, wherein:

the emulation circuit comprises a drain select switch, an emulation cell string and a source select switch, which are connected in series;

when the drain select switch and the source select switch are turned off, the first terminal of the comparator is charged to the predetermined voltage; and

the drain select switch and the source select switch are then turned on so that the first terminal of the comparator is discharged via the drain select switch, the emulation cell string and the source select switch.

9. The compensation circuit according to claim 1, further comprising a first switch and a second switch, wherein the first switch is coupled to the first terminal of the comparator, and the second switch is coupled to and between the first terminal of the comparator and the emulation circuit.

10. A compensation method for sensing a memory, the method being applied to a compensation circuit, which comprises a comparator and an emulation circuit, the comparator having a first terminal and a second terminal, and the emulation circuit coupled to the first terminal of the comparator, the method comprising the steps of:

providing a reference voltage to the second terminal of the comparator; and

the emulation circuit responding to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.

11. The method according to claim 10, wherein the comparator outputs the reading timing control signal at the first time spot if a current of the emulation circuit is decreased, or outputs the red timing control signal at the second time spot if the current of the emulation circuit is increased.

12. The method according to claim 10, wherein a predetermined voltage is provided to the first terminal of the comparator, and the predetermined voltage is a constant voltage, which does not fluctuate as a temperature is changed.

13. The method according to claim 10, wherein when a voltage of the first terminal of the comparator is discharged, via the emulation circuit, to be lower than the reference voltage, the read timing control signal is outputted by the comparator to control a sense amplifier to perform a sensing operation.

14. The method according to claim 13, wherein the comparator outputs the read timing control signal to control the sense amplifier to read a memory cell array, and a difference voltage between the predetermined voltage and the reference voltage is associated with a ratio of a load of the emulation circuit to a load of the memory cell array.

15. The method according to claim 10, wherein the emulation circuit comprises a drain select switch, an emulation cell string and a source select switch, which are connected in series, and the method further comprises the steps of:

charging the first terminal of the comparator to the predetermined voltage when the drain select switch and the source select switch are turned off; and

turning on the drain select switch and the source select switch such that the first terminal of the comparator is discharged via the drain select switch, the emulation cell string and the source select switch.