[go: up one dir, main page]

US20100184293A1 - Planarization process for pre-damascene structure including metal hard mask - Google Patents

Planarization process for pre-damascene structure including metal hard mask Download PDF

Info

Publication number
US20100184293A1
US20100184293A1 US12/726,347 US72634710A US2010184293A1 US 20100184293 A1 US20100184293 A1 US 20100184293A1 US 72634710 A US72634710 A US 72634710A US 2010184293 A1 US2010184293 A1 US 2010184293A1
Authority
US
United States
Prior art keywords
slurry
hard mask
planarization process
layer
metal hard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US12/726,347
Other versions
US8314031B2 (en
Inventor
Chia-Lin Hsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to US12/726,347 priority Critical patent/US8314031B2/en
Publication of US20100184293A1 publication Critical patent/US20100184293A1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSU, CHIA-LIN
Application granted granted Critical
Publication of US8314031B2 publication Critical patent/US8314031B2/en
Adjusted expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H10P52/403

Definitions

  • the present invention relates to a semiconductor process. More particularly, the present invention relates to a planarization process for a pre-damascene structure that includes a metal hard mask.
  • this invention provides a planarization process for a pre-damascene structure including a metal hard mask, which removes the metal hard mask also through CMP.
  • the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask.
  • a first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening, and then a second CMP step is conducted using a second slurry to remove the metal hard mask.
  • the first material layer and the second material layer may include a dielectric layer and a metal layer, respectively, for forming an interconnect damascene structure.
  • a barrier layer is preferably formed in the damascene opening and on the metal hard mask before the metal layer as the second material layer is formed, while the barrier layer on the metal hard mask is removed in the second CMP step prior to the metal hard mask.
  • the above damascene opening may be, for example, a dual damascene opening that includes a trench and a via hole contiguous with the trench.
  • the pre-damascene structure may include a dielectric layer as a first material layer, a metal layer as a second material layer and a barrier layer in the damascene opening and on the metal hard mask, while the planarization process may include three CMP steps.
  • the first CMP step is conducted using a first slurry to remove the metal layer outside the damascene opening.
  • the second CMP step is conducted using a second slurry to sequentially remove the barrier layer on the metal hard mask and the metal hard mask.
  • the third CMP step is then conducted using a third slurry to remove a portion of the dielectric layer.
  • FIGS. 1-3 illustrate a process flow of a planarization process according to a first embodiment of this invention.
  • FIGS. 4 and 5 illustrate different stages in the second CMP step of a planarization process according to a second embodiment of this invention, while FIGS. 1 , 2 , 4 + 5 and 3 in sequence illustrate the whole planarization process of the second embodiment.
  • such a second slurry may include SiO 2 , H 2 O 2 , benzotriazole (BTA) and water as well as have a pH value of 9-13, wherein BTA serves as a copper corrosion inhibitor.
  • the second CMP step may also be conducted on one platen, or on two separated platens in the same CMP machine to increase the throughput, as mentioned above.
  • FIGS. 1 , 2 , 4 + 5 and 3 in sequence illustrate the whole planarization process according to the second embodiment of this invention.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation application of and claims the priority benefit of patent application Ser. No. 11/160,262 filed on Jun. 16, 2005, now allowed. The entirety of the above patent application is incorporated by reference herein and made a part of this specification.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor process. More particularly, the present invention relates to a planarization process for a pre-damascene structure that includes a metal hard mask.
  • 2. Description of the Related Art
  • Damascene techniques are frequently used to form interconnect structures. In a conventional damascene process, a dielectric layer is formed and then patterned using a hard mask to form a damascene opening therein, a metal layer is formed filling the damascene opening, the metal layer outside the opening is removed through chemical mechanical polishing (CMP), and then the hard mask is removed. In the related art, the process of removing the metal layer outside the damascene opening through CMP is considered as a planarization process.
  • However, as the linewidth of semiconductor devices becomes smaller, the conventional SiO or SiN hard mask is no longer satisfactory for the requirements in critical dimension (CD). Therefore, metal hard masks are reported to use in advanced semiconductor processes. In the prior art, a metal hard mask is removed through dry- or wet-etching after the metal layer filling the damascene opening is planarized through CMP.
  • SUMMARY OF THE INVENTION
  • Accordingly, this invention provides a planarization process for a pre-damascene structure including a metal hard mask, which removes the metal hard mask also through CMP.
  • In a planarization process of this invention, the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening, and then a second CMP step is conducted using a second slurry to remove the metal hard mask.
  • According to a preferred embodiment of this invention, the first material layer and the second material layer may include a dielectric layer and a metal layer, respectively, for forming an interconnect damascene structure. In such cases, a barrier layer is preferably formed in the damascene opening and on the metal hard mask before the metal layer as the second material layer is formed, while the barrier layer on the metal hard mask is removed in the second CMP step prior to the metal hard mask.
  • Moreover, the above damascene opening may be, for example, a dual damascene opening that includes a trench and a via hole contiguous with the trench.
  • According to another embodiment of this invention, the pre-damascene structure may include a dielectric layer as a first material layer, a metal layer as a second material layer and a barrier layer in the damascene opening and on the metal hard mask, while the planarization process may include three CMP steps. The first CMP step is conducted using a first slurry to remove the metal layer outside the damascene opening. The second CMP step is conducted using a second slurry to sequentially remove the barrier layer on the metal hard mask and the metal hard mask. The third CMP step is then conducted using a third slurry to remove a portion of the dielectric layer.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1-3 illustrate a process flow of a planarization process according to a first embodiment of this invention.
  • FIGS. 4 and 5 illustrate different stages in the second CMP step of a planarization process according to a second embodiment of this invention, while FIGS. 1, 2, 4+5 and 3 in sequence illustrate the whole planarization process of the second embodiment.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment
  • Referring to FIG. 1, a substrate 100 having a prior conductive layer 110, a cap layer 120 and a pre-dual damascene structure thereon is provided, wherein the pre-dual damascene structure will be processed into a dual damascene structure that electrically connects with the conductive layer 110. The pre-dual damascene structure includes a dielectric layer 130 having a trench 150 and a via hole 160 contiguous with the trench 150 therein, a metal hard mask 140 on the dielectric layer 130, and a metal layer 180 filling the trench 150 and the via hole 160 and covering the metal hard mask 140.
  • In addition, a barrier layer 170 is preferably formed on the inner surfaces of the trench 150 and the via hole 160 and on the metal hard mask 140 before the metal layer 180 is formed, so as to prevent diffusion of metal atoms from the metal layer 180. The bottom of the metal layer 180 in the via hole 160 is separated from the conductive layer 110 by the barrier layer 170. The material of the cap layer 120 may be silicon nitride (SiN), SiC, SiCN, SiCO or SiCNO, etc., and the dielectric layer 130 may include TEOS-oxide, thermal oxide or low-k material, etc. The material of the metal hard mask 140 may be Ti, Ta, W, TiN, TaN or WN, for example, wherein the metal nitrides are preferable. The barrier layer 170 may include Ta or Ta/TaN, for example, and the metal layer 180 is possibly a copper layer.
  • Referring to FIG. 2, a first CMP step is conducted using a first slurry to remove the metal layer 180 outside the trench 150, so that a conductive line 180 a and a contact plug 180 b are formed in the trench 150 and the via hole 160, respectively. The selectivity of the first slurry to the metal layer 180 relative to the barrier layer 170 preferably ranges from 50:1 to 500:1. When the metal layer 180 includes copper, such a slurry may include SiO2 or Al2O3, H2O2 and water and have a pH value of 1-6. In addition, the first CMP step can be conducted on one platen, or on two separated platens in the same CMP machine to increase the throughput, as known in the art.
  • Referring to FIG. 3, a second CMP step is conducted using a second slurry to sequentially remove the barrier layer 170 on the metal hard mask 140 and the metal hard mask 140. The second CMP step can be further conducted to remove a portion of the dielectric layer 130. In such a case, the selectivity of the second slurry to the barrier layer 170 relative to the metal layer 180 preferably ranges from 1:1 to 5:1, the selectivity of the second slurry to the barrier layer 170 relative to the metal hard mask 140 preferably ranges from 1:5 to 5:1, and the selectivity of the second slurry to the barrier layer 170 relative to the dielectric layer 130 preferably ranges from 0.5:1 to 50:1. When the metal layer 180 includes copper, such a second slurry may include SiO2, H2O2, benzotriazole (BTA) and water as well as have a pH value of 9-13, wherein BTA serves as a copper corrosion inhibitor. The second CMP step may also be conducted on one platen, or on two separated platens in the same CMP machine to increase the throughput, as mentioned above.
  • Second Embodiment
  • FIGS. 1, 2, 4+5 and 3 in sequence illustrate the whole planarization process according to the second embodiment of this invention.
  • In the second embodiment, the substrate 100 having a pre-damascene structure as shown in FIG. 1 thereon is provided. A first CMP step is conducted to remove the copper layer 180 outside the damascene opening (150+160), as shown in FIG. 2. The slurry and polishing conditions adopted in the first CMP step can be the same as those mentioned in the above first embodiment.
  • Referring to FIGS. 4-5, a second CMP step is conducted using a second slurry to remove the barrier layer 170 on the metal hard mask 140 (FIG. 4) and then remove the metal hard mask 140 (FIG. 5). In the second CMP step, the selectivity of the second slurry to the barrier layer 170 relative to the metal layer 180 preferably ranges from 1:1 to 5:1, the selectivity of the second slurry to the barrier layer 170 relative to the metal hard mask 140 preferably ranges from 1:5 to 5:1, and the selectivity of the second slurry to the barrier layer 170 or the metal hard mask 140 relative to the dielectric layer 130 ranges from 3:1 to 50:1. When the metal layer 180 includes copper, such a second slurry may include SiO2, H2O2, benzotriazole (BTA) and water as well as have a pH value of 4-6, wherein the amount of SiO2 is no more than 10 wt % for inhibiting the polishing selectivity to the dielectric layer 130, and BTA serves as a copper corrosion inhibitor. In addition, the second CMP step may also be conducted on one platen, or on two separated platens in the same CMP machine to increase the throughput, as mentioned above.
  • Referring to FIG. 3, a third CMP step is conducted using a third slurry to remove a portion of the dielectric layer 130, so as to ensure that no residue of the metal hard mask 140 remains to short different conductive lines/contact plugs 180 a/b. When the metal layer includes copper, the third slurry suitable for TEOS-oxide, thermal oxide or low-k material, etc., may include SiO2, H2O2, benzotriazole (BTA) and water as well as have a pH value of 9-13. The third CMP step may also be conducted on one platen, or on two separated platens in the same CMP machine to increase the throughput, as mentioned above.
  • As described above, by applying the planarization process of this invention, the metal layer filling the damascene opening as well as the metal hard mask can be removed sequentially through CMP.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (12)

1. A planarization process for a pre-damascene structure which includes a metal hard, mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask, comprising:
conducting a first chemical mechanical polishing (CMP) step using a first slurry to remove the second material layer outside the damascene opening; and
conducting a second CMP step using a second slurry to remove the metal hard mask, wherein a composition of the second slurry is different from a composition of the first slurry,
wherein the second material layer comprises a metal layer, and the second slurry comprises SiO2, H2O2 and water.
2. The planarization process of claim 1, wherein the first material layer comprises a dielectric layer.
3. The planarization process of claim 2, wherein the damascene opening comprises a dual damascene opening.
4. The planarization process of claim 2, wherein
the pre-damascene structure further comprises a barrier layer in the damascene opening and on the metal hard mask; and
the second CMP step removes the barrier layer on the metal hard mask before removing the metal hard mask.
5. The planarization process of claim 4, wherein selectivity of the first slurry to the metal layer relative to the barrier layer ranges from 50:1 to 500:1.
6. The planarization process of claim 5, wherein the metal layer comprises copper, and the first slurry comprises SiO2 or Al2O3, H2O2 and water and has a pH value of 1-6.
7. The planarization process of claim 4, wherein the second CMP step further removes a portion of the dielectric layer after removing the metal hard mask.
8. The planarization process of claim 4, wherein
selectivity of the second slurry to the barrier layer relative to the metal layer ranges from 1:1 to 5:1;
selectivity of the second slurry to the barrier layer relative to the metal hard mask ranges from 1:5 to 5:1; and
selectivity of the second slurry to the barrier layer relative to the dielectric layer ranges from 0.5:1 to 50:1.
9. The planarization process of claim 8, wherein the metal layer comprises copper.
10. The planarization process of claim 1, wherein the second slurry further comprises benzotriazole (BTA).
11. The planarization process of claim 1, wherein the second slurry has a pH value of 9-13.
12. The planarization process of claim 11, wherein the second slurry further comprises benzotriazole (BTA).
US12/726,347 2005-06-16 2010-03-18 Planarization process for pre-damascene structure including metal hard mask Expired - Lifetime US8314031B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/726,347 US8314031B2 (en) 2005-06-16 2010-03-18 Planarization process for pre-damascene structure including metal hard mask

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/160,262 US7718536B2 (en) 2005-06-16 2005-06-16 Planarization process for pre-damascene structure including metal hard mask
US12/726,347 US8314031B2 (en) 2005-06-16 2010-03-18 Planarization process for pre-damascene structure including metal hard mask

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/160,262 Continuation US7718536B2 (en) 2005-06-16 2005-06-16 Planarization process for pre-damascene structure including metal hard mask

Publications (2)

Publication Number Publication Date
US20100184293A1 true US20100184293A1 (en) 2010-07-22
US8314031B2 US8314031B2 (en) 2012-11-20

Family

ID=37573957

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/160,262 Active 2026-09-15 US7718536B2 (en) 2005-06-16 2005-06-16 Planarization process for pre-damascene structure including metal hard mask
US11/868,538 Abandoned US20080026582A1 (en) 2005-06-16 2007-10-08 Planarization process for pre-damascene structure including metal hard mask
US12/726,347 Expired - Lifetime US8314031B2 (en) 2005-06-16 2010-03-18 Planarization process for pre-damascene structure including metal hard mask

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US11/160,262 Active 2026-09-15 US7718536B2 (en) 2005-06-16 2005-06-16 Planarization process for pre-damascene structure including metal hard mask
US11/868,538 Abandoned US20080026582A1 (en) 2005-06-16 2007-10-08 Planarization process for pre-damascene structure including metal hard mask

Country Status (1)

Country Link
US (3) US7718536B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130178057A1 (en) * 2012-01-11 2013-07-11 Globalfoundries Inc. Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7718536B2 (en) * 2005-06-16 2010-05-18 United Microelectronics Corp. Planarization process for pre-damascene structure including metal hard mask
JP2007081113A (en) * 2005-09-14 2007-03-29 Sony Corp Manufacturing method of semiconductor device
US20080242089A1 (en) * 2007-03-30 2008-10-02 Texas Instruments Incorporated Method for Distributed Processing at Copper CMP
KR20130116099A (en) * 2012-04-13 2013-10-23 삼성전자주식회사 Semiconductor device and method for fabricating the same
US8859430B2 (en) * 2012-06-22 2014-10-14 Tokyo Electron Limited Sidewall protection of low-K material during etching and ashing
US8742587B1 (en) * 2012-11-18 2014-06-03 United Microelectronics Corp. Metal interconnection structure
US11094554B2 (en) * 2017-03-31 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Polishing process for forming semiconductor device structure
US10879115B2 (en) * 2017-11-21 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
US11001733B2 (en) 2019-03-29 2021-05-11 Fujimi Incorporated Compositions for polishing cobalt and low-K material surfaces

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350682B1 (en) * 1998-01-23 2002-02-26 United Microelectronics Corp. Method of fabricating dual damascene structure using a hard mask
US6524962B2 (en) * 2001-05-31 2003-02-25 United Microelectronics Corp. Method for forming dual-damascene interconnect structure
US20040009671A1 (en) * 1998-03-18 2004-01-15 Cabot Microelectronics Corporation Chemical mechanical polishing slurry useful for copper substrates
US7091123B2 (en) * 2001-09-04 2006-08-15 Nec Electronics Corporation Method of forming metal wiring line including using a first insulating film as a stopper film
US7718536B2 (en) * 2005-06-16 2010-05-18 United Microelectronics Corp. Planarization process for pre-damascene structure including metal hard mask

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831013B2 (en) * 2001-11-13 2004-12-14 United Microelectronics Corp. Method of forming a dual damascene via by using a metal hard mask layer
US6713873B1 (en) * 2002-11-27 2004-03-30 Intel Corporation Adhesion between dielectric materials
US7300601B2 (en) * 2002-12-10 2007-11-27 Advanced Technology Materials, Inc. Passivative chemical mechanical polishing composition for copper film planarization
US6919276B2 (en) * 2003-04-24 2005-07-19 Taiwan Semiconductor Manufacturing Co., Ltd Method to reduce dishing and erosion in a CMP process
US20050097825A1 (en) * 2003-11-06 2005-05-12 Jinru Bian Compositions and methods for a barrier removal

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350682B1 (en) * 1998-01-23 2002-02-26 United Microelectronics Corp. Method of fabricating dual damascene structure using a hard mask
US20040009671A1 (en) * 1998-03-18 2004-01-15 Cabot Microelectronics Corporation Chemical mechanical polishing slurry useful for copper substrates
US6524962B2 (en) * 2001-05-31 2003-02-25 United Microelectronics Corp. Method for forming dual-damascene interconnect structure
US7091123B2 (en) * 2001-09-04 2006-08-15 Nec Electronics Corporation Method of forming metal wiring line including using a first insulating film as a stopper film
US7718536B2 (en) * 2005-06-16 2010-05-18 United Microelectronics Corp. Planarization process for pre-damascene structure including metal hard mask

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130178057A1 (en) * 2012-01-11 2013-07-11 Globalfoundries Inc. Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique
US8859418B2 (en) * 2012-01-11 2014-10-14 Globalfoundries Inc. Methods of forming conductive structures using a dual metal hard mask technique

Also Published As

Publication number Publication date
US20060286805A1 (en) 2006-12-21
US20080026582A1 (en) 2008-01-31
US8314031B2 (en) 2012-11-20
US7718536B2 (en) 2010-05-18

Similar Documents

Publication Publication Date Title
US8314031B2 (en) Planarization process for pre-damascene structure including metal hard mask
US20230298900A1 (en) Selective Removal Of An Etching Stop Layer For Improving Overlay Shift Tolerance
US6245663B1 (en) IC interconnect structures and methods for making same
US7871923B2 (en) Self-aligned air-gap in interconnect structures
US6734096B2 (en) Fine-pitch device lithography using a sacrificial hardmask
US7550822B2 (en) Dual-damascene metal wiring patterns for integrated circuit devices
CN100576494C (en) Method for forming dual damascene wiring of semiconductor device using protective via capping layer
KR100755664B1 (en) Methods for forming damasecence wiring structures having line and plug conductors formed from different materials
US7419916B2 (en) Manufacturing method of semiconductor device
US9390967B2 (en) Method for residue-free block pattern transfer onto metal interconnects for air gap formation
KR100641502B1 (en) Contact formation method using dual damascene process in semiconductor device manufacturing
KR20110001894A (en) Interconnect structure with via gouging components and method of manufacturing the same
US6465889B1 (en) Silicon carbide barc in dual damascene processing
US6194313B1 (en) Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process
US6150260A (en) Sacrificial stop layer and endpoint for metal CMP
US6406996B1 (en) Sub-cap and method of manufacture therefor in integrated circuit capping layers
KR100783868B1 (en) Manufacturing Method of Semiconductor Device and Semiconductor Device
JP2001110894A (en) Method for manufacturing electrical connection wiring of semiconductor device
US6459155B1 (en) Damascene processing employing low Si-SiON etch stop layer/arc
US6737348B2 (en) Method for forming buried interconnect
CN100364057C (en) Method and system for metal barrier and seed integration
KR100783989B1 (en) Wiring Formation Method of Semiconductor Device
US20090230557A1 (en) Semiconductor Device and Method for Making Same
KR20080062019A (en) Manufacturing method of semiconductor device
KR20090083773A (en) Metal wiring formation method of semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HSU, CHIA-LIN;REEL/FRAME:026492/0889

Effective date: 20050504

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12