US20100164523A1 - System for testing connections of two connectors - Google Patents
System for testing connections of two connectors Download PDFInfo
- Publication number
- US20100164523A1 US20100164523A1 US12/412,373 US41237309A US2010164523A1 US 20100164523 A1 US20100164523 A1 US 20100164523A1 US 41237309 A US41237309 A US 41237309A US 2010164523 A1 US2010164523 A1 US 2010164523A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
- G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
Definitions
- the disclosure relates to testing of electronic systems, and particularly, to a system for testing connectors.
- a typical connector includes a number of verification pins and a number of signal pins.
- the verification pins are configured for verifying whether two connectors are a matching pair.
- testing of the connections between devices or between the device and the peripheral is performed.
- Current systems for testing connectors only detect whether each pair of verification pins of each of the two connected connectors are electrically connected. If the verification pins are deemed to be electrically connected, the testing of the two connectors is considered as passed.
- it is not uncommon that other pins of the two matching connectors may not be electrically connected, even when electrical connection of each pair of verification pins has been detected. Thus the current testing process would not guarantee the flow of the data across the connection.
- FIG. 1 is functional block diagram of a system for testing connections of two connectors, according to an exemplary embodiment.
- FIG. 2 is a circuit diagram of the system of FIG. 1 .
- each of the two connectors 4 , 5 includes two verification pins 6 and a number of signal pins 7 .
- the connector 4 is a male connector and the connector 5 is a female connector.
- the pins 6 , 7 of the connector 4 are male pins and the pins 6 , 7 of the connector 5 are female pins.
- the roles of the connectors 4 , 5 is not limited to this embodiment but can be interchanged in other alternative embodiments.
- the number of the verification pins 6 is not limited to this embodiment, but depends on the type of the connectors 4 , 5 .
- each of the connectors 4 , 5 may only include only one verification pin 6 .
- the verification pins 6 are configured for identifying whether the two connectors 4 , 5 are a matching pair. In theory, if the two connectors 4 , 5 are a matching pair, when the two connectors 4 , 5 are coupled together, the verification pins 6 correspondingly form electrical connections and data and/or electrical signals can be transmitted between the connectors 4 , 5 .
- the signal pins 7 are configured for transmitting data/signals between the connectors 4 , 5 . In theory, if the two connectors 4 , 5 are a matching pair and coupled together, the signal pins 7 of the connector 4 and the signal pins 7 of the connector 5 will be electrically connected to each other correspondingly. In reality, it is not uncommon for the connector 4 and the connector 5 to be coupled, yet corresponding verification pins 6 and signal pins 7 might be electrically disconnected from each other correspondingly due to, for example, oxidation. Therefore, each pin must be tested for electrical connectivity.
- the system 100 includes a verification testing module 10 , a controlling module 20 , a signal testing module 30 , and a reporting module 40 .
- the verification testing module 10 is configured for testing whether the verification pins 6 of the connector 4 are electrically coupled to the corresponding verification pins 6 of the connector 5 .
- the verification testing module 10 includes a grounding unit 11 , a pull-up unit 12 , and a processing unit 13 .
- the grounding unit 11 is configured for connecting the verification pins 6 of the connector 5 to ground.
- the pull-up unit 12 is configured for pulling the voltage of the verification pins 6 of the connector 4 to “1” (high voltage). However, this pulling is intentionally weak enough that if the verification pin 6 of the connector 4 is electrically coupled to the verification pin 6 of the connector 5 , the voltage of the verification pin 6 of the connector 4 will go to “0” (low voltage level).
- the processing unit 13 is configured for measuring the voltage level of the verification pins 6 of the connector 4 and outputting the results.
- the results may be “00”, “01”, “10”, and “11”. Only result “00” indicates the two pairs of verification pins 6 of the connectors 4 are electrically connected to the corresponding verification pins 6 of the connector 5 .
- the pull-up unit 12 includes a first pull-up resistor R. Typically, the pull-up resistor R has high resistance.
- the controlling module 20 is configured for enabling communications between the signal pins 7 of the connector 4 and the corresponding pins 7 of the connector 5 , if the verification pins 6 of the connectors 4 , 5 have been detected to be electrically coupled to each other, to allow testing of the signal pins 7 .
- the controlling module 20 includes a number of first control switches 21 and a number of second control switches 22 .
- Each first control switch 21 includes a first control terminal 21 a, a first signal terminal 21 b, and a first output terminal 21 c.
- the first control terminals 21 a are connected to the verification testing module 10 .
- the first signal terminals 21 b are connected to inputs of the connector 4 .
- Each first output terminals 21 c forms two branches.
- Each second control switch 22 includes a second control terminal 22 a, a second signal terminal 22 b, and a second output terminal 22 c.
- the second control terminals 22 a are connected to the verification testing module 10 .
- the second signal terminals 22 b are connected to the inputs of the connector 5 .
- Each second output terminal 22 c forms two branches.
- One branch is connected to the signal testing module 30 , and another branch forms a second port 22 d of the corresponding signal pin 7 of the connector 5 .
- the signal testing module 30 is connected to the controlling module 20 and is configured for detecting the voltage level of the signal pins 7 sequentially when the connectors 4 , 5 are connected to each other and communications therebetween are allowed (i.e., testing of the signal pins 7 is allowed).
- the signal testing module 30 includes a first control unit 31 , a second control unit 32 , and a detecting unit 33 .
- the first control unit 31 includes a number of first switches 310 and a first control chip 312 .
- the first control chip 312 is connected to the first switches 310 and to the electrical ground via a pull-down resistor R 1 .
- the first control chip 312 includes a number of control pins.
- Each first switch 310 includes a third control terminal 310 a, a third signal terminal 310 b, and a pull-down terminal 310 c.
- the third control terminals 310 a are connected to the corresponding control pins of the first control chip 312 .
- the third signal terminals 310 b are connected to corresponding first output terminals 21 c.
- the pull-down terminals 310 c are connected to the pull-down resistor R 1 .
- the second control unit 32 includes a number of second switches 320 and a second control chip 322 .
- the second control chip 322 is connected to the second switches 320 and connected to a power source 321 via a second pull-up resistor R 2 .
- the second control chip 322 includes a number of control pins.
- Each second switch 320 includes a fourth control terminal 320 a, a fourth signal terminal 320 b, and a pull-up terminal 320 c.
- the fourth control terminals 320 a are connected to the corresponding control pins of the second control chip 322 .
- the fourth signal terminals 320 b are connected to the corresponding second output terminals 22 c.
- the pull-up terminals 320 c are connected to the second pull-up resistor R 2 .
- the first control chip 312 and the second control chip 322 are programmable chips, both having a sequence control circuit.
- the sequence control circuit is configured for controlling the control pins to output “1” in sequence to a corresponding third control terminal 310 a and fourth control terminal 320 a.
- the detecting unit 33 interconnects the first switches 310 and the pull-down resistor R 1 and is configured for detecting whether each pair of signal pins 7 are electrical connected.
- the detecting unit 33 when communications of all pairs of signal pins 7 are enabled (i.e., all first signal terminals 21 b are connected to the corresponding first output terminal 21 c and all second signal terminals 22 b are connected to the corresponding second output terminal 22 c ) and a pair of signal pins 7 is under testing (i.e., the corresponding third signal terminals 310 b are connected to the corresponding pull-down terminal 21 c and the fourth signal terminals 320 b are connected to the corresponding pull-up terminal 320 c ), if the pair of signal pins 7 are electrically connected, the detecting unit 33 would yields “1”. Otherwise, connection of the pair of signal pins 7 is broken.
- the signal testing module 30 further includes a recording unit 330 and a storage unit 331 .
- the recording unit 330 is configured for recording the result of the processing unit 13 and detecting unit 33 .
- the storage unit 331 is configured for storing the records of the recording unit 330 .
- the reporting module 40 is configured for reading records of testing from the storage unit 331 and outputting the records to users.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
- 1. Technical Field
- The disclosure relates to testing of electronic systems, and particularly, to a system for testing connectors.
- 2. Description of Related Art
- In electronic systems, connectors allow data flow across devices or across a device and its peripherals. A typical connector includes a number of verification pins and a number of signal pins. The verification pins are configured for verifying whether two connectors are a matching pair. During initialization of the electronic systems, testing of the connections between devices or between the device and the peripheral is performed. Current systems for testing connectors only detect whether each pair of verification pins of each of the two connected connectors are electrically connected. If the verification pins are deemed to be electrically connected, the testing of the two connectors is considered as passed. However, it is not uncommon that other pins of the two matching connectors may not be electrically connected, even when electrical connection of each pair of verification pins has been detected. Thus the current testing process would not guarantee the flow of the data across the connection.
- Therefore, it is desirable to provide a system for testing connections of two connectors, which can overcome the limitations described above.
-
FIG. 1 is functional block diagram of a system for testing connections of two connectors, according to an exemplary embodiment. -
FIG. 2 is a circuit diagram of the system ofFIG. 1 . - Referring to
FIGS. 1 and 2 , asystem 100 for fully testing connections of two 4, 5, according to an exemplary embodiment, is disclosed. Each of the twoconnectors 4, 5 includes twoconnectors verification pins 6 and a number ofsignal pins 7. In this embodiment, theconnector 4 is a male connector and theconnector 5 is a female connector. Accordingly, the 6, 7 of thepins connector 4 are male pins and the 6, 7 of thepins connector 5 are female pins. It can be understood that the roles of the 4, 5 is not limited to this embodiment but can be interchanged in other alternative embodiments. Also, the number of theconnectors verification pins 6 is not limited to this embodiment, but depends on the type of the 4, 5. For example, in other alternative embodiments, each of theconnectors 4, 5 may only include only oneconnectors verification pin 6. - The
verification pins 6 are configured for identifying whether the two 4, 5 are a matching pair. In theory, if the twoconnectors 4, 5 are a matching pair, when the twoconnectors 4, 5 are coupled together, theconnectors verification pins 6 correspondingly form electrical connections and data and/or electrical signals can be transmitted between the 4, 5. Theconnectors signal pins 7 are configured for transmitting data/signals between the 4, 5. In theory, if the twoconnectors 4, 5 are a matching pair and coupled together, theconnectors signal pins 7 of theconnector 4 and thesignal pins 7 of theconnector 5 will be electrically connected to each other correspondingly. In reality, it is not uncommon for theconnector 4 and theconnector 5 to be coupled, yetcorresponding verification pins 6 andsignal pins 7 might be electrically disconnected from each other correspondingly due to, for example, oxidation. Therefore, each pin must be tested for electrical connectivity. - The
system 100 includes averification testing module 10, a controllingmodule 20, asignal testing module 30, and areporting module 40. - The
verification testing module 10 is configured for testing whether theverification pins 6 of theconnector 4 are electrically coupled to thecorresponding verification pins 6 of theconnector 5. In this embodiment, theverification testing module 10 includes agrounding unit 11, a pull-up unit 12, and aprocessing unit 13. Thegrounding unit 11 is configured for connecting theverification pins 6 of theconnector 5 to ground. The pull-up unit 12 is configured for pulling the voltage of theverification pins 6 of theconnector 4 to “1” (high voltage). However, this pulling is intentionally weak enough that if theverification pin 6 of theconnector 4 is electrically coupled to theverification pin 6 of theconnector 5, the voltage of theverification pin 6 of theconnector 4 will go to “0” (low voltage level). Therefore, whether each pair of theverification pins 6 of theconnector 4 is electrically connected to theverification pins 6 of theconnector 5 can be determined by measuring the voltage level of theverification pins 6 of theconnector 4. Theprocessing unit 13 is configured for measuring the voltage level of theverification pins 6 of theconnector 4 and outputting the results. In this embodiment, the results may be “00”, “01”, “10”, and “11”. Only result “00” indicates the two pairs ofverification pins 6 of theconnectors 4 are electrically connected to thecorresponding verification pins 6 of theconnector 5. In this embodiment, the pull-up unit 12 includes a first pull-up resistor R. Typically, the pull-up resistor R has high resistance. - The controlling
module 20 is configured for enabling communications between thesignal pins 7 of theconnector 4 and thecorresponding pins 7 of theconnector 5, if theverification pins 6 of the 4, 5 have been detected to be electrically coupled to each other, to allow testing of theconnectors signal pins 7. In detail, the controllingmodule 20 includes a number offirst control switches 21 and a number ofsecond control switches 22. Eachfirst control switch 21 includes afirst control terminal 21 a, afirst signal terminal 21 b, and afirst output terminal 21 c. Thefirst control terminals 21 a are connected to theverification testing module 10. Thefirst signal terminals 21 b are connected to inputs of theconnector 4. Eachfirst output terminals 21 c forms two branches. One branch is connected to thesignal testing module 30, and another branch forms afirst port 21 d of thecorresponding signal pin 7 of theconnector 4. Eachsecond control switch 22 includes asecond control terminal 22 a, asecond signal terminal 22 b, and asecond output terminal 22 c. Thesecond control terminals 22 a are connected to theverification testing module 10. Thesecond signal terminals 22 b are connected to the inputs of theconnector 5. Eachsecond output terminal 22 c forms two branches. One branch is connected to thesignal testing module 30, and another branch forms asecond port 22 d of thecorresponding signal pin 7 of theconnector 5. As such, if the 4, 5 have been electrically connected to each other, and both theconnectors first control terminal 21 a and thesecond control terminal 22 a are “1”, thefirst signal terminal 21 b and thefirst output terminal 21 c are connected to each other, and thesecond signal terminal 22 b and thesecond output terminal 22 c are connected to each other. - The
signal testing module 30 is connected to the controllingmodule 20 and is configured for detecting the voltage level of thesignal pins 7 sequentially when the 4, 5 are connected to each other and communications therebetween are allowed (i.e., testing of theconnectors signal pins 7 is allowed). Thesignal testing module 30 includes afirst control unit 31, asecond control unit 32, and a detectingunit 33. - The
first control unit 31 includes a number offirst switches 310 and afirst control chip 312. Thefirst control chip 312 is connected to thefirst switches 310 and to the electrical ground via a pull-down resistor R1. In detail, thefirst control chip 312 includes a number of control pins. Eachfirst switch 310 includes athird control terminal 310 a, athird signal terminal 310 b, and a pull-down terminal 310 c. Thethird control terminals 310 a are connected to the corresponding control pins of thefirst control chip 312. Thethird signal terminals 310 b are connected to correspondingfirst output terminals 21 c. The pull-down terminals 310 c are connected to the pull-down resistor R1. When athird control terminal 310 a gets “1”, the correspondingthird signal terminal 310 b and the pull-down terminal 310 c are connected to electrically ground thecorresponding signal pin 7. When a third control terminal gets “0”, the correspondingthird signal terminal 310 b and the pull-down terminal 310 c are electrically disconnected. - The
second control unit 32 includes a number ofsecond switches 320 and asecond control chip 322. Thesecond control chip 322 is connected to thesecond switches 320 and connected to apower source 321 via a second pull-up resistor R2. In detail, thesecond control chip 322 includes a number of control pins. Eachsecond switch 320 includes afourth control terminal 320 a, afourth signal terminal 320 b, and a pull-upterminal 320 c. Thefourth control terminals 320 a are connected to the corresponding control pins of thesecond control chip 322. Thefourth signal terminals 320 b are connected to the correspondingsecond output terminals 22 c. The pull-upterminals 320 c are connected to the second pull-up resistor R2. When afourth control terminal 320 a gets “1”, the correspondingfourth signal terminal 320 b and the pull-upterminal 320 c are connected to pull thecorresponding signal pin 7 of theconnector 5 to “1”. When afourth control terminals 320 a gets “0”, the correspondingfourth signal terminal 320 b and the pull-upterminal 320 c are disconnected. - The
first control chip 312 and thesecond control chip 322 are programmable chips, both having a sequence control circuit. The sequence control circuit is configured for controlling the control pins to output “1” in sequence to a correspondingthird control terminal 310 a andfourth control terminal 320 a. - The detecting
unit 33 interconnects thefirst switches 310 and the pull-down resistor R1 and is configured for detecting whether each pair ofsignal pins 7 are electrical connected. In principle, when communications of all pairs ofsignal pins 7 are enabled (i.e., allfirst signal terminals 21 b are connected to the correspondingfirst output terminal 21 c and allsecond signal terminals 22 b are connected to the correspondingsecond output terminal 22 c) and a pair of signal pins 7 is under testing (i.e., the correspondingthird signal terminals 310 b are connected to the corresponding pull-down terminal 21 c and thefourth signal terminals 320 b are connected to the corresponding pull-upterminal 320 c), if the pair ofsignal pins 7 are electrically connected, the detectingunit 33 would yields “1”. Otherwise, connection of the pair of signal pins 7 is broken. - The
signal testing module 30 further includes arecording unit 330 and astorage unit 331. Therecording unit 330 is configured for recording the result of theprocessing unit 13 and detectingunit 33. Thestorage unit 331 is configured for storing the records of therecording unit 330. - The reporting
module 40 is configured for reading records of testing from thestorage unit 331 and outputting the records to users. - While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (10)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810306565 | 2008-12-26 | ||
| CN200810306565.7 | 2008-12-26 | ||
| CN200810306565A CN101769976A (en) | 2008-12-26 | 2008-12-26 | Connector detection system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US7746090B1 US7746090B1 (en) | 2010-06-29 |
| US20100164523A1 true US20100164523A1 (en) | 2010-07-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/412,373 Expired - Fee Related US7746090B1 (en) | 2008-12-26 | 2009-03-27 | System for testing connections of two connectors |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7746090B1 (en) |
| CN (1) | CN101769976A (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101769977A (en) * | 2008-12-30 | 2010-07-07 | 鸿富锦精密工业(深圳)有限公司 | Connector detection system |
| CN102540004A (en) * | 2010-12-08 | 2012-07-04 | 鸿富锦精密工业(深圳)有限公司 | test device |
| CN102608456B (en) * | 2012-03-02 | 2014-08-13 | 华为技术有限公司 | Parallel operation line failure detection device and system |
| CN103076534B (en) * | 2013-01-04 | 2015-04-01 | 常州机电职业技术学院 | Strip connector electrical continuity test method and test circuit |
| KR102086615B1 (en) * | 2013-02-13 | 2020-03-10 | 온세미컨덕터코리아 주식회사 | Jack detector, detecting device, and detecting method |
| CN103529343B (en) * | 2013-03-27 | 2016-04-13 | Tcl集团股份有限公司 | A kind of intelligent diagnosing method of electric equipment and system |
| CN103915732A (en) * | 2014-04-23 | 2014-07-09 | 首都师范大学 | Connector assembly capable of detecting connecting reliability in real time and detection method thereof |
| CN103926503A (en) * | 2014-05-05 | 2014-07-16 | 航天科技控股集团股份有限公司 | Extensible precise position reporting point connection detecting system |
| CN105988902A (en) * | 2015-02-02 | 2016-10-05 | 联想(上海)信息技术有限公司 | Electronic equipment and connection detecting method |
| CN106326153A (en) * | 2015-06-29 | 2017-01-11 | 鸿富锦精密工业(武汉)有限公司 | Interface detection circuit |
| CN105467262A (en) * | 2015-12-23 | 2016-04-06 | 广州视睿电子科技有限公司 | Method and device for detecting connection error of display equipment terminal |
| CN106128342B (en) * | 2016-06-24 | 2019-08-30 | 京东方科技集团股份有限公司 | Array substrate, display device and detection method for array substrate |
| CN107918080B (en) * | 2016-10-11 | 2020-12-18 | 大陆汽车电子(连云港)有限公司 | Sensor connection status detection method, device and sensor |
| CN108804261B (en) * | 2017-05-05 | 2023-05-19 | 中兴通讯股份有限公司 | Connector testing method and device |
| CN109115247B (en) * | 2017-06-26 | 2021-03-02 | 大陆汽车电子(连云港)有限公司 | System and method for monitoring connection between sensor and connector |
| CN109541384B (en) * | 2017-09-22 | 2020-06-26 | 华为技术有限公司 | Device, communication equipment and method for detecting connection state of connector |
| CN111220931A (en) | 2018-11-23 | 2020-06-02 | 华硕电脑股份有限公司 | detection circuit |
| CN110824387B (en) * | 2019-10-25 | 2021-10-26 | 苏州浪潮智能科技有限公司 | Device and method for detecting cable connection |
| CN110907857B (en) * | 2019-12-10 | 2022-05-13 | 上海国微思尔芯技术股份有限公司 | Automatic connector detection method based on FPGA |
| CN111025195B (en) * | 2019-12-19 | 2021-10-19 | 山东爱德邦智能科技有限公司 | a detection circuit |
| CN114578162B (en) * | 2022-03-04 | 2025-08-29 | 上海合见工业软件集团有限公司 | Connector connectivity detection system |
| CN115267619A (en) * | 2022-05-06 | 2022-11-01 | 深圳市国显科技有限公司 | A detection device and detection method of a TP connector |
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| US5670884A (en) * | 1995-06-16 | 1997-09-23 | Yazaki Corporation | Connector testing device |
| US6768314B2 (en) * | 2001-04-18 | 2004-07-27 | Takata Corporation | Method for detecting improper connection of connector |
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Also Published As
| Publication number | Publication date |
|---|---|
| US7746090B1 (en) | 2010-06-29 |
| CN101769976A (en) | 2010-07-07 |
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