[go: up one dir, main page]

US20100155845A1 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

Info

Publication number
US20100155845A1
US20100155845A1 US12/642,760 US64276009A US2010155845A1 US 20100155845 A1 US20100155845 A1 US 20100155845A1 US 64276009 A US64276009 A US 64276009A US 2010155845 A1 US2010155845 A1 US 2010155845A1
Authority
US
United States
Prior art keywords
channel transistor
integrated circuit
transistor
output buffer
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/642,760
Other languages
English (en)
Inventor
Takeo Toba
Kazuo Tanaka
Hiroyasu Ishizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Renesas Electronics Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHIZUKA, HIROYASU, TANAKA, KAZUO, TOBA, TAKEO
Publication of US20100155845A1 publication Critical patent/US20100155845A1/en
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION MERGER Assignors: RENESAS TECHNOLOGY CORP.
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME Assignors: NEC ELECTRONICS CORPORATION
Priority to US13/910,891 priority Critical patent/US9947651B2/en
Priority to US15/918,659 priority patent/US20180197850A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • H10W72/90—
    • H10W72/932—

Definitions

  • the present invention relates to chip area reduction techniques for semiconductor devices, and more particularly to a technique useful for layout area reduction in the “PAD on I/O (Input/Output)” cell structure.
  • pads coupled with bonding wires or the like are overlapped with I/O cells as interfaces with the outside, which is called the “PAD on I/O cell” structure.
  • the output buffer block includes, for example, an output buffer comprised of a P-channel MOS transistor and an N-channel MOS transistor, a first and a second diode for ESD (electrostatic discharge) protection, a first and a second resistance, and an ESD protection circuit.
  • the first and second diodes for ESD protection are coupled in series between the supply voltage and reference potential.
  • One coupling end of the P-channel MOS transistor is coupled with the supply voltage and the other coupling end of the transistor is coupled with one coupling end of the first resistance.
  • the other coupling end of the first resistance is coupled with one coupling end of the second resistance and the other coupling end of the second resistance is coupled with one coupling end of the N-channel MOS transistor.
  • the other coupling end of the N-channel MOS transistor is coupled with the reference potential.
  • the ESD protection circuit is coupled between the supply voltage and reference voltage.
  • a pad is coupled with the junction of the first and second diodes and the junction of the first and second resistances.
  • the above circuit configuration has the following drawback: a pad is coupled with the junction of the first and second resistances and thus the lead part coupled with the pad is forced to lie between these two resistances, and as a consequence, the pad will protrude from the I/O cell and the chip area cannot be reduced effectively.
  • An object of the present invention is to provide a technique that in the “PAD on I/O (Input/Output) cell” structure, the pad lead part is disposed almost in the center of the I/O part (cell) so as to reduce the semiconductor chip layout area.
  • a semiconductor integrated circuit device including a semiconductor chip, in which the semiconductor chip includes a plurality of I/O pads disposed along edges of the semiconductor chip, and a plurality of I/O parts disposed on the semiconductor chip and coupled with any of the I/O pads.
  • the I/O parts each include an output buffer block including an N-channel transistor and a P-channel transistor to form an output buffer and functioning as an interface for output of signals to the outside, and a logic block for controlling the output buffer and an input buffer.
  • the logic block, the N-channel transistor, and the P-channel transistor are arranged toward an edge of the semiconductor chip in order and a pad lead part to be coupled with the I/O pad lies between the logic block and the N-channel transistor.
  • a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the N-channel transistor can have a high resistance.
  • the output buffer block may include a first and a second diode for ESD protection and the first and second diodes may lie between the N-channel transistor and P-channel transistor.
  • the output buffer block may have a resistance for ESD protection and the resistance may lie between the first and second diodes and the P-channel transistor.
  • a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the P-channel transistor can have a high resistance.
  • a semiconductor integrated circuit device including a semiconductor chip, in which the semiconductor chip includes a plurality of I/O pads disposed along edges of the semiconductor chip, and a plurality of I/O parts disposed on the semiconductor chip and coupled with any of the I/O pads.
  • the I/O parts each include an output buffer block including an N-channel transistor and a P-channel transistor to form an output buffer and functioning as an interface for output of signals to the outside, and a logic block which includes an input buffer block functioning as an interface for input of signals from the outside and controls the output buffer and the input buffer.
  • the logic block, the P-channel transistor, and the N-channel transistor are arranged in line in order and a pad lead part to be coupled with the I/O pad lies between the logic block and the P-channel transistor.
  • a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the N-channel transistor can have a high resistance.
  • the output buffer block may include a first and a second diode for ESD protection and the first and second diodes may lie between the N-channel transistor and the P-channel transistor.
  • the output buffer block may have a resistance for ESD protection and the resistance may lie between the first and second diodes and the P-channel transistor.
  • a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the P-channel transistor can have a high resistance.
  • the number of constituent elements of the protection circuit of the output buffer block can be decreased.
  • FIG. 1 illustrates the layout of a semiconductor chip according to a first embodiment of the present invention
  • FIG. 2 illustrates pads and part of an I/O region on the semiconductor chip shown in FIG. 1 in enlarged form
  • FIG. 3 shows an example of the layout of an I/O part on the semiconductor chip shown in FIG. 1 ;
  • FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer block in the I/O part shown in FIG. 3 ;
  • FIG. 5 shows the arrangement of go-round power-supply wires formed in a wiring layer over the I/O part shown in FIG. 3 ;
  • FIG. 6 shows the position of a pad coupled with the I/O part shown in FIG. 3 ;
  • FIG. 7 is a sectional view of the I/O part shown in FIG. 3 ;
  • FIG. 8 is a plan view of a transistor provided in the output buffer block shown in FIG. 3 , combined with a sectional view thereof;
  • FIG. 9 is a circuit diagram of an ordinary I/O part which the present inventors have examined.
  • FIG. 10 shows the layout of the output buffer block in the I/O part shown in FIG. 9 ;
  • FIG. 11 shows comparison between the I/O part according to the first embodiment of the invention and the ordinary I/O part examined by the present inventors in terms of layout
  • FIG. 12 shows the positional relation between I/O parts and pads according to the first embodiment
  • FIG. 13 shows an example of the layout of an I/O part according to another embodiment of the invention.
  • FIG. 14 shows another example of the layout of an I/O part according to another embodiment of the invention.
  • FIG. 15 is a circuit diagram showing an example of the configuration of an output buffer block according to a second embodiment of the present invention.
  • FIG. 16 shows an example of the layout of the output buffer block shown in FIG. 15 ;
  • FIG. 17 shows an example of the layout of an I/O part according to another embodiment of the invention.
  • FIG. 18 shows another example of the layout of an I/O part according to another embodiment of the invention.
  • FIG. 19 shows an example of the layout of an I/O part according to another embodiment of the invention.
  • FIG. 20 shows another example of the layout of an I/O part according to another embodiment of the invention.
  • FIG. 21 is a circuit diagram showing an example of an output buffer block according to a third embodiment of the present invention.
  • FIG. 22 shows an example of the layout of the output buffer block shown in FIG. 21 ;
  • FIG. 23 shows an example of the layout of an output buffer block according to another embodiment of the invention.
  • FIG. 1 illustrates the layout of a semiconductor chip according to a first embodiment of the present invention
  • FIG. 2 illustrates pads and part of an I/O region on the semiconductor chip shown in FIG. 1 in enlarged form
  • FIG. 3 shows an example of an I/O part on the semiconductor chip shown in FIG. 1
  • FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer block in the I/O part shown in FIG. 3
  • FIG. 5 shows the arrangement of go-round power-supply wires formed in a wiring layer over the I/O part shown in FIG. 3
  • FIG. 6 shows the position of a pad coupled with the I/O part in FIG. 3
  • FIG. 7 is a sectional view of the I/O part shown in FIG. 3 ;
  • FIG. 8 is a plan view of a transistor provided in the output buffer block shown in FIG. 3 , combined with a sectional view thereof;
  • FIG. 9 is a circuit diagram of an ordinary I/O part which the present inventors have examined;
  • FIG. 10 shows the layout of the output buffer block in the I/O part shown in FIG. 9 ;
  • FIG. 11 shows comparison between the I/O part according to the first embodiment of the invention and the ordinary I/O part examined by the present inventors in terms of layout; and
  • FIG. 12 shows the positional relation between I/O parts and pads according to the first embodiment.
  • a semiconductor chip 1 which is provided in a semiconductor integrated circuit device has a plurality of pads 2 arranged in lines in four peripheral areas as shown in FIG. 1 , in which the pads are coupled, for example, with bonding wires.
  • a plurality of pads 2 a which also function as I/O pads are arranged in lines, in which the pads 2 and pads 2 a are arranged in two rows and in a staggered pattern.
  • an I/O region 3 as an interface with the outside lies under the pads 2 and 2 a , forming a so-called “PAD on I/O” structure.
  • a core region 4 Located in the center of the semiconductor chip 1 is a core region 4 in which a logic circuit including semiconductor elements such as transistors is formed.
  • FIG. 2 illustrates, in enlarged form, pads 2 and 2 a and part of the I/O region 3 (area indicated by dotted line in FIG. 1 ) in the PAD on I/O structure.
  • a plurality of I/O parts 5 are arranged in a row along each edge of the semiconductor chip 1 and pads 2 and 2 a are arranged in two rows above them in a staggered pattern.
  • the I/O parts 5 and pads 2 and 2 a are each rectangular and the long edge of each of the pads 1 and 2 a is, for example, approximately half of the long edge of the I/O parts 5 .
  • a pad lead part 5 a is formed on one short edge side of each pad 2 (or 2 a ) and the center of the I/O part 5 is coupled with the corresponding pad 2 (or pad 2 a ) through the part lead part 5 a.
  • FIG. 3 shows an example of the layout of the I/O part 5 and FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer block 7 provided in the I/O part 5 .
  • the I/O part 5 includes a logic block 6 and an output buffer block 7 .
  • the logic block 6 includes an ESD protection circuit 6 a (shown in FIG. 4 ), an input buffer block for input buffer, a level shifter for voltage level shift, and an inverter for sending a drive signal to the output buffer block 7 .
  • the output buffer block 7 includes transistors 8 and 9 for output buffer, diodes 10 and 11 for ESD protection, and a resistance 12 for ESD protection.
  • the transistor 8 is a P-channel MOS transistor and the transistor 9 is an N-channel MOS transistor.
  • the diodes 10 and 11 are coupled in series between supply voltage VCCQ and reference potential VSSQ.
  • One coupling end of the transistor 8 is coupled with the supply voltage VCCQ and the other coupling end of the transistor 8 is coupled with one coupling end of the resistance 12 .
  • the other coupling end of the resistance 12 is coupled with one coupling end of the transistor 9 and the other coupling end of the transistor 9 is coupled with the reference potential VSSQ.
  • the junction of the diode 10 , a first diode, and the diode 11 , a second diode, and the junction of the other coupling end of the resistance 12 and the one coupling end of the transistor 9 form an output part for the output buffer block 7 which is coupled with a pad 2 (or pad 2 a ).
  • the transistor 8 is located nearest to the periphery of the semiconductor chip 1 in the I/O part 5 .
  • the resistance 12 lies above the transistor 8 and the diodes 10 and 11 lie above the resistance 12 .
  • the transistor 9 lies above the diodes 10 and 11
  • the logic block 6 lies above the transistor 9 with the pad lead part 5 a , for example, formed in a metal wiring layer between them.
  • FIG. 5 shows the arrangement of go-round power-supply wires formed over the I/O part 5 shown in FIG. 3 .
  • the go-round power-supply wires are arranged as follows: go-round wire for core supply voltage 13 , go-round wire for core reference potential 14 , go-round wires for I/O supply voltage 15 , and go-round wires for I/O reference potential 16 are arranged over the logic block 6 ; and go-round wires for I/O reference potential 17 and go-round wires for I/O supply voltage 18 are arranged over the output buffer block 7 , with the pad lead part 5 a between the two groups of go-round wires.
  • the go-round wire for core supply voltage 13 feeds the supply voltage to the core region 4 and the go-round wire for core reference potential 14 feeds the reference potential to the core region 4 .
  • the go-round wires for I/O supply voltage 15 and 18 feed supply voltage VCCQ to the I/O part 5 and the go-round wires for I/O reference potential 16 and 17 feeds reference potential VSSQ to the I/O part 5 .
  • FIG. 6 shows the position of the pad 2 coupled with the I/O part 5 shown in FIG. 5 .
  • This pad 2 is one of the pads located on the outer side (the peripheral side of the semiconductor chip 1 ) among the pads 2 arranged in a staggered pattern and the pad 2 is in such a position that it does not protrude from the short edge of the I/O part 5 on the peripheral side of the semiconductor chip 1 .
  • FIG. 7 is a sectional view of the I/O part 5 shown in FIG. 3 .
  • the logic block 6 and the transistor 9 , diode 11 and diode 10 , resistance 12 and transistor 8 of the output buffer block 7 are formed from left to right in FIG. 7 .
  • the go-round wire for core supply voltage 13 In the wiring layer lying over the device formation layer, the go-round wire for core supply voltage 13 , the go-round wire for core reference potential 14 , go-round wires for I/O supply voltage 15 , go-round wires for I/O reference potential 16 , go-round wires for I/O reference potential 17 , and go-round wires for I/O supply voltage 18 are formed from left to right in FIG. 7 .
  • the pad lead part 5 a and pad 2 are formed.
  • the pad lead part 5 a and pad 2 are so formed that they lie over the output buffer block 7 formed in the device formation layer.
  • the transistor 9 (indicated by the dotted line circle in FIG. 4 ) is manufactured in a way that a conductive film is not formed in part of the diffusion layer, in order for the drain of the transistor 9 to have a high resistance.
  • FIG. 8 is a plan view of the transistor 9 , combined with a sectional view thereof.
  • a P-well 19 is formed over a semiconductor substrate, and an N+ type semiconductor region 20 functioning as a drain and an N+ type semiconductor region 21 functioning as a source are formed on the right and left over the P-well 19 .
  • a conductive film which is a metal silicide 22 such as cobalt silicide or nickel silicide.
  • a metal silicide 23 is formed over the N+ type semiconductor region 20 as well, though the region 20 is not all covered by the metal silicide 23 unlike the N+ type semiconductor region 21 and the metal silicide 23 is only formed over part of the region 20 which is coupled with a via 25 for coupling with a wire 24 formed in the overlying wiring layer.
  • the sheet resistance can be increased, for example, to a level approximately 10 to 50 times higher than when a metal silicide is formed all over the N+ type semiconductor region 20 .
  • a gate 26 is formed over the P-well 19 through an insulating film such as silicon oxide.
  • the drain terminal can have a high resistance so that the transistor 9 is protected from ESD.
  • FIG. 9 is a circuit diagram of an ordinary I/O part 50 which the present inventors have examined.
  • the I/O part 50 (shown in FIG. 10 ) includes a logic block 51 ( FIG. 10 ) and an output buffer block 52 .
  • the logic block 51 includes an ESD protection circuit, an input buffer block for input buffer, a level shifter for voltage level shift, and an inverter for sending a drive signal to the output buffer block 52 .
  • the output buffer block 52 includes transistors 53 and 54 for output buffer, diodes 55 and 56 for ESD protection, and resistances 57 and 58 for ESD protection.
  • the transistor 53 is a P-channel MOS transistor and the transistor 54 is an N-channel MOS transistor.
  • the diodes 55 and 56 are coupled in series between supply voltage VCCQ and reference potential VSSQ.
  • One coupling end of the transistor 53 is coupled with the supply voltage VCCQ and the other coupling end of the transistor 53 is coupled with one coupling end of the resistance 57 .
  • the other coupling end of the resistance 57 is coupled with one coupling end of the resistance 58 and the other coupling end of the resistance 58 is coupled with one coupling end of the transistor 54 .
  • the other coupling end of the transistor 54 is coupled with the reference potential VSSQ.
  • the junction of the diode 55 and diode 56 and the junction of the resistance 53 and resistance 54 are coupled with a pad lead part 59 which forms an output part for the output buffer block 52 .
  • FIG. 10 shows the layout of the output buffer block 52 in the I/O part 50 shown in FIG. 9 .
  • the logic block 51 lies in an upper part of the figure and the transistor 54 of the output buffer block 52 lies below the logic block 51 .
  • the resistance 58 lies below the transistor 54 and the diode 56 lies below the resistance 58 .
  • the diode 55 lies below the diode 56 with the pad lead part 59 between them.
  • the resistance 57 lies below the diode 55 and the transistor 53 lies below the resistance 57 .
  • the pad lead part 59 to be coupled with a pad 60 can only be placed between the resistance 57 and resistance 58 and as a consequence, the pad lead part 59 should be located off the center of the I/O part 50 , resulting in a protrusion from the short edge of the I/O part 50 as shown on the left in FIG. 11 . This leads to a larger semiconductor chip.
  • the structure of the transistor 9 shown in FIG. 8 eliminates the need for a resistance equivalent to the resistance 58 and permits the pad 2 (or pad 2 a ) through the drain of the transistor 9 to be on the same node, so the pad lead part 5 a can be disposed almost in the center of the I/O part 5 as shown on the right in FIG. 11 .
  • the pads 2 on the outer side (on the peripheral side of the semiconductor chip 1 ) among the pads arranged in a staggered pattern can be moved toward the center of the semiconductor chip 1 and the inner pads 2 a located nearer to the center of the semiconductor chip 1 than the pads 2 can be moved toward the outer peripheral side of the semiconductor chip 1 .
  • the pads 2 and 2 a can be located inside the I/O part 5 without the need for decreasing the size of the pads 2 and 2 a.
  • the diodes 10 and 11 and the resistance 12 are placed between the transistors 8 and 9 , so the distance between the transistors 8 and 9 can be increased, so latch-up phenomena due to parasitic thyristors (SCR) is prevented and the reliability is improved.
  • the protection circuit in the output buffer block 7 can be smaller.
  • the pads 2 and 2 a are arranged in an overlaid manner, so as not to protrude from the I/O part 5 , the chip area of the semiconductor chip 1 can be decreased, making it possible to realize a smaller and low-cost semiconductor integrated circuit device.
  • transistor 9 diode 11 , diode 10 , resistance 12 and transistor 8 are arranged in order from top to bottom when seen in the plan view of FIG. 3 in the first embodiment, the order of arrangement may be altered.
  • the layout of the output buffer block may be altered as follows: the diode 11 , diode 10 , transistor 9 , resistance 12 , and transistor 8 are arranged from top to bottom as shown in FIG. 13 or the diode 10 , transistor 9 , diode 11 , resistance 12 , and transistor 8 are arranged from top to bottom as shown in FIG. 14 .
  • FIG. 15 is a circuit diagram showing an example of the configuration of an output buffer block 7 according to a second embodiment of the present invention and FIG. 16 shows an example of the layout of the output buffer block shown in FIG. 15 .
  • the semiconductor chip 1 is the same as the one shown in FIG. 1 in the aforementioned embodiment except the structure of the output buffer block 7 provided in the I/O part 5 .
  • the output buffer block 7 includes diodes 10 and 11 and transistors 8 a and 9 .
  • the diodes 10 and 11 are coupled in series between supply voltage VCCQ and reference potential VSSQ.
  • One coupling end of the transistor 8 a a P-channel MOS transistor, is coupled with the supply voltage VCCQ and the other coupling end of the transistor 8 a is coupled with one coupling end of the transistor 9 , an N-channel MOS transistor.
  • the other coupling end of the transistor 9 is coupled with the reference potential VSSQ.
  • the junction of the diode 10 and diode 11 , and the junction of the transistor 8 a and transistor 9 form an output part for the output buffer block 7 which is coupled with a pad 2 or pad 2 a.
  • a metal silicide film is not formed over part of the upper surface of the N+ type semiconductor region which functions as a drain, so that the drain terminal has a high resistance.
  • the drain terminal of the transistor 8 a can have the same function as the resistance 12 ( FIG. 4 ), the resistance 12 is no longer needed.
  • FIG. 16 illustrates an example of the layout of the I/O part 5 .
  • the logic block 6 lies in an upper part of the figure and the transistor 9 lies below the logic block 6 with the pad lead part 5 a between them.
  • the diodes 10 and 11 lie below the transistor 9
  • the transistor 8 a lies below the diodes.
  • the pad lead part 5 a can be located almost in the center of the I/O part 5 , so the chip area of the semiconductor chip 1 ( FIG. 1 ) can be smaller. This also eliminates the need for the resistance 12 ( FIG. 4 ), which means that the circuit of the output buffer block 7 can be even smaller.
  • the layout of the output buffer block 7 as shown in FIG. 16 may be varied as follows: for example, as show in FIG. 17 , the diodes 11 and 10 lie between the transistor 8 a and transistor 9 and their positions are reversed or as shown in FIG. 18 , the diodes 10 and 11 lie between the logic block 6 and the transistor 9 with the pad lead part 5 a between them.
  • FIG. 19 Another possible layout of the output buffer block 7 is that as shown in FIG. 19 , the pad lead part 5 a lies between the diodes 11 and 10 and the transistor 9 or as shown in FIG. 20 , the pad lead part 5 a lies between the diode 11 and diode 10 .
  • FIG. 21 is a circuit diagram showing an example of an output buffer block according to a third embodiment of the present invention and FIG. 22 shows an example of the layout of the output buffer block shown in FIG. 21 .
  • the circuit of the output buffer block includes a resistance 27 in addition to the diodes 10 and 11 and transistors 8 a and 9 included in the second embodiment as shown in FIG. 15 .
  • One coupling end of the resistance 27 is coupled with the junction of the diodes 10 and 11 and the other coupling end of the resistance 27 is coupled with the junction of the transistor 8 a and transistor 9 .
  • the other elements are coupled in the same way as those in the second embodiment as shown in FIG. 15 .
  • FIG. 22 illustrates an example of the layout of the I/O part 5 .
  • the logic block 6 When seen in the plan view ( FIG. 22 ), in the I/O part 5 , the logic block 6 lies in an upper part of the figure and the diode 10 and diode 11 lie below the logic block 6 with the pad lead part 5 a between the logic block and the diodes.
  • the resistance 27 lies below the diode 11 and the transistor 9 lies below the resistance 27 , and the transistor 8 lies below the transistor 9 .
  • the pad lead part 5 a can be located almost in the center of the I/O part 5 , so the chip area of the semiconductor chip 1 ( FIG. 1 ) can be smaller.
  • the layout of the output buffer block 7 as shown in FIG. 22 may be varied as follows: for example, as shown in FIG. 23 , the positions of the transistor 8 a and transistor 9 are reverse to those shown in FIG. 22 .
  • the present invention is suitable as a chip area reduction technique for semiconductor integrated circuit devices with a “PAD on I/O (Input/Output)” cell structure.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
US12/642,760 2008-12-19 2009-12-18 Semiconductor integrated circuit device Abandoned US20100155845A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/910,891 US9947651B2 (en) 2008-12-19 2013-06-05 Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal
US15/918,659 US20180197850A1 (en) 2008-12-19 2018-03-12 Semiconductor integrated circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-323589 2008-12-19
JP2008323589A JP2010147282A (ja) 2008-12-19 2008-12-19 半導体集積回路装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/910,891 Continuation US9947651B2 (en) 2008-12-19 2013-06-05 Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal

Publications (1)

Publication Number Publication Date
US20100155845A1 true US20100155845A1 (en) 2010-06-24

Family

ID=42264782

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/642,760 Abandoned US20100155845A1 (en) 2008-12-19 2009-12-18 Semiconductor integrated circuit device
US13/910,891 Active US9947651B2 (en) 2008-12-19 2013-06-05 Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal
US15/918,659 Abandoned US20180197850A1 (en) 2008-12-19 2018-03-12 Semiconductor integrated circuit device

Family Applications After (2)

Application Number Title Priority Date Filing Date
US13/910,891 Active US9947651B2 (en) 2008-12-19 2013-06-05 Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal
US15/918,659 Abandoned US20180197850A1 (en) 2008-12-19 2018-03-12 Semiconductor integrated circuit device

Country Status (3)

Country Link
US (3) US20100155845A1 (zh)
JP (1) JP2010147282A (zh)
TW (2) TWI496225B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2901477A4 (en) * 2012-09-26 2016-07-06 Baysand Inc FLEXIBLE AND SPACE-SAVING INPUT / OUTPUT CIRCUIT FOR INTEGRATED CIRCUITS
TWI582940B (zh) * 2016-06-20 2017-05-11 台灣類比科技股份有限公司 積體電路及其具自我靜電保護的輸出緩衝器佈局結構
CN106935583A (zh) * 2011-10-18 2017-07-07 瑞萨电子株式会社 半导体集成电路器件
CN107564902A (zh) * 2016-07-01 2018-01-09 台湾类比科技股份有限公司 集成电路及其具自我静电保护的输出缓冲器布局结构
US10861851B2 (en) 2011-12-30 2020-12-08 Intel Corporation Wrap-around trench contact structure and methods of fabrication
US20230139094A1 (en) * 2021-10-29 2023-05-04 Renesas Electronics Corporation Semiconductor device
US11824055B2 (en) 2019-11-06 2023-11-21 Socionext Inc. Semiconductor integrated circuit device
US12376384B2 (en) 2021-04-08 2025-07-29 Socionext Inc. Semiconductor integrated circuit device

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012104552A (ja) * 2010-11-08 2012-05-31 Panasonic Corp 半導体集積回路
JP6248635B2 (ja) * 2011-11-08 2017-12-20 ソニー株式会社 センサ装置、解析装置および記憶媒体
EP3312875B1 (en) * 2015-06-19 2025-04-30 Renesas Electronics Corporation Semiconductor device
JP6118923B2 (ja) * 2016-01-26 2017-04-19 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP6793025B2 (ja) * 2016-12-07 2020-12-02 日立オートモティブシステムズ株式会社 半導体装置
JP2018186144A (ja) * 2017-04-25 2018-11-22 株式会社村田製作所 半導体装置及びパワーアンプモジュール
JP7724190B2 (ja) * 2021-10-29 2025-08-15 ルネサスエレクトロニクス株式会社 半導体装置
JPWO2024047820A1 (zh) * 2022-08-31 2024-03-07

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060001101A1 (en) * 2004-07-02 2006-01-05 Shigeru Hirata Semiconductor device
US20070120258A1 (en) * 2005-11-30 2007-05-31 Renesas Technology Corp. Semiconductor device
US20080111255A1 (en) * 2006-11-09 2008-05-15 Daisuke Matsuoka Semiconductor integrated circuit and multi-chip module
US20080303093A1 (en) * 2007-06-05 2008-12-11 Kabushiki Kaisha Toshiba Semiconductor apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1070266A (ja) * 1996-08-26 1998-03-10 Nec Corp 半導体装置およびその製造方法
JP3147849B2 (ja) 1998-03-06 2001-03-19 日本電気株式会社 半導体集積回路装置の保護回路
US6444511B1 (en) * 2001-05-31 2002-09-03 Taiwan Semiconductor Manufacturing Company CMOS output circuit with enhanced ESD protection using drain side implantation
JP2005243907A (ja) * 2004-02-26 2005-09-08 Renesas Technology Corp 半導体装置
EP1577507A1 (de) * 2004-03-01 2005-09-21 Alstom Technology Ltd Kraftanlage mit Kohlefeuerung
JP2007042718A (ja) * 2005-08-01 2007-02-15 Renesas Technology Corp 半導体装置
JP2007227665A (ja) * 2006-02-23 2007-09-06 Ricoh Co Ltd 半導体集積回路装置
KR100773097B1 (ko) * 2006-08-22 2007-11-02 삼성전자주식회사 패드를 갖는 반도체 소자
JP5264135B2 (ja) 2006-11-09 2013-08-14 パナソニック株式会社 半導体集積回路及びマルチチップモジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060001101A1 (en) * 2004-07-02 2006-01-05 Shigeru Hirata Semiconductor device
US20070120258A1 (en) * 2005-11-30 2007-05-31 Renesas Technology Corp. Semiconductor device
US20080111255A1 (en) * 2006-11-09 2008-05-15 Daisuke Matsuoka Semiconductor integrated circuit and multi-chip module
US20080303093A1 (en) * 2007-06-05 2008-12-11 Kabushiki Kaisha Toshiba Semiconductor apparatus

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106935583A (zh) * 2011-10-18 2017-07-07 瑞萨电子株式会社 半导体集成电路器件
US10861851B2 (en) 2011-12-30 2020-12-08 Intel Corporation Wrap-around trench contact structure and methods of fabrication
US11776959B2 (en) 2011-12-30 2023-10-03 Intel Corporation Wrap-around trench contact structure and methods of fabrication
US12426360B2 (en) 2011-12-30 2025-09-23 Intel Corporation Wrap-around trench contact structure and methods of fabrication
EP2901477A4 (en) * 2012-09-26 2016-07-06 Baysand Inc FLEXIBLE AND SPACE-SAVING INPUT / OUTPUT CIRCUIT FOR INTEGRATED CIRCUITS
TWI582940B (zh) * 2016-06-20 2017-05-11 台灣類比科技股份有限公司 積體電路及其具自我靜電保護的輸出緩衝器佈局結構
CN107564902A (zh) * 2016-07-01 2018-01-09 台湾类比科技股份有限公司 集成电路及其具自我静电保护的输出缓冲器布局结构
US11824055B2 (en) 2019-11-06 2023-11-21 Socionext Inc. Semiconductor integrated circuit device
US12376384B2 (en) 2021-04-08 2025-07-29 Socionext Inc. Semiconductor integrated circuit device
US20230139094A1 (en) * 2021-10-29 2023-05-04 Renesas Electronics Corporation Semiconductor device
US12464826B2 (en) * 2021-10-29 2025-11-04 Renesas Electronics Corporation Semiconductor device

Also Published As

Publication number Publication date
US9947651B2 (en) 2018-04-17
TWI496225B (zh) 2015-08-11
TW201029079A (en) 2010-08-01
TW201532162A (zh) 2015-08-16
JP2010147282A (ja) 2010-07-01
US20130264647A1 (en) 2013-10-10
TWI593031B (zh) 2017-07-21
US20180197850A1 (en) 2018-07-12

Similar Documents

Publication Publication Date Title
US9947651B2 (en) Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal
US10692856B2 (en) Semiconductor integrated circuit device
US6721933B2 (en) Input/output cell placement method and semiconductor device
US5347150A (en) Semiconductor input/output circuits operating at different power supply voltages
US8653641B2 (en) Integrated circuit device
CN1822366B (zh) 半导体器件
CN101471340A (zh) 半导体集成电路
US6552594B2 (en) Output buffer with improved ESD protection
US20110051299A1 (en) Semiconductor integrated circuit
US20080237645A1 (en) Semiconductor device
JPWO2016110905A1 (ja) 半導体装置及びその設計方法
JP5008840B2 (ja) 半導体装置
WO2021090471A1 (ja) 半導体集積回路装置
JP2000252363A (ja) 半導体集積回路
JP5604602B2 (ja) 半導体集積回路装置
JP2010161158A (ja) 半導体集積回路装置
JP4892143B2 (ja) 半導体装置
US20100006891A1 (en) Semiconductor thyristor device
JP5916820B2 (ja) 半導体集積回路装置
JP4175155B2 (ja) 半導体装置
US20070200140A1 (en) Electrostatic protection device for semiconductor circuit for decreasing input capacitance
KR100639221B1 (ko) 반도체회로용 정전기 보호소자
US20250192045A1 (en) Semiconductor integrated circuit device
US8039965B2 (en) Semiconductor device with reduced layout area having shared metal line between pads
KR20060106105A (ko) 패드 아래에 형성된 ｅｓｄ 회로를 구비하는 반도체 장치및 그 제조 방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: RENESAS TECHNOLOGY CORP.,JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TOBA, TAKEO;TANAKA, KAZUO;ISHIZUKA, HIROYASU;SIGNING DATES FROM 20091001 TO 20091007;REEL/FRAME:023687/0584

AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:024864/0635

Effective date: 20100401

Owner name: NEC ELECTRONICS CORPORATION, JAPAN

Free format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024879/0190

Effective date: 20100401

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION