US20100109087A1

US20100109087A1 - Multichannel Metal Oxide Semiconductor (MOS) Transistors

Info

Publication number: US20100109087A1
Application number: US12/687,613
Authority: US
Inventors: Kyoung-hwan Yeo; Dong-gun Park; Jeong-Dong Choe
Original assignee: Individual
Current assignee: Individual
Priority date: 2003-05-15
Filing date: 2010-01-14
Publication date: 2010-05-06
Also published as: US7670912B2; US20040227181A1; KR100471173B1; KR20040098673A

Abstract

Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.

Description

CLAIM FOR PRIORITY RELATED APPLICATION

This application is a continuation of U.S. application Ser. No. 10/797,463, filed Mar. 10, 2004, which claims priority from Korean Patent Application No. 2003-30883, filed May 15, 2003, the disclosures of which are hereby incorporated herein by reference as if set forth in their entirety.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and methods of fabricating the same and, more specifically, to metal oxide semiconductor (MOS) transistors and methods of fabricating the same.

BACKGROUND OF THE INVENTION

As integrated circuit devices become more highly integrated, the overall size of metal oxide semiconductor (MOS) transistors have become smaller and channel lengths of the MOS transistors have also been reduced. Accordingly, short channel MOS transistors may experience a punch-through phenomenon that may cause large leakage currents between source and drain regions of the transistor. In addition, source and drain junction capacitances and gate capacitances may also increase. Thus, it may be difficult to provide high performance, low power integrated circuit devices.
To address the problems with MOS transistors discussed above, silicon on insulator (SOI) technology using a SOI substrate has been introduced. A SOI substrate typically includes a supporting substrate, an insulating layer on the supporting substrate and a silicon layer on the insulating layer. SOI devices may provide low junction leakage currents, reduction in frequency of punch-through, low operation voltage and high efficiency in device isolation. However, heat generated from SOI devices during operation may not be efficiently conducted to the supporting substrate due to the insulating layer between the supporting substrate and the silicon layer. Accordingly, temperatures of SOI devices may increase and thereby degrade the overall characteristics of the device. Furthermore, SOI devices may experience a floating body effect that may cause a parasitic bipolar transistor action and complex manufacturing techniques may be used to remove the floating body effect. Accordingly, improved integrated circuit devices and methods of fabricating integrated circuit devices may be desired.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a unit cell of a metal oxide semiconductor (MOS) transistor, the unit cell including an integrated circuit substrate a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions.
In some embodiments of the present invention, the at least two spaced apart horizontal channel regions include an active region on the integrated circuit substrate and at least one epitaxial pattern on the active region and spaced apart from the active region. In certain embodiments of the present invention, the at least one epitaxial pattern includes first and second epitaxial patterns. The second epitaxial pattern may be positioned on the first epitaxial pattern and spaced apart from the first epitaxial pattern. The unit cell may further include a mask pattern on the second epitaxial pattern. The second epitaxial pattern may be directly connected to the mask pattern.
In further embodiments of the present invention, the source and drain regions include vertical source and drain regions. The vertical source region may be positioned on a first side of the horizontal channel region and the vertical drain region may be positioned on a second side of the horizontal channel region. The vertical drain region may also be spaced apart from the source region.
In still further embodiments of the present invention, a gate pattern is provided on the horizontal channel and between the at least two spaced apart horizontal channel regions. A gate insulation layer may also be provided between the gate pattern and the at least two spaced apart horizontal channel regions channel. Source and drain electrodes may be electrically coupled to the vertical source and drain regions, respectively. A first insulation pattern may be provided between the source and drain electrodes and the integrated circuit substrate and between the gate pattern and the integrated circuit substrate.
In some embodiments of the present invention, a mask pattern may be provided on the horizontal channel. The gate pattern may extend between an upper channel region of the at least two spaced apart horizontal channel regions and the mask pattern. A second insulation pattern may also be provided on the horizontal channel and the vertical source and drain regions. The second insulation pattern may define a gate opening on the horizontal channel. The gate pattern may be provided in the gate opening and the source and drain electrodes may extend through the second insulation pattern and be connected to the vertical source drain regions.
In further embodiments of the present invention, a third insulation pattern may be provided on the second insulation pattern and the gate pattern. The source and drain electrodes may extend through the third insulation pattern and the second insulation pattern to be connected to the vertical source and drain regions. An upper surface of the first insulation pattern may be higher relative to a lower surface of the gate pattern.
While the present invention is described above primarily with reference transistors, methods of forming transistors are also provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-section of transistors according to some embodiments of the present invention.

FIG. 1B is a cross-section taken along the line A-A′ of FIG. 1A.

FIG. 1C is a cross-section taken along the line B-B′ of FIG. 1A.

FIG. 1D is cross-section illustrating operations of transistors according to some embodiments of the present invention.

FIGS. 2A through 9A are cross-sections illustrating processing steps in the fabrication of transistors according to some embodiments of the present invention.

FIGS. 2B through 9B are cross-sections taken along the lines A-A′ of FIGS. 2A through 9A illustrating processing steps in the fabrication of transistors according to some embodiments of the present invention.

FIGS. 2C through 9C are cross-sections taken along the line B-B′ of FIGS. 2A through 9A illustrating processing steps in the fabrication of transistors according to some embodiments of the present invention.

FIG. 10A is a cross-section of transistors according to further embodiments of the present invention.

FIG. 10B is a cross-section taken along the line A-A′ of FIG. 10A of transistors according to further embodiments of the present invention.

FIG. 10C is a cross-section taken along the line B-B′ of FIG. 10A of transistors according to further embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will be further understood that when a layer is referred to as being “on” to another layer, it can be directly on the other layer or intervening layers may also be present. It will be further understood that when a layer is referred to as being “directly on” another layer, no intervening layers may be present. Like numbers refer to like elements throughout.
It will be understood that although the terms first and second are used herein to describe various layers or regions, these layers or regions should not be limited by these terms. These terms are only used to distinguish one layer or region from another layer or region. Thus, a first layer or region discussed below could be termed a second layer or region, and similarly, a second layer or region may be termed a first layer or region without departing from the teachings of the present invention.
Embodiments of the present invention will be described below with respect to FIGS. 1A through 10C. Embodiments of the present invention provide unit cells of metal oxide semiconductor (MOS) transistors that include a horizontal channel having at least two spaced apart channel regions. Thus, when a gate voltage is applied to a gate electrode, at least two channels are formed at the at least two spaced apart horizontal channel regions. MOS transistors according to some embodiments of the present invention may provide increased driving currents regardless of the dimensions of the transistor due to the multiple channels corresponding to the at least two spaced apart horizontal channel regions. Accordingly, improved MOS transistors may be provided according to embodiments of the present invention as discussed further below.
Referring now to FIGS. 1A through 1C, cross-sections of transistors according to embodiments of the present invention will be discussed. FIG. 1A is a cross-section of transistors according to some embodiments of the present invention. FIG. 1B is a cross-section taken along the line A-A′ of FIG. 1A. Similarly, FIG. 1C is a cross-section taken along the line B-B′ of FIG. 1A. As illustrated in FIGS. 1A, 1B and 1C, a MOS transistor is provided on an integrated circuit substrate 10. The transistor includes a source region 52 s, a drain region 52 d and a gate 34 (gate pattern). The gate 34 is provided between the source region 52 s and the drain region 52 d. A horizontal channel is provided between the source and drain regions 52 s and 52 d and includes at least two spaced apart horizontal channel regions 14 a and 50. The source and drain regions 52 s and 52 d are vertical source and drain regions 52 s and 52 d. The vertical source region 52 s is provided on a first side of the horizontal channel regions 14 a and 50 and the vertical drain region 52 d is provided on a second side of the horizontal channel regions 14 a and 50 and is spaced apart from the vertical source region 52 s. In embodiments of the present invention illustrated in FIGS. 1A through 1C, the at least two spaced apart horizontal channel regions include an active region 50 and first and second epitaxial patterns 14 a. The active region 50 may be defined by a trench 20. First and second epitaxial patterns 14 a may be stacked sequentially on the integrated circuit substrate and the active region 50.
It will be understood that embodiments of the present invention illustrated in FIGS. 1A through 1C are provided for exemplary purposes only and that embodiments of the present invention are not limited to this configuration. For example, the horizontal channel illustrated in FIGS. 1A through 1C includes an active region 50 and first and second epitaxial patterns 14 a, i.e., three spaced apart horizontal channel regions 50 and 14 a. However, horizontal channels according to some embodiments of the present invention may include two spaced apart horizontal channel regions or more than three horizontal channel regions without departing from the scope of the present invention.
A gate pattern 34 may be provided in a gap region of the horizontal channel regions 14 a and 50. The gate pattern may be provided on the horizontal channel regions 14 a and 50. A gate insulation layer 32 may be provided between the horizontal channel regions 14 a and 50 and the gate pattern 34. A mask pattern 16 a is provided on an upper surface of the second epitaxial pattern 14 a. In other words, the mask pattern 16 a is provided on an upper surface of the last horizontal channel region 14 a in the stack of spaced apart channel regions 50 and 14 a. The mask pattern 16 a is provided between the upper surface of the second epitaxial pattern 14 a and the gate pattern 34. The vertical source and drain regions 52 s and 52 d are electrically coupled to a source electrode 42 s and a drain electrode 42 d, respectively.
In some embodiments of the present invention, a first insulation pattern 22 may be provided between the source and drain electrodes 42 s and 42 d and the integrated circuit substrate 10 to reduce leakage of a current from the source and drain electrodes 42 s and 42 d into the integrated circuit substrate 10. A second insulation pattern 30 may be provided on a surface of the integrated circuit substrate 10, including the horizontal channel regions 14 a and 50 and the vertical source and drain regions 52 s and 52 d. The second insulation pattern 30 may define a gate opening. The gate pattern 34 may be provided in the gate opening using, for example, a damascene process. Furthermore, source and drain electrodes 42 s and 42 d may penetrate the second insulation pattern 30, electrically coupling the source and drain electrodes 42 s and 42 d to the source and drain regions 52 s and 52 d.
A third insulation pattern 36 may be provided on the second insulation pattern 30. In embodiments of the present invention including the third insulation pattern 36, the third insulation pattern 36 may electrically insulate an interconnection connected to source and drain electrodes 42 s and 42 d and the gate pattern 34. Furthermore, an etch stop layer 26 may be provided between a lower surface of the second insulation pattern 30 and the first insulation pattern 22. The etch stop layer 26 may reduce the likelihood that the first insulation pattern 22 will be over etched during a process of forming the source and drain electrodes 42 s and 42 d. The etch stop layer 26 may also reduce the likelihood that the first insulation pattern 22 will be over etched during a process of forming the gate opening 28.
Referring now to FIG. 1D, a cross-section illustrating operations of transistors according to embodiments of the present invention will be discussed. As illustrated in FIG. 1D, a source voltage Vs and a drain voltage Vd are applied to a source 52 s and a drain 52 d, respectively. When a gate voltage Vg is applied to a gate electrode 34 g, a channel (CH) is formed at the horizontal channel regions 14 a and 50. In particular, a channel is formed at the active region 50 and the first and second epitaxial patterns 14 a. Accordingly, transistors according to some embodiments of the present invention, may provide increased driving currents regardless of the dimensions of the transistor due to the multiple channels that are formed at the at least two spaced apart horizontal channel regions.
Referring now to FIGS. 2A through 9C, cross-sections illustrating processing steps in the fabrication of transistors according to embodiments of the present invention will be discussed. FIGS. 2A through 9A are cross-sectional views illustrating processing steps in the fabrication of transistors according to some embodiments of the present invention. FIGS. 2B through 9B are cross-sections taken along the line A-A′ of FIGS. 2A through 9A. FIGS. 2C through 9C are cross-sections taken along the line B-B′ of FIGS. 2A through 9A.
Referring now to FIGS. 2A through 2C, a stacked layer 18 is formed on the integrated circuit substrate 10. In particular, a first epitaxial layer 12 is formed on the integrated circuit substrate. A second epitaxial layer 14 is formed on the first epitaxial layer 12. As illustrated in FIGS. 2B and 2C, a second set of first and second epitaxial layers 12 and 14 may be provided on the first set of first and second epitaxial layers 12 and 14. It will be understood that although embodiments of the present invention are discussed herein as including two sets of first and second epitaxial layers 12 and 14 on the integrated circuit substrate, embodiments of the present invention are not limited to this configuration. For example, three or more sets of first and second epitaxial layers may be provided on the integrated circuit substrate 10 without departing from the scope of the present invention. The first epitaxial layer 12 may include a material, for example, silicon germanium, having high etch selectivity relative the integrated circuit substrate 10, which includes, for example, silicon. The second epitaxial layer 14 may include a material similar to the material making up the integrated circuit substrate 10, for example, silicon. Finally, the stacked layer 18 may include a mask layer 16 formed on the second epitaxial layer 14 of the upper most set of first and second epitaxial layers 12 and 14. The second epitaxial layer or layers 14 may be doped by implanting impurities into the stacking the second epitaxial layer or layers 14 after forming the stacking structure 18 or during the formation of the sets of first and second epitaxial layers 12 and 14.
Referring now to FIGS. 3A through 3C, the stacked layer 18 and the integrated circuit substrate 10 are patterned to form a trench 20 and a stacked pattern 18 a. The trench 20 defines an active region 50 of the integrated circuit substrate 10. The stacked pattern 18 a is formed on the active region 50. The stacked pattern 18 a includes first and second sets of first and second epitaxial patterns 12 a and 14 a, which are alternately stacked on the active region 50. As illustrated in FIGS. 3B and 3C, the stacked pattern 18 a may further include a mask pattern 16 a.
Referring now to FIGS. 4A through 4C, a first insulation pattern 22 is formed on a floor of the trench 20. The first insulation pattern 22 may be formed by providing an insulation layer on a surface of the integrated circuit substrate 10 and recessing the insulation layer. Accordingly, the first insulation pattern 22 is provided on the integrated circuit substrate around the stacked pattern 18 a. The first insulation pattern 22 may be formed by recessing the first insulation layer 22 until the first epitaxial pattern 12 a is exposed. As illustrated in FIGS. 4B and 4C, a bottom surface of the active region may be low relative to an upper surface of the first insulation pattern 22. However, in some embodiments of the present invention, a bottom surface of the active region can be high relative to the upper surface of the first insulation pattern 22 without departing from the scope of the present invention.
Referring now to FIGS. 5A through 5C, a third epitaxial layer 24 may be formed on the surface of the stacked pattern 18 a and the exposed surface of the integrated circuit substrate 10 using, for example, a selective epitaxial growth (SEG) process. In embodiments of the present invention including a mask pattern 16 a as part of the stacked pattern, the third epitaxial layer 24 may be formed on the sidewalls of the stacked pattern 18 a where the second epitaxial patterns 14 a are exposed. The third epitaxial layer 24 may include a material having an etch selectivity with respect to the first epitaxial pattern 12 a and a similar material as the second epitaxial pattern 14 a. For example, the third epitaxial layer 24 may include silicon.
Source and drain regions may be formed by implanting impurities into the third epitaxial layer 24. It will be understood that the source and drain regions may be formed in a subsequent process using, for example, conformal concentration using an oblique ion implantation. An etch stop layer 26 is formed on a surface of the integrated circuit substrate 10. The presence of the etch stop layer 26 may reduce the likelihood of over etching the first insulation pattern 22. The etch stop layer 26 may include, for example, silicon nitride.
Referring now to FIGS. 6A through 6C, a second insulation pattern 30 may be formed on the surface of the integrated circuit substrate 10. The second insulation layer 30 may be patterned to form a gate opening 28 on the stacked pattern 18 a. In some embodiments of the present invention, the etch stop layer 26 may be patterned after the second insulation pattern 30 is patterned. Accordingly, the gate opening 28 may expose a portion of the mask pattern 16 a, the third epitaxial layer 24 and the first insulation pattern 22.
Referring now to FIGS. 7A through 7C, the third epitaxial layer 24 may be removed in the gate opening 28 to expose a portion of the first epitaxial patterns 12 a and the second epitaxial patterns 14 a. The first epitaxial patterns 12 a are etched using, for example, an isotropic etch process, thereby removing the first epitaxial patterns 12 a from the stacked pattern 18 a. Accordingly, the second epitaxial patterns 14 a are provided on the active region 50 and spaced apart from the active region 50. Upper surfaces of the active region 50 and the second epitaxial patterns 14 a may provide a channel of the transistor.
A gate insulation layer 32 is formed on surface of the channel of the transistor. In other words, the gate insulation layer 32 is formed on a surface of the active region 50 and surfaces of the second epitaxial patterns 14 a. The gate insulation layer 32 can be formed conformally using, for example, a thermal process or a chemical vapor deposition (CVD) method.
Referring now to FIGS. 8A through 8C, a gate pattern 34 is provided in the gate opening 28 by, for example, using a damascene process. In particular, a polysilicon layer may be formed on a surface of the second insulation pattern 30 and in the gate opening 28. The polysilicon layer may be planarized to form the gate pattern 34. In some embodiments of the present invention, the polysilicon layer may be formed in the gate opening 28 and a metal silicide layer may be formed on the resultant structure. The metal silicide layer may be planarized to form the gate pattern 34. The gate pattern 34 is formed on the mask pattern 16 a and in the gap region between the channel regions 50 and 14 a. In further embodiments of the present invention, after forming a polysilicon gate pattern 34, a silicide layer may be formed by, for example, performing a silicidation process on an exposed surface of the gate pattern 34. The channel of the transistor can be formed on surfaces of the second epitaxial patterns 14 a and the active region 50 opposite to the gate pattern 34.
Referring now to FIGS. 9A through 9C, a third insulation pattern 36 is formed on a surface of the integrated circuit substrate including the gate pattern 34. The third insulation pattern 36 and the etch stop layer 26 may be patterned to expose the third epitaxial layer 24 to form a source contact hole 40 s on a first side of the gate pattern 34 and a drain contact hole 40 d on a second side of the gate pattern and spaced apart from the source contact hole 40 s. In some embodiments of the present invention, the third epitaxial layer 24 may not be doped. Thus, in these embodiments of the present invention, impurities may be implanted through the source and drain contact holes 40 s and 40 d.
The presence of the first insulation pattern 22 on the floor of the source and drain contact holes 40 s and 40 d may reduce the likelihood that the integrated circuit substrate will be over etched during the formation of the source and drain contact holes 40 s and 40 d. A conductive layer is provided in the source and drain contact holes 40 s and 40 d to provide source and drain electrodes 42 s and 42 d (FIGS. 1B and 1C), respectively. The source and drain electrodes 42 s and 42 d are electrically coupled to the third epitaxial layer 24.
Referring now to FIGS. 10A through 10C, cross-sections of transistors according to further embodiments of the present invention will be discussed. FIG. 10B is a cross-section taken along the line A-A′ of FIG. 10A. FIG. 10C is a cross-section taken along the line B-B′ of FIG. 10A. Like reference numerals refer to like elements discussed above with respect to FIGS. 1A through 9C and, thus, details with respect to the like elements will not be repeated herein.
As illustrated in FIGS. 10A through 10C, a trench 20 (FIGS. 3B and 3C) is provided on the integrated circuit substrate 10. Similar to the first embodiment, the transistor includes a horizontal channel having at least two spaced apart horizontal channel regions 14 a and 50 and vertical source and drain regions 52 s and 52 d (FIGS. 1A and 1B). Different from embodiments of the present invention discussed above with respect to FIGS. 2A through 9C, the upper most layer of the at least two horizontal channel regions 14 a and 50 are vertically isolated by a mask pattern 16 a. The gate pattern 34 is provided in a gap region between the horizontal channel regions 14 a and between upper most layer of the horizontal channel region and the mask pattern 16 a. The gate pattern 34 is provided on the horizontal channel regions 14 a and 50. The gate insulation layer 32 is provided between the horizontal channel regions 14 a and 50 and the gate pattern 34. However, different from embodiments of the present invention discussed above, a channel can be formed on an upper surface of the upper most layer of the horizontal channel region.
Transistors according to some embodiments of the present invention illustrated in FIGS. 10A through 10C may be formed using processing steps similar to those discussed above with respect to FIGS. 2A through 9C. However, in embodiments of the present invention illustrated in FIGS. 10A through 10C, the upper most layer of the stacked layer (18 of FIGS. 2A, 2B and 2C) is formed of a material having low etch selectivity relative to the integrated circuit substrate. As a result, the upper most layer of the stacked pattern is removed separating the mask pattern 16 a from the horizontal channel region 14 a.
As briefly discussed above with respect to FIGS. 1A through 10C, embodiments of the present invention provide a transistor having a channel including at least two channel horizontal channel regions. High driving currents may be used in transistors according to embodiments of the present invention based on the number of layers of horizontal channel regions. Accordingly, transistors according to embodiments of the present invention may provide high driving currents without increasing the dimensions of the transistor. Accordingly, more highly integrated devices may possibly be fabricated.
Furthermore, as discussed above, transistors according to embodiments of the present invention include vertical source and drain regions. Accordingly, the surface dimension of the source and drain regions is wide relative to conventional transistors even though the junction depth of the source and drain regions has been reduces. Therefore, the resistance of transistors according to embodiments of the present invention can be reduced. Finally, the presence of an etch stop layer may reduce damage caused to the integrated circuit substrate during the process of forming the source and drain contact holes, thus, a leakage current may be reduced.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. A unit cell of a metal oxide semiconductor (MOS) transistor, comprising:

an integrated circuit substrate;

a MOS transistor on the integrated circuit substrate, the MOS transistor having a vertical source region, a vertical drain region and a plurality of gates, the plurality of gates being between the vertical source region and the vertical drain region; and

a horizontal channel between the vertical source and drain regions, the horizontal channel including at least two spaced apart horizontal channel regions,

wherein widths of the plurality of gates contacted to the at least two horizontal channel regions are identical.

2. The unit cell of claim 1, wherein the at least two spaced apart horizontal channel region comprise:

an active region on the integrated circuit substrate; and

at least one epitaxial pattern on the active region and spaced apart from the active region.

3. The unit cell of claim 2, wherein the at least one epitaxial pattern comprises first and second epitaxial patterns, the second epitaxial pattern being on the first epitaxial pattern and spaced apart from the first epitaxial pattern, the unit cell further comprising:

a mask pattern on the second epitaxial pattern.

4. The unit cell of claim 3, wherein the second epitaxial pattern is directly connected to the mask pattern.

5. The unit cell of claim 1, wherein the source and drain regions comprise vertical source and drain regions, the vertical source region being on a first side of the horizontal channel region and the vertical drain region being on a second side of the horizontal channel region and spaced apart from the vertical source region.

6. The unit cell of claim 5, further comprising:

a gate pattern on the horizontal channel and between the at least two spaced apart horizontal channel regions; and

a gate insulation layer between the gate pattern and the at least two spaced apart horizontal channel regions.

7. The unit cell of claim 3, further comprising:

a source electrode electrically coupled to the vertical source region;

a drain electrode electrically coupled to the vertical drain region; and

a first insulation pattern between the source and drain electrodes and the integrated circuit substrate and between the gate pattern and the integrated circuit substrate.

8. The unit cell of claim 7, wherein the gate pattern extends between an upper channel region of the at least two spaced apart horizontal channel regions and the mask pattern.

9. The unit cell of claim 8, further comprising:

a second insulation pattern on the horizontal channel and the vertical source and drain regions, wherein the second insulation pattern defines a gate opening on the horizontal channel, wherein the gate pattern is provided in the gate opening and wherein the source and drain electrodes extend through the second insulation pattern and are connected to the vertical source drain regions.

10. The unit cell of claim 9, further comprising:

a third insulation pattern on the second insulation pattern and the gate pattern, wherein the source and drain electrodes extend through the third insulation pattern and the second insulation pattern and are connected to the vertical source and drain regions.

11. The unit cell of claim 10, wherein an upper surface of the first insulation pattern is higher relative to a lower surface of the gate pattern.

12. A unit cell of a metal oxide semiconductor (MOS) transistor, comprising:

an integrated circuit substrate including a trench and an active region higher than the trench, the active region protruding from the integrated circuit substrate to function as a horizontal channel;

the horizontal channel between a vertical source region and a vertical drain region, the horizontal channel including at least two single crystalline horizontal channel regions formed in spaced apart patterns, and further including the active region higher than the trench;

a plurality of gates between at least two single crystalline horizontal channel regions, wherein widths of the plurality of gates that contact the at least two single crystalline horizontal channel regions are substantially identical;

the vertical source region and the vertical drain region in other patterns at one side of the spaced apart patterns, respectively, wherein the vertical source and drain regions extend along sides of the at least two horizontal channel regions and sides of the active region protruding from the integrated circuit substrate; and

a vertical source electrode contacted to a side of the vertical source region and a vertical drain electrode contacted to a side of the vertical drain region.

13. A transistor comprising:

an integrated circuit substrate including a trench region to define an active region and a device insulation layer on a floor of the trench region;

a horizontal channel including a plurality of spaced apart channel layers on the active region, wherein widths of the plurality of spaced apart channel layers are substantially identical;

a gate pattern on the horizontal channel, the gate pattern including a plurality of gates simultaneously formed between the plurality of spaced apart channel layers;

a pair of junctions including a vertical source region and a vertical drain region on the device isolation layer; and

a vertical source electrode and a vertical drain electrode on the device isolation layer, the vertical source electrode contacting to a side of the source region and the vertical drain electrode contacting to a side of the drain region.

14. The transistor of claim 13, wherein an upper surface of the device isolation layer is lower relative to the active region.

15. The transistor of claim 13, wherein the pair of junction covers sides of the active region and sides of the plurality of spaced apart channel layers.

16. The transistor of claim 13, wherein the plurality of spaced apart channel layers are single crystalline.

17. The transistor of claim 13, wherein the horizontal channel comprises at least one gap region, in which at least one gate is formed, between the plurality of spaced apart channel layers.