US20100044237A1 - Method for manufacturing printed circuit boards - Google Patents
Method for manufacturing printed circuit boards Download PDFInfo
- Publication number
- US20100044237A1 US20100044237A1 US12/426,276 US42627609A US2010044237A1 US 20100044237 A1 US20100044237 A1 US 20100044237A1 US 42627609 A US42627609 A US 42627609A US 2010044237 A1 US2010044237 A1 US 2010044237A1
- Authority
- US
- United States
- Prior art keywords
- electrically conductive
- metal layer
- layer
- conductive metal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000007772 electroless plating Methods 0.000 claims abstract description 7
- 238000009713 electroplating Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 239000011230 binding agent Substances 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0346—Deburring, rounding, bevelling or smoothing conductor edges
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
Definitions
- the present disclosure generally relates to printed circuit boards, and particularly, relates to a method for manufacturing printed circuit boards (PCBs).
- PCBs printed circuit boards
- a through hole metalizing process is employed in a traditional method for manufacturing double-sided PCBs or multilayer PCBs to establish electrical connection between circuits of different layers.
- the through hole metalizing process generally includes a step of filling electrically conductive material into a through hole of a PCB substrate having a base and two copper layers formed on opposite surfaces of the base. As such, the conductive material electrically connects the copper layers to each other.
- the thermal expansion index of the electrically conductive material may be different from that of the copper layers.
- interspaces are formed between the conductive material and the PCB substrate.
- etchant may be lodged into the interspaces and corrode the PCB substrate.
- FIG. 1 is a flow chart showing a method for manufacturing a PCB according to a first embodiment.
- FIG. 2 is a cross-sectional view of a substrate defining a through hole according to the first embodiment.
- FIG. 3 is similar to FIG. 2 , but showing a protecting layer is applied on an outer surface of the substrate with the through hole exposed.
- FIG. 4 is similar to FIG. 3 , but showing a first electrically conductive metal layer formed on an inner surface of the substrate defined in the though hole.
- FIG. 5 is similar to FIG. 4 , but showing a second electrically conductive metal layer formed on the first electrically conductive metal layer and the through hole completely filled by the second electrically conductive metal layer.
- FIG. 6 is similar to FIG. 5 , but showing the protecting layer removed.
- FIG. 7 is similar to FIG. 6 , but showing two ends of the second electrically conductive metal layer smoothened.
- FIG. 8 is a cross-sectional view of a substrate defining a blind hole according to a second embodiment.
- FIG. 9 is similar to FIG. 8 , but showing a first electrically conductive metal layer formed on an inner surface defined in the through hole and an outer surface of the substrate.
- FIG. 10 is similar to FIG. 9 , but showing a protecting layer applied on an outer surface of the substrate.
- FIG. 11 is similar to FIG. 10 , but showing a second electrically conductive metal layer formed in the blind hole and the blind hole is filled by the second electrically conductive metal layer.
- FIG. 12 is similar to FIG. 11 , but showing the protecting material attached on the first electrically conductive metal layer removed.
- FIG. 13 is similar to FIG. 12 , but showing a portion of the first electrically conductive metal layer formed on the outer surface removed.
- a method for manufacturing a PCB provided in a first embodiment includes the following steps.
- a double-sided substrate 10 is provided.
- the substrate 10 includes a base 13 , a first electrically conductive layer 11 and a second electrically conductive layer 12 formed on two opposite surfaces of the base 13 .
- the first conductive layer 11 has a first outer surface 111
- the second conductive layer 12 has a second outer surface 121 .
- the substrate 10 defines a through hole 101 therein passing through the first, second conductive layers 11 , 12 and the base 13 , and has an inner surface 1011 in the through hole 101 .
- the base 13 is an insulating resin layer, and the first conductive layer 11 and the second conductive layer 12 are made of copper.
- the thickness of the first conductive layer 11 and the second conductive layer 12 is less than or equal to 10 micrometers, and the diameter of the through hole 101 is in the range from 50 micrometers to 100 micrometers.
- the base 13 can be an overlapping structure of a unit including an insulating resin layer and two conductive layers disposed on two opposite surfaces of the resin layer.
- step 2 as shown in FIG. 4 , a first electrically conductive metal layer 20 is formed on the inner surface 1011 of the substrate 10 using an electro-less plating process.
- a protecting layer 31 is applied onto and fully cover each of the first and second outer surfaces 111 , 121 of the substrate 10 except the through hole 101 .
- the two protecting layers 31 are configured for protecting the first and second conductive layers 11 , 13 from being plated.
- the two protecting layers 31 are dry photoresist films attached on the substrate 10 using a laminating process.
- the two protecting layers 31 can be liquid photoresist layers applied using a coating process, or a known binder layer capable of being manually stripped from the substrate 10 .
- the first and second outer surfaces 111 , 112 can be firstly cleared using a lye and secondly etched using a known etchant.
- the substrate 10 is subsequently plated using an electro-less plating process.
- the inner surface 1011 is cleared using a lye and etched to improve an adhesion force of metal layer contained in the electro-less plating process.
- a first electrically conductive metal layer 20 is formed on the inner surface 1011 of the substrate 10 .
- the first electrically conductive metal layer 20 is made of copper and the thickness thereof is general less than 6 micrometers.
- a second electrically conductive metal layer 40 is directly formed on the first electrically conductive metal layer 20 using an electro-plating process until the through hole 101 is entirely filled with the second electrically conductive metal layer 40 .
- a portion of the obtained second electrically conductive metal layer 40 adjacent to the first electrically conductive metal layer 20 is thicker than the central portion thereof.
- the second electrically conductive metal layer 40 defines a first end 41 and an opposite second end 42 . Both the first and second ends 41 , 42 are arc-shaped in cross-section, and respectively extend beyond the first and second outer surfaces 111 , 112 .
- the protecting layers 31 on the substrate 10 are removed using a typical etching process. Thereafter, as shown in FIG. 7 , the second electrically conductive metal layer 40 is smoothened using a roller 90 until both the first and second ends 41 , 42 have a flat end surface. Additionally, when being a binder layer, the protecting layer 31 can be manually stripped, and the second electrically conductive metal layer 40 can be polished.
- both the first and second electrically conductive metal layers 20 , 40 are compact, and have approximate similar thermal expansion indexes to those of the two conductive layers 11 , 12 . Therefore, interspace is prevented from being formed between the two electrically conductive metal layers 20 , 40 and the two conductive layers 11 , 12 , the inner surface 1011 is protected from corrosion in wet process.
- a method for manufacturing a PCB is provided in a second embodiment, differing from the first embodiment is that the substrate 50 defining a blind hole 501 passing through only the first conductive layer 51 and the base 53 , and exposing a portion of the second conductive layer 52 .
- the substrate 50 defines an inner surface 5011 in the blind hole 501 and an outer surface 511 on the first conductive layer 51 .
- the method includes a step of forming a first electrically conductive metal layer 60 on the substrate 50 using an electro-less plating process.
- the first electrically conductive metal layer 60 includes a first portion 61 formed on the outer surface 511 and a second portion 63 formed on the inner surface 5011 defined in the blind hole 501 .
- the method includes a step of applying protecting layers 71 onto the substrate 50 .
- the first portion 61 of the first metal layer 60 and the second conductive layer 52 are covered by the protecting layers 71 while the second portion 63 is exposed.
- the protecting layers 71 are dry photoresist films.
- the protecting layers 71 can be liquid photoresist layers or binder layers.
- the method includes a step of forming a second electrically conductive metal layer 80 on the second portion 63 using an electro-plating process until the blind hole 501 is filled with conductive metal layer 80 .
- the method includes a step of removing a portion of the protecting layer 71 attached on the first portion 61 from the substrate 50 using a typical etching process or by manual stripping. Another portion of the protecting layer 71 attached on the second conductive layer 52 is kept for manufacturing electrical traces in subsequent process using a traditional exposing and developing method. Additionally, when the protecting layers 71 are binder layers, another portion of the protecting layers 71 attached on the second conductive layer 52 should be removed.
- the first portion 61 of the first electrically conductive metal layer 60 is removed. Therefore, the thickness of the first conductive layer 51 remains unchanged.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
- 1. Technical Field
- The present disclosure generally relates to printed circuit boards, and particularly, relates to a method for manufacturing printed circuit boards (PCBs).
- 2. Description of Related Art
- As technology progresses, microphones, portable computers and other electronic products have achieved ever greater levels of miniaturization by the use of double-sided PCBs and multilayer PCBs having via-holes and buried-holes.
- Usually, a through hole metalizing process is employed in a traditional method for manufacturing double-sided PCBs or multilayer PCBs to establish electrical connection between circuits of different layers. The through hole metalizing process generally includes a step of filling electrically conductive material into a through hole of a PCB substrate having a base and two copper layers formed on opposite surfaces of the base. As such, the conductive material electrically connects the copper layers to each other.
- However, the thermal expansion index of the electrically conductive material may be different from that of the copper layers. As a result, because of heating and cooling of the PCB, interspaces are formed between the conductive material and the PCB substrate. Thus, in wet etching process, etchant may be lodged into the interspaces and corrode the PCB substrate.
- What is needed, therefore, is a method for manufacturing a printed circuit board to overcome the above-described problem.
- Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the different views.
-
FIG. 1 is a flow chart showing a method for manufacturing a PCB according to a first embodiment. -
FIG. 2 is a cross-sectional view of a substrate defining a through hole according to the first embodiment. -
FIG. 3 is similar toFIG. 2 , but showing a protecting layer is applied on an outer surface of the substrate with the through hole exposed. -
FIG. 4 is similar toFIG. 3 , but showing a first electrically conductive metal layer formed on an inner surface of the substrate defined in the though hole. -
FIG. 5 is similar toFIG. 4 , but showing a second electrically conductive metal layer formed on the first electrically conductive metal layer and the through hole completely filled by the second electrically conductive metal layer. -
FIG. 6 is similar toFIG. 5 , but showing the protecting layer removed. -
FIG. 7 is similar toFIG. 6 , but showing two ends of the second electrically conductive metal layer smoothened. -
FIG. 8 is a cross-sectional view of a substrate defining a blind hole according to a second embodiment. -
FIG. 9 is similar toFIG. 8 , but showing a first electrically conductive metal layer formed on an inner surface defined in the through hole and an outer surface of the substrate. -
FIG. 10 is similar toFIG. 9 , but showing a protecting layer applied on an outer surface of the substrate. -
FIG. 11 is similar toFIG. 10 , but showing a second electrically conductive metal layer formed in the blind hole and the blind hole is filled by the second electrically conductive metal layer. -
FIG. 12 is similar toFIG. 11 , but showing the protecting material attached on the first electrically conductive metal layer removed. -
FIG. 13 is similar toFIG. 12 , but showing a portion of the first electrically conductive metal layer formed on the outer surface removed. - Referring to
FIGS. 1-7 , a method for manufacturing a PCB provided in a first embodiment includes the following steps. - In
step 1, as shown inFIG. 2 , a double-sided substrate 10 is provided. Thesubstrate 10 includes a base 13, a first electricallyconductive layer 11 and a second electricallyconductive layer 12 formed on two opposite surfaces of the base 13. The firstconductive layer 11 has a firstouter surface 111, and the secondconductive layer 12 has a secondouter surface 121. Thesubstrate 10 defines a throughhole 101 therein passing through the first, second 11, 12 and the base 13, and has anconductive layers inner surface 1011 in the throughhole 101. - The base 13 is an insulating resin layer, and the first
conductive layer 11 and the secondconductive layer 12 are made of copper. For purpose of manufacturing thin electrical traces, the thickness of the firstconductive layer 11 and the secondconductive layer 12 is less than or equal to 10 micrometers, and the diameter of thethrough hole 101 is in the range from 50 micrometers to 100 micrometers. Additionally, the base 13 can be an overlapping structure of a unit including an insulating resin layer and two conductive layers disposed on two opposite surfaces of the resin layer. - In
step 2, as shown inFIG. 4 , a first electricallyconductive metal layer 20 is formed on theinner surface 1011 of thesubstrate 10 using an electro-less plating process. - In detail, as shown in
FIG. 3 , a protectinglayer 31 is applied onto and fully cover each of the first and second 111, 121 of theouter surfaces substrate 10 except the throughhole 101. The two protectinglayers 31 are configured for protecting the first and secondconductive layers 11, 13 from being plated. In the present embodiment, the two protectinglayers 31 are dry photoresist films attached on thesubstrate 10 using a laminating process. Additionally, the two protectinglayers 31 can be liquid photoresist layers applied using a coating process, or a known binder layer capable of being manually stripped from thesubstrate 10. Furthermore, for purpose of improving adhesion force between the protectinglayers 31 and the first, second 11, 12, prior to applying the protectingconductive layers layers 31 onto thesubstrate 10, the first and secondouter surfaces 111, 112 can be firstly cleared using a lye and secondly etched using a known etchant. - As shown in
FIG. 4 , thesubstrate 10 is subsequently plated using an electro-less plating process. In actual operation, before plating, theinner surface 1011 is cleared using a lye and etched to improve an adhesion force of metal layer contained in the electro-less plating process. Hence, a first electricallyconductive metal layer 20 is formed on theinner surface 1011 of thesubstrate 10. The first electricallyconductive metal layer 20 is made of copper and the thickness thereof is general less than 6 micrometers. - In
step 3, as shown inFIG. 5 , a second electricallyconductive metal layer 40 is directly formed on the first electricallyconductive metal layer 20 using an electro-plating process until thethrough hole 101 is entirely filled with the second electricallyconductive metal layer 40. In actual operation, a portion of the obtained second electricallyconductive metal layer 40 adjacent to the first electricallyconductive metal layer 20 is thicker than the central portion thereof. In the present embodiment, the second electricallyconductive metal layer 40 defines afirst end 41 and an oppositesecond end 42. Both the first and 41, 42 are arc-shaped in cross-section, and respectively extend beyond the first and secondsecond ends outer surfaces 111, 112. - As shown in
FIG. 6 , the protectinglayers 31 on thesubstrate 10 are removed using a typical etching process. Thereafter, as shown inFIG. 7 , the second electricallyconductive metal layer 40 is smoothened using aroller 90 until both the first and 41, 42 have a flat end surface. Additionally, when being a binder layer, the protectingsecond ends layer 31 can be manually stripped, and the second electricallyconductive metal layer 40 can be polished. - In the present embodiment, both the first and second electrically
20, 40 are compact, and have approximate similar thermal expansion indexes to those of the twoconductive metal layers 11, 12. Therefore, interspace is prevented from being formed between the two electricallyconductive layers 20, 40 and the twoconductive metal layers 11, 12, theconductive layers inner surface 1011 is protected from corrosion in wet process. - Referring to
FIGS. 8-12 , a method for manufacturing a PCB is provided in a second embodiment, differing from the first embodiment is that thesubstrate 50 defining ablind hole 501 passing through only the first conductive layer 51 and thebase 53, and exposing a portion of the secondconductive layer 52. Thesubstrate 50 defines aninner surface 5011 in theblind hole 501 and anouter surface 511 on the first conductive layer 51. - As shown in
FIG. 9 , the method includes a step of forming a first electricallyconductive metal layer 60 on thesubstrate 50 using an electro-less plating process. The first electricallyconductive metal layer 60 includes afirst portion 61 formed on theouter surface 511 and asecond portion 63 formed on theinner surface 5011 defined in theblind hole 501. - As shown in
FIG. 10 , the method includes a step of applying protectinglayers 71 onto thesubstrate 50. Thefirst portion 61 of thefirst metal layer 60 and the secondconductive layer 52 are covered by the protectinglayers 71 while thesecond portion 63 is exposed. The protecting layers 71 are dry photoresist films. Alternatively, the protectinglayers 71 can be liquid photoresist layers or binder layers. - As showing in
FIG. 11 , the method includes a step of forming a second electricallyconductive metal layer 80 on thesecond portion 63 using an electro-plating process until theblind hole 501 is filled withconductive metal layer 80. - Referring to
FIG. 12 , the method includes a step of removing a portion of the protectinglayer 71 attached on thefirst portion 61 from thesubstrate 50 using a typical etching process or by manual stripping. Another portion of the protectinglayer 71 attached on the secondconductive layer 52 is kept for manufacturing electrical traces in subsequent process using a traditional exposing and developing method. Additionally, when the protecting layers 71 are binder layers, another portion of the protecting layers 71 attached on the secondconductive layer 52 should be removed. - Referring to
FIGS. 12˜13 , thefirst portion 61 of the first electricallyconductive metal layer 60 is removed. Therefore, the thickness of the first conductive layer 51 remains unchanged. - While certain embodiments have been described and exemplified above, various other embodiments will be apparent to those skilled in the art from the foregoing disclosure. The present invention is not limited to the particular embodiments described and exemplified but is capable of considerable variation and modification without departure from the scope of the appended claims.
Claims (14)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008103040448A CN101657072B (en) | 2008-08-19 | 2008-08-19 | Circuit board manufacturing method |
| CN200810304044.8 | 2008-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20100044237A1 true US20100044237A1 (en) | 2010-02-25 |
Family
ID=41695342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/426,276 Abandoned US20100044237A1 (en) | 2008-08-19 | 2009-04-19 | Method for manufacturing printed circuit boards |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20100044237A1 (en) |
| CN (1) | CN101657072B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI557544B (en) * | 2015-06-24 | 2016-11-11 | 碁鼎科技秦皇島有限公司 | Heat sink, manufacturing method thereof and electronic device |
| KR20190012075A (en) * | 2017-07-26 | 2019-02-08 | 삼성전기주식회사 | Printed circuit board |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104659017A (en) * | 2013-11-20 | 2015-05-27 | 宏启胜精密电子(秦皇岛)有限公司 | Medium board and manufacturing method thereof |
| CN105789938B (en) * | 2014-12-23 | 2020-08-04 | 南京中兴软件有限责任公司 | Rack internal power supply method, bus type power supply board and communication equipment |
| CN107404804B (en) * | 2016-05-20 | 2020-05-22 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and method of making the same |
| CN112770518A (en) * | 2019-10-21 | 2021-05-07 | 深南电路股份有限公司 | Circuit board and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6039889A (en) * | 1999-01-12 | 2000-03-21 | Fujitsu Limited | Process flows for formation of fine structure layer pairs on flexible films |
| US20030178229A1 (en) * | 2001-03-14 | 2003-09-25 | Yukihiko Toyoda | Multilayered printed wiring board |
| US20040078970A1 (en) * | 2001-02-23 | 2004-04-29 | Keiichi Naitoh | Method of manufacturing flexible wiring board |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5891606A (en) * | 1996-10-07 | 1999-04-06 | Motorola, Inc. | Method for forming a high-density circuit structure with interlayer electrical connections method for forming |
| JP2002076617A (en) * | 2000-08-28 | 2002-03-15 | Matsushita Electric Works Ltd | Method for manufacturing printed circuit board and printed circuit board |
| JP2006179822A (en) * | 2004-12-24 | 2006-07-06 | Cmk Corp | Printed wiring board and manufacturing method thereof |
| CN101192542A (en) * | 2006-11-22 | 2008-06-04 | 全懋精密科技股份有限公司 | Circuit board structure and manufacturing method thereof |
-
2008
- 2008-08-19 CN CN2008103040448A patent/CN101657072B/en active Active
-
2009
- 2009-04-19 US US12/426,276 patent/US20100044237A1/en not_active Abandoned
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6039889A (en) * | 1999-01-12 | 2000-03-21 | Fujitsu Limited | Process flows for formation of fine structure layer pairs on flexible films |
| US20040078970A1 (en) * | 2001-02-23 | 2004-04-29 | Keiichi Naitoh | Method of manufacturing flexible wiring board |
| US20030178229A1 (en) * | 2001-03-14 | 2003-09-25 | Yukihiko Toyoda | Multilayered printed wiring board |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI557544B (en) * | 2015-06-24 | 2016-11-11 | 碁鼎科技秦皇島有限公司 | Heat sink, manufacturing method thereof and electronic device |
| KR20190012075A (en) * | 2017-07-26 | 2019-02-08 | 삼성전기주식회사 | Printed circuit board |
| JP2019029636A (en) * | 2017-07-26 | 2019-02-21 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | Printed circuit board |
| KR102421980B1 (en) * | 2017-07-26 | 2022-07-18 | 삼성전기주식회사 | Printed circuit board |
| JP7148052B2 (en) | 2017-07-26 | 2022-10-05 | サムソン エレクトロ-メカニックス カンパニーリミテッド. | printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101657072B (en) | 2011-12-21 |
| CN101657072A (en) | 2010-02-24 |
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