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US20090315086A1 - Image sensor and cmos image sensor - Google Patents

Image sensor and cmos image sensor Download PDF

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Publication number
US20090315086A1
US20090315086A1 US12/486,495 US48649509A US2009315086A1 US 20090315086 A1 US20090315086 A1 US 20090315086A1 US 48649509 A US48649509 A US 48649509A US 2009315086 A1 US2009315086 A1 US 2009315086A1
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electrode
located under
gate electrode
impurity
impurity region
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Mamoru Arimoto
Kaori Misawa
Hayato Nakashima
Ryu Shimizu
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Assigned to SANYO ELECTRIC CO., LTD. reassignment SANYO ELECTRIC CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAKASHIMA, HAYATO, ARIMOTO, MAMORU, MISAWA, KAORI, SHIMIZU, RYU
Publication of US20090315086A1 publication Critical patent/US20090315086A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements

Definitions

  • the present invention relates to an image sensor and a CMOS image sensor, and more particularly, it relates to an image sensor and a CMOS image sensor each comprising a charge increasing portion for increasing signal charges.
  • An image sensor comprising a charge increasing portion (electron increasing portion) for increasing signal charges is known in general.
  • An image sensor comprising an electron storage portion for storing electrons (signal charges), a storage gate electrode for storing the electrons in the electron storage portion, an electron increasing portion for impact-ionizing and increasing (multiplying) the electrons stored in the electron storage portion, a multiplier gate electrode for forming an electric field increasing the electrons by impact-ionization on the electron increasing portion, a transfer gate electrode provided between the storage gate electrode and the multiplier gate electrode, and an impurity region for forming a path through which electrons are transferred, provided under the multiplier gate electrode, the transfer gate electrode and the storage gate electrode is disclosed.
  • electrons are repeatedly transferred between the electron storage portion and the electron increasing portion, thereby increasing the electrons.
  • An image sensor comprises a charge storage portion for storing signal charges, a first electrode for applying a voltage to the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion by impact-ionization, a second electrode for applying a voltage to the charge increasing portion, a third electrode for transferring the signal charges, provided between the first electrode and the second electrode and an impurity region of a first conductive type for forming a path through which the signal charges are transferred, provided on portions located under at least the first electrode, the second electrode and the third electrode, wherein an impurity concentration of a region of the impurity region corresponding to the portion located under the second electrode is higher than an impurity concentration of a region of the impurity region corresponding to the portion located under the third electrode.
  • a CMOS image sensor comprises a charge storage portion for storing signal charges, a first electrode for applying a voltage to the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion by impact-ionization, a second electrode for applying a voltage to the charge increasing portion, a third electrode for transferring the signal charges, provided between the first electrode and the second electrode and an impurity region of a first conductive type for forming a path through which the signal charges are transferred, provided on portions located under at least the first electrode, the second electrode and the third electrode, wherein the charge storage portion, the charge increasing portion, the first electrode, the second electrode and the third electrode are provided in one pixel, and an impurity concentration of a region of the impurity region corresponding to the portion located under the second electrode is higher than an impurity concentration of a region of the impurity region corresponding to the portion located under the third electrode.
  • FIG. 1 is a plan view showing an overall structure of a CMOS image sensor according to a first embodiment of the present invention
  • FIGS. 2 and 3 are sectional views showing the structure of the CMOS image sensor according to the first embodiment of the present invention
  • FIG. 4 is a plan view showing a pixel of the CMOS image sensor according to the first embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing a circuit structure of the CMOS image sensor according to the first embodiment of the present invention.
  • FIG. 6 is a signal waveform diagram for illustrating electron transferring and multiplying operations of the CMOS image sensor according to the first embodiment of the present invention
  • FIG. 7 is a potential diagram for illustrating the electron transferring and multiplying operations of the CMOS image sensor according to the first embodiment of the present invention.
  • FIG. 8 is a signal waveform diagram for illustrating electron transferring and multiplying operations of the CMOS image sensor according to the first embodiment of the present invention
  • FIG. 9 is a potential diagram for illustrating the electron transferring and multiplying operations of the CMOS image sensor according to the first embodiment of the present invention.
  • FIG. 10 is a diagram showing a profile of an impurity implanted into a buried layer according to the first embodiment of the present invention.
  • FIG. 11 is a diagram showing a potential in the vicinity of an interface between a gate insulating film and a buried layer according to the first embodiment of the present invention.
  • FIG. 12 is a potential diagram in a CMOS image sensor according to a second embodiment of the present invention.
  • FIGS. 13 and 14 are potential diagrams for illustrating electron transferring and multiplying operations of the CMOS image sensor according to the second embodiment of the present invention.
  • the first embodiment of the present invention is applied to an active CMOS image sensor employed as an exemplary image sensor.
  • the CMOS image sensor according to the first embodiment comprises an imaging portion 51 including a plurality of pixels 50 arranged in the form of a matrix, a row selection register 52 and a column selection register 53 , as shown in FIG. 1 .
  • element isolation regions 2 for isolating the pixels 50 from each other are formed on a surface of a p-type well region 1 formed on a surface of an n-type silicon substrate 100 , as shown in FIGS. 2 and 3 .
  • the n-type silicon substrate 100 is an example of the “semiconductor substrate” in the present invention.
  • a photodiode (PD) portion 4 and a floating diffusion (FD) region 5 consisting of an n-type impurity region are formed at a prescribed interval, to hold a buried layer 3 consisting of an n ⁇ -type and n-type impurity regions therebetween.
  • the buried layer 3 is an example of the “impurity region” in the present invention.
  • the photodiode portion 4 is an example of the “photoelectric conversion portion” in the present invention
  • the FD region 5 is an example of the “voltage conversion portion” in the present invention.
  • a peak concentration of the impurity in the region (electron multiplying portion 3 a ) of the buried layer 3 located under a multiplier gate electrode 8 is higher than a peak concentration of the impurity in each of regions of the buried layer 3 located under remaining electrodes other than the multiplier gate electrode 8 . More specifically, the peak concentration of the impurity in each of the portions of the buried layer 3 located under the remaining electrodes other than the multiplier gate electrode 8 is about 8.5 ⁇ 10 16 cm ⁇ 3 , while the peak concentration of the impurity in the portion (electron multiplying portion 3 a ) of the buried layer 3 located under the multiplier gate electrode 8 is about 2.5 ⁇ 10 17 cm ⁇ 3 .
  • arsenic is implanted as the impurity.
  • a potential of the portion of the buried layer 3 located under the multiplier gate electrode 8 is rendered higher than that of the portion of the buried layer 3 located under each of the remaining electrodes other than the multiplier gate electrode 8 , when the same level signals are supplied (the same voltages are applied) to the electrodes respectively.
  • the PD portion 4 has a function of generating electrons in response to the quantity of incident light and storing the generated electrons, and is formed to be adjacent to the corresponding element isolation region 2 as well as to the buried layer 3 .
  • the FD region 5 has a function of holding signal charges formed by transferred electrons and converting the signal charges to a voltage.
  • the FD region 5 is formed to be adjacent to the corresponding buried layer 3 .
  • a gate insulating film 6 made of SiO 2 is formed on an upper surface of the buried layer 3 .
  • the transfer gate electrode 7 , the multiplier gate electrode 8 , the transfer gate electrode 9 , the storage gate electrode 10 and the read gate electrode 11 are formed in this order from a side of the PD portion 4 toward a side of the FD region 5 .
  • a reset gate electrode 12 is formed through the gate insulating film 6 to be adjacent to the FD region 5 , and a reset drain region (RD region) 13 is formed to be opposed to the FD region 5 with the reset gate electrode 12 therebetween.
  • the electron multiplying portion 3 a is provided on the portion of the buried layer 3 located under the multiplier gate electrode 8
  • an electron storage portion 3 b is provided on the portion of the buried layer 3 located under the storage gate electrode 10 .
  • the transfer gate electrode 7 , the multiplier gate electrode 8 , the transfer gate electrode 9 , the storage gate electrode 10 and the read gate electrode 11 are examples of the “fourth electrode”, the “second electrode”, the “third electrode”, the “first electrode” and the “fifth electrode” in the present invention.
  • the electron multiplying portion 3 a is an example of the “charge increasing portion” in the present invention.
  • the electron storage portion 3 b is an example of the “charge storage portion” in the present invention.
  • wiring layers 20 , 21 , 22 , 23 and 24 supplying clock signals ⁇ 1 , ⁇ 2 , ⁇ 3 , ⁇ 4 and ⁇ 5 for voltage control are electrically connected to the transfer gate electrode 7 , the multiplier gate electrode 8 , the transfer gate electrode 9 , the storage gate electrode 10 and the read gate electrode 11 through contact portions 7 a , 8 a , 9 a , 10 a and 11 a respectively.
  • the wiring layers 20 , 21 , 22 , 23 and 24 are formed every row, and electrically connected to the transfer gate electrode 7 , the multiplier gate electrode 8 , the transfer gate electrode 9 , the storage gate electrode 10 and the read gate electrode 11 of the plurality of pixels 50 forming each row respectively.
  • a signal line 25 for extracting a signal through a contact portion 5 a is electrically connected to the FD region 5 .
  • the portions of the buried layer 3 located under the transfer gate electrodes 7 and 9 , the storage gate electrode 10 and the read gate electrode 11 respectively are controlled to potentials of about 4 V when the voltages of about 2.9 V are applied (high-level signals are supplied) to the transfer gate electrodes 7 and 9 , the storage gate electrode 10 and the read gate electrode 11 respectively.
  • the portions of the buried layer 3 located under the transfer gate electrodes 7 and 9 , the storage gate electrode 10 and the read gate electrode 11 respectively are controlled to potentials of about 1.5 V and the potential of the portion (electron multiplying portion 3 a ), formed to have a high concentration, of the buried layer 3 located under the multiplier gate electrode 8 is controlled to a potential of about 2.5 V.
  • the FD region 5 is controlled to a potential of about 5 V.
  • the reset drain region 13 is controlled to a potential of about 5 V, and has a function as an ejecting portion of electrons held in the FD region 5 .
  • the transfer gate electrode 7 has a function of transferring electrons generated by the PD portion 4 to the electron multiplying portion 3 a located on the portion of the buried layer 3 located under the multiplier gate electrode 8 through the portion of the buried layer 3 located under the transfer gate electrode 7 by supplying the ON-state (high-level) signal to the transfer gate electrode 7 .
  • the portion of the buried layer 3 located under the transfer gate electrode 7 has a function as an isolation barrier dividing the PD portion 4 and portion of the buried layer 3 located under the multiplier gate electrode 8 (electron multiplying portion 3 a ) from each other when the OFF-state (low-level) signal is supplied to the transfer gate electrode 7 .
  • the multiplier gate electrode 8 is supplied with the ON-state signal, so that a high electric field is applied to the electron multiplying portion 3 a located on the portion of the buried layer 3 located under the multiplier gate electrode 8 . Then the speed of electrons transferred from the PD portion 4 through the portion of the buried layer 3 located under the transfer gate electrode 7 is increased by a high electric field generated in the electron multiplying portion 3 a and the electrons are multiplied by impact-ionization with atoms in the buried layer 3 .
  • the transfer gate electrode 9 has a function of transferring electrons between the portion (electron multiplying portion 3 a ) of the buried layer 3 located under the multiplier gate electrode 8 and the electron storage portion 3 b provided on the portion of the buried layer 3 located under the storage gate electrode 10 by supplying the ON-state signal to the transfer gate electrode 9 .
  • the transfer gate electrode 9 functions as a charge transfer barrier for suppressing transfer of electrons between the electron multiplying portion 3 a located under the multiplier gate electrode 8 and the electron storage portion 3 b located under the storage gate electrode 10 .
  • the read gate electrode 11 When the ON-state signal is supplied to the read gate electrode 11 , the read gate electrode 11 has a function of transferring electrons stored in the portion of the buried layer 3 (electron storage portion 3 b ) located under the storage gate electrode 10 to the FD region 5 .
  • the read gate electrode 11 When the OFF-state signal is supplied to the read gate electrode 11 , the read gate electrode 11 has a function of dividing the portion (electron storage portion 3 b ) of the buried layer 3 located under the storage gate electrode 10 and the FD region 5 .
  • each pixel 50 includes a reset transistor Tr 1 , an amplification transistor Tr 2 and a pixel selection transistor Tr 3 .
  • a reset gate line 30 is connected to the reset gate electrode 12 of the reset transistor Tr 1 through the contact portion 12 a , to supply a reset signal.
  • a drain (reset drain 13 ) of the reset transistor Tr 1 is connected to a power supply potential (VDD) line 31 through another contact portion 13 a.
  • the FD region 5 constituting sources of the reset transistor Tr 1 and the read gate electrode 11 and a gate 40 of the amplification transistor Tr 2 are connected with each other through the contact portions 5 a and 40 a by the signal line 25 .
  • a drain of the pixel selection transistor Tr 3 is connected to a source of the amplification transistor Tr 2 .
  • a row selection line 32 and an output line 33 are connected to a gate 41 and a source of the pixel selection transistor Tr 3 through the contact portions 41 a and 42 respectively.
  • electrons generated by the PD portion 4 (about 3 V) are transferred to the portion (electron multiplying portion 3 a ) of the buried layer 3 located under the multiplier gate electrode 8 (higher potential of about 13 V) through the portion of the buried layer 3 located under the transfer gate electrode 7 (about 4V), and the electrons are multiplied on the electron multiplying portion 3 a by impact ionization. Thereafter a voltage of about 0 V is applied to the transfer gate electrode 7 .
  • a voltage of about 2.9 V is applied to the transfer gate electrode 9 and a voltage of about 0 V is thereafter applied to the multiplier gate electrode 8 .
  • electrons are transferred from the electron multiplying portion 3 a (about 2.5 V) under the multiplier gate electrode 8 to the portion of the buried layer 3 located under the transfer gate electrode 9 (higher potential of about 4V).
  • a voltage of about 2.9 is applied to the storage gate electrode 10 and a voltage of about 0 V is thereafter applied to the transfer gate electrode 9 .
  • the electrons are transferred from the portion of the buried layer 3 located under the transfer gate electrode 9 to the portion (electron storage portion 3 b ) of the buried layer 3 located under the storage gate electrode 10 (higher potential of about 4 V).
  • a voltage of about 2.9 V is applied to the read gate electrode 11 , to control the potential of the portion of the buried layer 3 located under the read gate electrode 11 to a potential of about 4 V. Then a voltage of about 0 V is applied to the storage gate electrode 10 . Thus, the electrons are transferred to the FD region 5 through the portion of the buried layer 3 located under the read gate electrode 11 (about 4 V). Thus, the electron transferring operation is completed.
  • a voltage of about 12 V is applied to the multiplier gate electrode 8 in a period E shown in FIGS. 8 and 9 and a voltage of about 2.9 V is applied to the transfer gate electrode 9 in a period F, in the state where the portion of the buried layer 3 located under the storage gate electrode 10 (electron storage portion 3 b ) stores electrons by performing the operations of the periods A to C in FIGS. 6 and 7 .
  • the portion (electron multiplying portion 3 a ) of the buried layer 3 located under the multiplier gate electrode 8 is controlled to a potential of about 13 V and the portion of the buried layer 3 located under the transfer gate electrode 9 is thereafter controlled to a potential of about 4 V.
  • a voltage of about 0 V is applied to the storage gate electrode 10 , to transfer the electrons stored in the electron storage portion 3 b to the portion (electron multiplying portion 3 a ), having a higher potential, of the buried layer 3 located under the multiplier gate electrode 8 through the portion of the buried layer 3 located under the transfer gate electrode 9 (about 4 V).
  • the electrons are transferred to the electron multiplying portion 3 a to be multiplied in the aforementioned manner.
  • a voltage of about 0 V is applied to the transfer gate electrode 9 in a period G, thereby completing the electron multiplying operation.
  • the aforementioned operation in the periods A to C and the periods E to G is controlled to be performed a plurality of times (about 400 times, for example), thereby multiplying the electrons transferred from the PD portion 4 to about 2000 times.
  • Signal charges by thus multiplied and stored electrons are read as a voltage signal through the FD region 5 and the signal line 25 .
  • an impurity concentration of the portion (electron multiplying portion 3 a ) (see FIG. 3 ) of the buried layer 3 located under the multiplier gate electrode 8 reaches a maximum on the interface between the gate insulating film 6 and the buried layer 3 , and this concentration (peak concentration) is about 2.5 ⁇ 10 17 cm ⁇ 3 .
  • the impurity concentration is gradually reduced along a depth direction of the buried layer 3 . As shown by a dotted line of FIG.
  • the impurity concentration of each of the portions of the buried layer 3 located under the remaining electrodes other than the multiplier gate electrode 8 reaches a maximum on the interface between the gate insulating film 6 and the buried layer 3 , and this concentration (peak concentration) is about 8.5 ⁇ 10 16 cm ⁇ 3 .
  • the impurity concentration is gradually reduced along a depth direction of the buried layer 3 .
  • the peak concentration of the impurity in the portion (electron multiplying portion 3 a ) of the buried layer 3 located under the multiplier gate electrode 8 is about 2.5 ⁇ 10 17 cm ⁇ 3
  • a maximum point of the potential is deep with respect to the depth direction of the buried layer 3 as shown by the solid line of FIG. 11 .
  • the maximum point of the potential is separated from the interface between the gate insulating film 6 and the buried layer 3 . Consequently, the channel of electrons is separated from the interface between the gate insulating film 6 and the buried layer 3 .
  • the channel of electrons is formed on the position separated from the interface between the multiplier gate electrode 8 and the buried layer 3 when a voltage of about 3 V is applied to the buried layer 3 having the peak concentration of the impurity of about 8.5 ⁇ 10 16 cm ⁇ 3 (comparative example), while the channel of the electrons is formed in the vicinity of the interface between the multiplier gate electrode 8 and the buried layer 3 and electrons are transferred and multiplied while rubbing the interface when a voltage of 12 V is applied to the buried layer 3 .
  • a multiplication factor of electrons is improved by about three times as compared with a case where the peak concentration of the impurity is about 8.5 ⁇ 10 16 cm ⁇ 3 also when a voltage applied to the multiplier gate electrode 8 is reduced from a prescribed voltage by 2 V, in a case where the peak concentration (about 2.5 ⁇ 10 17 cm ⁇ 3 ) of the impurity in the portion of the buried layer 3 located under the multiplier gate electrode 8 (electron multiplying portion 3 a ) is larger than the peak concentration (about 8.5 ⁇ 10 16 cm ⁇ 3 ) of the impurity in the portion of the buried layer 3 located under each of the remaining electrodes other than the multiplier gate electrode 8 .
  • the electron channel on the portion located under the multiplier gate electrode 8 is disadvantageously relatively shallower than the electron channel on the portion located under each of the remaining electrodes, to which a low electrode is applied, other than the multiplier gate electrode 8 with respect to the depth direction of the buried layer 3 .
  • the peak concentration (about 2.5 ⁇ 10 17 cm ⁇ 3 ) of the impurity of a region of the buried layer 3 corresponding to the portion located under the multiplier gate electrode 8 is higher than the peak concentration (about 8.5 ⁇ 10 16 cm ⁇ 3 ) of the impurity of a region of the buried layer 3 corresponding to the portion located under each of the remaining electrodes other than the multiplier gate electrode 8 , whereby the electron channel located under the multiplier gate electrode 8 is prevented from being shallower than the electron channel located under each of the remaining electrodes other than the multiplier gate electrode 8 with respect to the interface of the buried layer 3 and the electron channel can be rendered deeper from the surface of the substrate.
  • the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the multiplier gate electrode 8 is higher than the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under each of the remaining electrodes other than the multiplier gate electrode 8 , whereby a potential well formed under the multiplier gate electrode 8 can be kept deeper also when the voltage applied to the multiplier gate electrode 8 is slightly reduced, and hence power consumption of the CMOS image sensor can be reduced by reducing the voltage applied to the multiplier gate electrode 8 .
  • the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the multiplier gate electrode 8 is higher than the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the transfer gate electrode 7 , whereby a potential barrier can be easily formed between the PD portion 4 and the electron multiplying portion 3 a.
  • the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the multiplier gate electrode 8 is higher than the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the transfer gate electrode 9 , whereby a potential barrier can be easily formed between the electron multiplying portion 3 a and the electron storage portion 3 b , and difference in potentials between the portions of the buried layer 3 located under the multiplier gate electrode 8 and the transfer gate electrode 9 can be increased.
  • a depth from the surface of the semiconductor substrate 100 which is a position where the potential of the region (electron multiplying portion 3 a ) corresponding to the portion located under the multiplier gate electrode 8 reaches a maximum is larger than a depth from the surface of the semiconductor substrate 100 which is a position where the potential of the region corresponding to the portion located under each of the remaining electrodes other than the multiplier gate electrode 8 reaches a maximum, when the same voltages are applied to the multiplier gate electrode 8 and the remaining electrodes, whereby the electron channel can be easily rendered deeper from the surface of the semiconductor substrate 100 .
  • the CMOS image censor comprises the transfer gate electrode 7 provided on a side of multiplier gate electrode 8 opposite to the transfer gate electrode 9 and the read gate electrode 11 provided on a side of the storage gate electrode 10 opposite to the transfer gate electrode 9 , whereby potential barriers can be formed between the PD portion 4 and the electron multiplying portion 3 a and between the electron storage portion 3 b and the FD region 5 by applying voltages of about 0 V to the transfer gate electrode 7 and the read gate electrode 11 when electrons are multiplied between the multiplier gate electrode 8 and the storage gate electrode 10 .
  • the electrons can be inhibited from leaking toward the PD portion 4 and the FD region 5 from the electron multiplying portion 3 a and the electron storage portion 3 b respectively.
  • the impurity concentrations of the regions of the buried layer 3 corresponding to the portions located under the transfer gate electrodes 7 and 9 , the storage gate electrode 10 and the read gate electrode 11 are rendered substantially equal to each other (n ⁇ -type), whereby the portions of the buried layer 3 (impurity region) located under the transfer gate electrodes 7 and 9 , the storage gate electrode 10 and the read gate electrode 11 can be easily formed through the same step.
  • the portions of the buried layer 3 located under the transfer gate electrode 7 , the multiplier gate electrode 8 , the transfer gate electrode 9 , the storage gate electrode 10 and the read gate electrode 11 are formed by the n-type impurity region, whereby the electrons generated on the PD portion 4 can be transferred and multiplied on the buried layer 3 .
  • a peak concentration of an impurity of a portion (electron storage portion 3 b ) of a buried layer 3 located under a storage gate electrode 10 is larger than a peak concentration of an impurity of each of portions of the buried layer 3 located under a transfer gate electrodes 7 and 9 and a read gate electrode 11 , dissimilarly to the aforementioned first embodiment.
  • the peak concentration of the impurity of the portion (electron storage portion 3 b ) of the buried layer 3 located under the storage gate electrode 10 is about 2.5 ⁇ 10 17 cm ⁇ 3 identical with the peak concentration of the impurity of an electron multiplying portion 3 a , as shown in FIG. 12 .
  • the peak concentration of the impurity of each of the portions of the buried layer 3 located under the multiplier gate electrode 8 and the storage gate electrode 10 is larger than the peak concentration of the impurity of each of the portions of the buried layer 3 located under the transfer gate electrodes 7 and 9 and the read gate electrode 11 .
  • the remaining structure of the second embodiment is similar to that of the aforementioned first embodiment.
  • Electron transferring and multiplying operations of the CMOS image sensor according to the second embodiment will be now described with reference to FIGS. 6 , 8 , 13 and 14 .
  • electrons generated by the PD portion 4 (about 3 V) are transferred to the portion (electron multiplying portion 3 a ) of the buried layer 3 located under the multiplier gate electrode 8 (higher potential of about 13 V) through the portion of the buried layer 3 located under the transfer gate electrode 7 (about 4V), and the electrons are multiplied on the electron multiplying portion 3 a by impact ionization. Thereafter a voltage of about 0 V is applied to the transfer gate electrode 7 .
  • a voltage of about 2.9 V is applied to the transfer gate electrode 9 and a voltage of about 0 V is thereafter applied to the multiplier gate electrode 8 .
  • electrons are transferred from the electron multiplying portion 3 a (about 2.5 V) under the multiplier gate electrode 8 to the portion of the buried layer 3 located under the transfer gate electrode 9 (higher potential of about 4 V).
  • a voltage of about 2.9 is applied to the storage gate electrode 10 and a voltage of about 0 V is thereafter applied to the transfer gate electrode 9 .
  • the electrons are transferred from the portion of the buried layer 3 located under the transfer gate electrode 9 to the portion (electron storage portion 3 b ) of the buried layer 3 located under the storage gate electrode 10 (higher potential of about 5 V).
  • a voltage of about 2.9 V is applied to the read gate electrode 11 , to control the potential of the portion of the buried layer 3 located under the read gate electrode 11 to a potential of about 4 V. Then a voltage of about 0 V is applied to the storage gate electrode 10 . Thus, the electrons are transferred to an FD region 5 through the portion of the buried layer 3 located under the read gate electrode 11 (about 4 V). Thus, the electron transferring operation is completed.
  • a voltage of about 12 V is applied to the multiplier gate electrode 8 in a period E shown in FIGS. 8 and 14 and a voltage of about 2.9 V is applied to the transfer gate electrode 9 in a period F, in the state where the portion (electron storage portion 3 b ) of the buried layer 3 located under the storage gate electrode 10 stores electrons by performing the operations of the periods A to C in FIGS. 6 and 13 .
  • the portion (electron multiplying portion 3 a ) of the buried layer 3 located under the multiplier gate electrode 8 is controlled to a potential of about 13 V and the portion of the buried layer 3 located under the transfer gate electrode 9 is thereafter controlled to a potential of about 4 V.
  • a voltage of about 0 V is applied to the storage gate electrode 10 , to transfer the electrons stored in the electron storage portion 3 b to the portion (electron multiplying portion 3 a ) (higher potential of about 13 V) of the buried layer 3 located under the multiplier gate electrode 8 through the portion of the buried layer 3 located under the transfer gate electrode 9 (about 4 V).
  • the electrons are transferred to the electron multiplying portion 3 a to be multiplied in the aforementioned manner.
  • a voltage of about 0 V is applied to the transfer gate electrode 9 in a period G, thereby completing the electron multiplying operation.
  • the peak concentration (about 2.5 ⁇ 10 17 cm ⁇ 3 ) of the impurity of a region of the buried layer 3 corresponding to the portion located under the storage gate electrode 10 is higher than the peak concentration (about 8.5 ⁇ 10 16 cm ⁇ 3 ) of the impurity of a region of the buried layer 3 corresponding to the portion located under the transfer gate electrode 9 , whereby the potential of the region of the buried layer 3 corresponding to the portion located under the storage gate electrode 10 can be increased as compared with a case where the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the storage gate electrode 10 is equal to the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the transfer gate electrode 9 , and hence a larger number of electrons can be held.
  • the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the storage gate electrode 10 and the peak concentration of the impurity of the region of the buried layer 3 corresponding to the portion located under the multiplier gate electrode 8 are substantially equal to each other, whereby the electron storage portion 3 b under the storage gate electrode 10 and the electron multiplying portion 3 a under the multiplier gate electrode 8 can be simultaneously formed.
  • the impurity concentrations of the regions of the buried layer 3 corresponding to the portions located under the transfer gate electrodes 7 and 9 and the read gate electrode 11 are substantially equal to each other (n ⁇ -type), whereby the portions of the buried layer 3 (impurity region) located under the transfer gate electrodes 7 and 9 and the read gate electrode 11 can be easily formed through the same step.
  • each of the aforementioned first and second embodiments is applied to the active CMOS image sensor amplifying signal charges in each pixel 50 as an exemplary image sensor
  • the present invention is not restricted to this but is also applicable to a passive CMOS image sensor not amplifying signal charges in each pixel.
  • the present invention is not restricted to this but electrodes between the PD portion 4 and the FD region 5 may be formed by three or four electrodes.
  • the present invention is not restricted to this but the buried layer 3 , the PD portion 4 and the FD region 5 may be formed on the surface of the p-type silicon substrate.
  • the present invention is not restricted to this but holes may alternatively be employed as the signal charges by entirely reversing the conductivity type of the substrate impurity and the polarities of the applied voltages.
  • the present invention is not restricted to this but a dopant other than As (arsenic) may be implanted.

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100013975A1 (en) * 2008-07-15 2010-01-21 Sanyo Electric Co., Ltd. Image sensor
US8587037B1 (en) * 2009-07-08 2013-11-19 Hrl Laboratories, Llc Test structure to monitor the in-situ channel temperature of field effect transistors
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