US20090094414A1

US20090094414A1 - Firmware Update for Storage Device

Info

Publication number: US20090094414A1
Application number: US12/333,320
Authority: US
Inventors: Chi-Chun Hsu; Wen-Yi Wu
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2004-09-16
Filing date: 2008-12-12
Publication date: 2009-04-09
Also published as: TW200611189A; US7480904B2; US20060059300A1; TWI259974B

Abstract

A storage device includes a firmware memory, a buffer memory, a processor and a memory update controller. When the storage device is under a normal mode, the memory update controller is in an idle state. The processor controls the storage device to fetch an update firmware and store the update firmware into the buffer memory. When the storage device is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This continuation application claims the benefit of co-pending U.S. patent application Ser. No. 10/907,949, which filed on Apr. 21, 2005 and included herein by reference.

BACKGROUND

The present invention relates to a storage device (e.g., an optical disc drive) comprising a dedicated memory update controller for updating firmware of the storage device.
An optical disc drive is a device for accessing information stored in an optical disc. A processor of an optical disc drive controls operations of the optical disc drive through executing specific program codes. The specific program codes are referred to as the firmware of the optical disc drive. The optical disc drive's firmware includes all needed data, commands, instructions, programs, and all other information utilized by the optical disc drive. The optical disc drive's firmware is always stored in a nonvolatile memory of the optical disc drive and needs to be updated if required.
A firmware update scheme of a system in a related art stores both the needed firmware information and an update routine code in a nonvolatile memory of an optical disc drive. Under a normal operation mode, a processor of the optical disc drive executes the firmware stored in the nonvolatile memory to control operations of the optical disc drive. Under a firmware update mode, the processor executes the update routine code to update the firmware stored in the nonvolatile memory. This firmware update scheme requires additional update routine code. The nonvolatile memory must provide additional space for storing the update routine code. Furthermore, additional time is required for the processor to update the firmware by executing the update routine.
U.S. Pat. No. 6,170,043 discloses another firmware update scheme for optical disc drives. According to this patent, an optical disc drive includes a system control chip, a buffer memory, and a flash memory. The system control chip comprises a microprocessor and an additional memory. Under a normal operation mode, the flash memory stores the optical disc drive's firmware, and the additional memory of the system control chip stores ordinary information. The microprocessor executes the firmware stored in the flash memory to control ordinary operations of the optical disc drive. Under a firmware update mode, the additional memory of the system control chip stores an update routine code. The microprocessor updates the firmware stored in the flash memory by a new version of firmware stored in the buffer memory. The additional update routine code must be provided during firmware update. The firmware update requires significant time.
U.S. Pat. No. 6,523,083 discloses another firmware update method. Unfortunately, this firmware update method needs an additional host device.

SUMMARY OF THE INVENTION

According to the claimed invention, a storage device having at least a normal operation mode and a firmware update mode is disclosed. The storage device includes: a firmware memory; a buffer memory; a processor electrically connected to the firmware memory, for controlling the storage device to fetch an update firmware and store the update firmware into the buffer memory when the storage device is under the normal operation mode; and a memory update controller electrically connected to the firmware memory and the buffer memory, for fetching the update firmware from the buffer memory and storing the update firmware into the firmware memory when the storage device is under the firmware update mode.
According to the claimed invention, a firmware update method utilized in a storage device is disclosed. The storage device includes a firmware memory, a buffer memory, a processor, and a memory update controller. The method includes: (a) controlling the storage device to fetch an update firmware and store the update firmware into the buffer memory with the processor; and (b) without utilizing the processor to execute an update routine code, utilizing the memory update controller to fetch the update firmware from the buffer memory and store the update firmware into the firmware memory.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an optical disc drive according to an exemplary embodiment of the present invention.

FIG. 2 shows an embodiment of the memory update controller of FIG. 1.

FIG. 3, FIG. 4, and FIG. 5 show flowcharts illustrating how the optical disc drive of FIG. 1 operates.

DETAILED DESCRIPTION

FIG. 1 shows an optical disc drive 100 according to an exemplary embodiment of the present invention. In this embodiment, the optical disc drive 100 includes a radio frequency (RF) circuit 110, a buffer memory 120, a firmware memory 130, and a system control chip 140. The buffer memory 120 stores information retrieved from an optical disc 102 or information to be recorded into the optical disc 102. The buffer memory 120 can be a volatile memory, such as a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM). The firmware memory 130 stores firmware. The firmware memory 130 can be a nonvolatile memory, such as a flash memory, an electrical erasable programmable read only memory (EEPROM), or a serial flash memory.
The system control chip 140 includes a memory update controller 142, a processor 144, a decoder 146, and a controller 148. The processor 144 can be a microprocessor or an embedded processor. A data bus 141 interconnects the memory update controller 142, the processor 144, the decoder 146, and the controller 148. The data bus 141 can also be set external to the system control chip 140. In addition to controlling the RF circuit 110 to access the optical disc 102, the system control chip 140 connects to an optional computer 106 through a main board interface 104. The main board interface 104 can be an integrated drive electronics (IDE) interface, a small computer system interface (SCSI interface), a serial advanced technology attachment (SATA) interface, or any other functionally similar interfaces.
The optical disc drive 100 of this embodiment has a normal operation mode and a firmware update mode. When the optical disc drive 100 is under the normal operation mode, the memory update controller 142 is in an idle state. Through the data bus 141, the processor 144 accesses the firmware stored in the firmware memory 130. The processor 144 controls ordinary operations of the optical disc drive 100 by executing the firmware stored in the firmware memory 130. When a firmware update is required, the processor 144 controls the optical disc drive 100 to fetch an update firmware, e.g. from the optical disc 102, and store the update firmware into the buffer memory 120 in the same manner as if the update firmware is ordinary information. The update firmware can also be stored in the buffer memory 120 with a specific format, such as a table of content (TOC) format. After the update firmware is retrieved and stored into the buffer memory 120, the optical disc drive 100 enters the firmware update mode. Under the firmware update mode, the processor 144 is in an idle state; the memory update controller 142 becomes a dedicated hardware for updating the firmware. Without utilizing the processor 144 to execute an update routine code, the memory update controller 142 fetches the update firmware from the buffer memory 120 (e.g., through the decoder 146), and updates the firmware memory 130.
For example, every time the computer 106 is turned on or reset, the processor 144 initializes the optical disc drive 100. After the initialization process is finished, the processor 144 enters a standby state to wait for commands from the computer 106. If the system control chip 140 receives a read command, the processor 144 sends corresponding parameters and instructions to control the operations of the decoder 146 and the controller 148. Data is retrieved from the optical disc 102, decoded and corrected if necessary, and stored in the buffer memory 120. The computer 106 then reads the data stored in the buffer memory 120. During the read operation, the optical disc drive 100 is under the normal operation mode, and the memory update controller 142 remains in an idle state.
During the firmware update, the processor 144 first controls the optical disc drive 100 to fetch an update firmware, e.g. from the optical disc 102, and store the update firmware into the buffer memory 120. Secondly, the processor 144 initializes the memory update controller 142. This initialization process that is performed on the memory update controller 142 can alternatively be performed by the computer 106 or other external devices. The information utilized in the initialization process may include, but is not limited to, a starting address of the update firmware in the buffer memory 120, a size of the update firmware, and a target address of the firmware memory 130. If there does exist a fixed target address, the information utilized in the initialization process may also exclude the fixed target address of the firmware memory 130. After the initialization process is finished, the optical disc drive 100 enters the firmware update mode, the processor 144 enters the idle state, and the memory update controller 142 begins to update the firmware stored in the firmware memory 130.
FIG. 2 is a diagram illustrating a relationship between the memory update controller 142 and the firmware memory 130. In FIG. 2, the memory update controller 142 includes a direct memory access (DMA) unit 201 and a dedicated memory update unit 202. The DMA unit 201 fetches the update firmware from the buffer memory 120 (e.g., through the decoder 146) in sequence and sends the fetched update firmware to the dedicated memory update unit 202. The dedicated memory update unit 202 then stores the update firmware received from the DMA unit 201 into the firmware memory 130. Additionally, a small FIFO may be placed between the DMA unit 201 and the dedicated memory update unit 202.
For example, consider that the firmware memory 130 is a flash memory. In this example, there exist multiple methods to update the firmware stored in the firmware memory 130. One is to update the firmware memory 130 in a byte-by-byte manner, and the other is to update the firmware memory 130 in a page-by-page manner. Each page includes 128 bytes of memory space. When the memory update controller 142 is performing the firmware update, the update firmware stored in the buffer memory 120 is treated as ordinary data. When each piece of data is being stored into the firmware memory 130, the firmware memory 130 can send an indication flag to the data bus 141 to report its status. The dedicated memory update unit 202 examines the indication flag to determine whether each piece of data is correctly stored into the firmware memory 130. Once the entire update firmware in the buffer memory 120 is correctly stored into the firmware memory 130, the firmware update is completed. The memory update controller 142 may dispatch a reset signal to reset the processor 144 and switch the optical disc drive 100 back to the normal operation mode.
FIGS. 3-5 show flowcharts illustrating the operations of the optical disc drive 100. Please refer to FIG. 3. In step 300, the computer 106 is reset. Next, the computer 106 sends instructions to the processor 144 to make the processor 144 reinitialize the optical disc drive 100 (step 310). After the optical disc drive 100 is reinitialized, the processor 144 continues to determine whether there is a request for firmware update (step 321). The firmware update can be instructed in several ways, for example, by a user through a dedicated user interface or by the computer 106 through the main board interface 104. When there is a request for firmware update, the optical disc drive 100 goes to step 322; otherwise, the optical disc drive 100 goes to step 340 to perform ordinary operations, such as accessing the optical disc 102.
In step 322, the firmware of the optical disc drive 100 is updated. This step can be further divided into two parts, shown in FIGS. 4 and 5, respectively. The first part is under the normal operation mode and the second part is under the firmware update mode.
In step 410 of FIG. 4, the processor 144 executes the firmware stored in the firmware memory 130 to control the optical disc drive 100 to fetch the update firmware, e.g. from the optical disc 102, and store the update firmware into the buffer memory 120. Next, in step 411, the processor 144 initializes the memory update controller 142. More specifically, the processor 144 sets related information, such as the starting address of the update firmware in the buffer memory 120, the size of the update firmware, and the destination address in the firmware memory 130, into registers of the memory update controller 142. Next, in step 430, the optical disc drive 100 enters the firmware update mode. The memory update controller 142 updates the firmware stored in the firmware memory 130. The processor 144 then enters the idle state.
In step 500, the DMA unit 201 fetches the update firmware from the buffer memory 120 in a byte-by-byte manner or a page-by-page manner. The DMA unit 201 then sends the fetched update firmware and address information to the dedicated memory update unit 202. In step 510, the dedicated memory update unit 202 converts the received update firmware and address information into a format conforming to an update protocol adopted by the firmware memory 130. Finally, the dedicated memory update unit 202 updates the firmware memory 130. Step 520 checks whether the firmware update was completed within a certain time constraint. It is considered that the firmware update is failed if the firmware update is not completed within the time constraint. The optical disc drive 100 goes to step 530 to indicate the failure of the firmware update. The optical disc drive 100 goes to step 540 if the firmware update is finished within the time constraint. Step 530 can be implemented utilizing a counter as an auxiliary tool. Step 540 determines whether the entire update firmware stored in the buffer memory 120 has been written into the firmware memory 130. The firmware update is considered finished if the entire update firmware stored in the buffer memory 120 was written into the firmware memory 130. In this case, step 310 of FIG. 3 is executed next. The optical disc drive 100 enters the normal operation mode, the memory update controller 142 enters the idle state, and the processor 144 reinitializes the optical disc drive 100. Finally, in step 340, the processor 144 controls ordinary operations of the optical disc drive 100 by executing the renewed firmware stored in the firmware memory 130. In the event where step 540 determines that the firmware update is not finished, the memory update controller 142 proceeds with step 500 to process a subsequent byte (or a subsequent page) of the update firmware.
In contrast to the related art, the present invention does not require an additional update routine code or the additional memory space for storing the additional update routine code. Furthermore, since the memory update controller is utilized to update firmware of the optical disc drive without utilizing the processor to execute an update routine code, the firmware update is faster than that of the related art.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A storage device having a normal operation mode and a firmware update mode, the storage device comprising:

a firmware memory;

a buffer memory;

a processor electrically connected to the firmware memory, for controlling the storage device to fetch an update firmware and store the update firmware into the buffer memory when the storage device is under the normal operation mode; and

a memory update controller electrically connected to the firmware memory and the buffer memory, for fetching the update firmware from the buffer memory and storing the update firmware into the firmware memory when the storage device is under the firmware update mode without the processor executing an update routine code for updating firmware stored in the firmware memory.

2. The storage device of claim 1, wherein the processor controls the storage device to fetch the update firmware from an optical disc.

3. The storage device of claim 1, wherein the memory update controller comprises:

a direct memory access (DMA) unit electrically connected to the buffer memory, for fetching the update firmware from the buffer memory; and

a dedicated memory update unit electrically connected to the DMA unit and the firmware memory, for receiving the update firmware from the DMA unit and storing the update firmware into the firmware memory.

4. The storage device of claim 1, wherein when the storage device is under the normal operation mode, the processor executes the firmware stored in the firmware memory to control operations of the storage device.

5. The storage device of claim 1, wherein when the storage device is under the firmware update mode, the processor is in an idle state; and when the storage device is under the normal operation mode, the memory update controller is in an idle state.

6. The storage device of claim 1, wherein the processor and the memory update controller are set in a system control chip of the storage device.

7. The storage device of claim 1, wherein the firmware memory is a flash memory, an electrical erasable programmable read only memory (EEPROM), or a serial flash memory.

8. The storage device of claim 1, wherein the buffer memory is a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM).

9. A system control chip utilized in a storage device, for updating firmware of the storage device, the system control chip comprising:

a processor electrically connected to a firmware memory of the storage device, the firmware memory being for storing firmware of the storage device;

a controller electrically connected to the processor, for receiving a control signal and general data;

a decoder electrically connected to the processor, the controller, and a buffer memory of the storage device; and

a memory update controller electrically connected to the processor and the firmware memory, for receiving an update firmware and storing the update firmware into the firmware memory without the processor executing an update routine code for updating firmware stored in the firmware memory.

10. The system control chip of claim 9, wherein the memory update controller is further electrically connected to the decoder, and receives the update firmware from the decoder.

11. The system control chip of claim 10, wherein the memory update controller comprises:

a direct memory access (DMA) unit electrically connected to the decoder, for receiving the update firmware from the decoder; and

12. The system control chip of claim 9, wherein the processor, the controller, the decoder, and the memory update controller are interconnected through a data bus.

13. The system control chip of claim 12, wherein the processor sets the memory update controller through the data bus.

14. The system control chip of claim 9, wherein the processor executes the firmware stored in the firmware memory to control operations of the decoder and the controller.

15. The system control chip of claim 9, wherein the firmware memory is a flash memory, an electrical erasable programmable read only memory (EEPROM), or a serial flash memory.

16. The system control chip of claim 9, wherein the buffer memory is a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM).

17. A firmware update method utilized in a storage device, the storage device comprising a firmware memory, a buffer memory, a processor, and a memory update controller, the firmware update method comprising:

(a) controlling the storage device to fetch an update firmware and store the update firmware into the buffer memory with the processor; and

(b) without utilizing the processor to execute an update routine code for updating firmware stored in the firmware memory, utilizing the memory update controller to fetch the update firmware from the buffer memory and store the update firmware into the firmware memory.

18. The firmware update method of claim 17, wherein step (a) controls the storage device to fetch the update firmware from an optical disc.

19. The firmware update method of claim 17, wherein:

step (a) further comprises controlling the memory update controller to be in an idle state; and

step (b) further comprises controlling the processor to be in an idle state.

20. The firmware update method of claim 17, wherein the firmware memory is a flash memory, an electrical erasable programmable read only memory (EEPROM), or a serial flash memory.

21. The firmware update method of claim 17, wherein the buffer memory is a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM).