US20090090915A1 - Thin film transistor, display device having thin film transistor, and method for manufacturing the same - Google Patents

Thin film transistor, display device having thin film transistor, and method for manufacturing the same Download PDF

Info

Publication number: US20090090915A1
Authority: US; United States
Prior art keywords: impurity element; donor; serves; film; microcrystalline semiconductor
Prior art date: 2007-10-05
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

US12/238,517

Other languages

English (en)

Inventor

Shunpei Yamazaki

Yoshiyuki Kurokawa

Yasuhiro Jinbo

Satoshi Kobayashi

Daisuke Kawae

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Semiconductor Energy Laboratory Co Ltd

Original Assignee

Semiconductor Energy Laboratory Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2007-10-05

Filing date

2008-09-26

Publication date

2009-04-09

2008-09-26 Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd

2008-09-26 Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD. reassignment SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JINBO, YASUHIRO, YAMAZAKI, SHUNPEI, KAWAE, DAISUKE, KOBAYASHI, SATOSHI, KUROKAWA, YOSHIYUKI

2009-04-09 Publication of US20090090915A1 publication Critical patent/US20090090915A1/en

2013-03-18 Priority to US13/845,443 priority Critical patent/US8945962B2/en

Status Abandoned legal-status Critical Current

Images

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/019—Manufacture or treatment of FETs having stacked nanowire, nanosheet or nanoribbon channels
- H10D30/0191—Manufacture or treatment of FETs having stacked nanowire, nanosheet or nanoribbon channels forming stacked channels, e.g. changing their shapes or sizes
- H10D30/0194—Manufacture or treatment of FETs having stacked nanowire, nanosheet or nanoribbon channels forming stacked channels, e.g. changing their shapes or sizes the stacked channels having different properties
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/501—FETs having stacked nanowire, nanosheet or nanoribbon channels
- H10D30/502—FETs having stacked nanowire, nanosheet or nanoribbon channels characterised by the stacked channels
- H10D30/504—FETs having stacked nanowire, nanosheet or nanoribbon channels characterised by the stacked channels wherein the stacked channels have different properties
- H10D30/506—FETs having stacked nanowire, nanosheet or nanoribbon channels characterised by the stacked channels wherein the stacked channels have different properties having different thicknesses, sizes or shapes
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/40—Crystalline structures
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H10D30/6739—Conductor-insulator-semiconductor electrodes

Definitions

the present invention relates to a thin film transistor, a display device having the thin film transistor at least in a pixel portion, and a method for manufacturing the thin film transistor and the display device.
Thin film transistors are applied to a wide range of electronic devices such as ICs or electro-optical devices, and prompt development of thin film transistors that are to be used as switching elements in display devices, in particular, is being pushed.
a thin film transistor including an amorphous semiconductor film, a thin film transistor including a polycrystalline semiconductor film, or the like is used as a switching element in a display device.
a method for forming a polycrystalline semiconductor film a technique is known in which a pulsed excimer laser beam is processed into a linear shape with an optical system, and an amorphous silicon film is scanned with the linear beam, thereby being crystallized.
a thin film transistor including a microcrystalline semiconductor film is used (see Reference 1: Japanese Published Patent Application No. H4-242724; and Reference 2: Japanese Published Patent Application No. 2005-49832).
a thin film transistor including a polycrystalline semiconductor film has advantages that the field effect mobility thereof is two or more orders of magnitude higher than that of a thin film transistor including an amorphous semiconductor film, and that a pixel portion and a peripheral driver circuit of a display device can be formed over one substrate.
the thin film transistor including a polycrystalline semiconductor film requires a more complicated process than the thin film transistor including an amorphous semiconductor film because of crystallization of the semiconductor film. Thus, there are problems such as a reduction in yield and an increase in cost.
an inverted-staggered thin film transistor including a microcrystalline semiconductor film has problems in that the crystallinity of an interface region between a gate insulating film and a microcrystalline semiconductor film is low and electric characteristics are poor.
An aspect of the present invention is a thin film transistor including a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a pair of buffer layers formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which is formed over the pair of buffer layers, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added; in which a part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor film or the entire microcrystalline semiconductor film includes an impurity element which serves as a donor.
a feature of the thin film transistor of the present invention is that a region of the microcrystalline semiconductor film which is in contact with the gate insulating film includes the impurity element which serves as a donor.
the entire microcrystalline semiconductor film can include the impurity element which serves as a donor.
only a region of the microcrystalline semiconductor film which is in contact with the gate insulating film can include the impurity element which serves as a donor.
a first microcrystalline semiconductor film including the impurity element which serves as a donor is formed in the region which is in contact with the gate insulating film, and a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film.
the second microcrystalline semiconductor film does not include the impurity element which serves as a donor at a higher concentration than the detection limit of secondary ion mass spectrometry (SIMS).
a feature of the thin film transistor of the present invention is that the gate insulating film includes the impurity element which serves as a donor.
a feature of the thin film transistor of the present invention is that a first microcrystalline semiconductor film that is in contact with a gate insulating film, a second microcrystalline semiconductor film that is in contact with the first microcrystalline semiconductor film and includes an impurity element which serves as a donor, and a third microcrystalline semiconductor film that is in contact with the second microcrystalline semiconductor film including the impurity element which serves as a donor are formed.
the first microcrystalline semiconductor film and the third microcrystalline semiconductor film do not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS.
a gate insulating film or a microcrystalline semiconductor film which includes an impurity element which serves as a donor is formed and a thin film transistor is formed in which the microcrystalline semiconductor film serves as a channel formation region.
the peak concentration of the impurity element which serves as a donor is from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
a gate insulating film is formed over a gate electrode; a first microcrystalline semiconductor film including an impurity element which serves as a donor is formed over the gate insulating film, using gas including the impurity element which serves as a donor, deposition gas including silicon or germanium, and hydrogen; a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film, using deposition gas including silicon or germanium, and hydrogen; and a thin film transistor is manufactured using the first microcrystalline semiconductor film and the second microcrystalline semiconductor film.
a gate insulating film including an impurity element which serves as a donor is formed over a gate electrode, using gas including the impurity element which serves as a donor, and deposition gas including silicon or germanium; a microcrystalline semiconductor film including the impurity element which serves as a donor is formed over the gate insulating film including the impurity element which serves as a donor, using deposition gas including silicon or germanium, and hydrogen; and a thin film transistor is manufactured using the microcrystalline semiconductor film.
a protective film including an impurity element which serves as a donor is formed on an inner wall of a reaction chamber of a plasma CVD apparatus, using gas including the impurity element which serves as a donor, deposition gas including silicon or germanium, and hydrogen; then, a substrate provided with a gate electrode is carried in the reaction chamber; a gate insulating film is formed over the gate electrode; a microcrystalline semiconductor film is formed over the gate insulating film, using deposition gas including silicon or germanium, and hydrogen; and a thin film transistor is manufactured using the microcrystalline semiconductor film.
gas including an impurity element which serves as a donor is fed into a reaction chamber of a plasma CVD apparatus; then, a gate insulating film including the impurity element which serves as a donor is formed over a substrate provided with a gate electrode; a microcrystalline semiconductor film is formed over the gate insulating film, using deposition gas including silicon or germanium, and hydrogen; and a thin film transistor is manufactured using the microcrystalline semiconductor film.
a first gate insulating film is formed over a substrate provided with a gate electrode; gas including an impurity element which serves as a donor is fed into a reaction chamber of a plasma CVD apparatus; then, a second gate insulating film including the impurity element which serves as a donor is formed over the first gate insulating film, using non-deposition gas including oxygen or nitrogen, and deposition gas including silicon; a microcrystalline semiconductor film is formed over the second gate insulating film; and a thin film transistor is manufactured using the microcrystalline semiconductor film.
a first gate insulating film is formed over a substrate provided with a gate electrode; a second gate insulating film is formed over the first gate insulating film; then, gas including an impurity element which serves as a donor for a semiconductor is fed into a reaction chamber of a plasma CVD apparatus; subsequently, a third gate insulating film including the impurity element which serves as a donor is formed over the second gate insulating film, using non-deposition gas including oxygen or nitrogen, and deposition gas including silicon; a microcrystalline semiconductor film is formed over the third gate insulating film, using deposition gas including silicon or germanium, and hydrogen; and a thin film transistor is manufactured using the microcrystalline semiconductor film.
the impurity element which serves as a donor is phosphorus, arsenic, or antimony.
a gate insulating film including an impurity element which serves as a donor is formed over a gate electrode, or an impurity element which serves as a donor is adsorbed onto a gate insulating film, whereby crystallinity can be increased at an interface with the gate insulating film in forming the microcrystalline semiconductor film.
a thin film transistor can be manufactured in which the microcrystalline semiconductor film whose crystallinity has been increased at the interface with the gate insulating film is used for a channel formation region.
a microcrystalline semiconductor film in contact with a gate insulating film forming a microcrystalline semiconductor film including an impurity element which serves as a donor can increase the speed of carrier travel in the microcrystalline semiconductor film, so that a thin film transistor with high field effect mobility and high on-current can be manufactured.
the peak concentration of the impurity element which serves as a donor and is included in the gate insulating film or the microcrystalline semiconductor film is set to be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive, so that an accumulation-type thin film transistor (i.e., a thin film transistor in which a channel formation region includes an n-type impurity element at a low concentration) can be manufactured.
the peak concentration of the impurity element which serves as a donor and is included in the gate insulating film or the microcrystalline semiconductor film is lower than 6 ⁇ 10 15 atoms/cm 3 , the amount of the impurity element which serves as a donor is insufficient, and thus an increase in the field effect mobility and in the on-current cannot be expected.
the concentration of the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
a buffer layer is formed successively over the microcrystalline semiconductor film, whose crystallinity at the interface with the gate insulating film has been increased, and source and drain regions and source and drain wirings are formed over the buffer layer, so that a thin film transistor is formed.
Another feature of the present invention is that a pixel electrode connected to the thin film transistor is formed and a display device is manufactured.
Display devices include light-emitting devices and liquid crystal display devices.
a light-emitting device includes a light-emitting element and a liquid crystal display device includes a liquid crystal element.
a light-emitting element includes, in its category, an element whose luminance is controlled with current or voltage; specifically, an organic electroluminescent (EL) element and an inorganic EL element.
EL organic electroluminescent
the display devices include a panel in which a display element is sealed, and a module in which an IC and the like including a controller are mounted on the panel.
the present invention relates to one mode of an element substrate before the display element is completed in a manufacturing process of the display device, and the element substrate is provided with a means for supplying current to the display element in each of a plurality of pixels.
the element substrate may be in a state of being provided with only a pixel electrode of the display element, a state after a conductive film to be a pixel electrode is formed and before the conductive film is etched to form the pixel electrode, or any other states.
a display device in this specification means an image display device, a light-emitting device, or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module including a connector such as a flexible printed circuit (FPC), tape automated bonding (TAB) tape, or a tape carrier package (TCP); a module having TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.
a module including a connector such as a flexible printed circuit (FPC), tape automated bonding (TAB) tape, or a tape carrier package (TCP); a module having TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.
FPC flexible printed circuit
TAB tape
a microcrystalline semiconductor film which has high crystallinity from an interface with an insulating film can be formed, and a thin film transistor with excellent electric characteristics can be manufactured using the microcrystalline semiconductor film for a channel formation region. Further, a display device having the thin film transistor can be manufactured.
FIGS. 1A and 1D are cross-sectional views illustrating a thin film transistor of the present invention
FIGS. 1B , 1 C, 1 E, and 1 F are diagrams showing peak concentrations of an impurity element which serves as a donor in stacked films;
FIGS. 2A and 2E are cross-sectional views illustrating a thin film transistor of the present invention
FIGS. 2B , 2 C, 2 D, and 2 F are diagrams showing peak concentrations of an impurity element which serves as a donor in stacked films;
FIG. 3A is a cross-sectional view illustrating a thin film transistor of the present invention
FIG. 3B is a diagram showing a peak concentration of an impurity element which serves as a donor in stacked films;
FIGS. 4A and 4C are cross-sectional views illustrating a thin film transistor of the present invention
FIGS. 4B and 4D are diagrams showing a peak concentration of an impurity element which serves as a donor in stacked films;
FIG. 5A is a cross-sectional view illustrating a thin film transistor of the present invention
FIG. 5B is a diagram showing a peak concentration of an impurity element which serves as a donor in stacked films;
FIG. 6 is a cross-sectional view illustrating a thin film transistor of the present invention.
FIGS. 7A and 7C are cross-sectional views illustrating a thin film transistor of the present invention
FIGS. 7B and 7D are diagrams showing peak concentrations of an impurity element which serves as a donor in stacked films;
FIG. 8 is an example of a timing chart illustrating a process for forming gate insulating films and a microcrystalline semiconductor film
FIGS. 9A to 9C are cross-sectional views illustrating a method for manufacturing a display device of the present invention.
FIGS. 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device of the present invention.
FIGS. 11A and 11B are cross-sectional views illustrating a method for manufacturing a display device of the present invention.
FIGS. 12A to 12C are top views illustrating a method for manufacturing a display device of the present invention.
FIG. 14 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention.
FIG. 16 is an example of a timing chart illustrating a process for forming gate insulating films and a microcrystalline semiconductor film
FIG. 18 is an example of a timing chart illustrating a process for forming gate insulating films and a microcrystalline semiconductor film
FIG. 19 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention.
FIG. 22 is a drawing showing a structure of a plasma CVD apparatus applicable to the present invention.
FIGS. 24A and 24B are cross-sectional views illustrating a method for manufacturing a display device of the present invention.
FIGS. 25A to 25D are drawings illustrating multi-tone photomasks applicable to the present invention.
FIGS. 26A to 26C are cross-sectional views illustrating a method for manufacturing a display device of the present invention.
FIGS. 27A and 27B are cross-sectional views illustrating a method for manufacturing a display device of the present invention.
FIGS. 30A to 30C are top views illustrating a method for manufacturing a display device of the present invention.
FIG. 31 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention.
FIG. 33 is a top view illustrating a display device of the present invention.
FIG. 34 is a top view illustrating a display device of the present invention.
FIGS. 36A to 36C are perspective views illustrating display panels of the present invention.
FIGS. 37A to 37D are perspective views illustrating electronic devices having display devices of the present invention.
FIG. 39 is a graph illustrating a result of measuring phosphorus concentrations in microcrystalline silicon films of the present invention with SIMS;
FIG. 40 is a graph illustrating a result of measuring phosphorus concentrations in microcrystalline silicon films of the present invention with SIMS;
FIG. 41 is a graph illustrating a result of phosphorus concentrations in microcrystalline silicon films of the present invention with SIMS;
FIGS. 42A to 42E are drawings illustrating structures of Samples 1 to 5, respectively;
FIG. 43 is a graph illustrating a result of measuring lifetime of carriers in microcrystalline silicon films by a ⁇ -PCD method
FIG. 44 is a cross-sectional view illustrating a model used for simulation
FIGS. 45A and 45B are graphs showing DC characteristics which are calculated by simulation
FIGS. 46A and 46B are graphs showing DC characteristics which are calculated by simulation
FIGS. 47A and 47B are graphs showing DC characteristics which are calculated by simulation
FIGS. 48A and 48B are graphs showing on-currents which are calculated by simulation
FIGS. 49A and 49B are graphs showing threshold values which are calculated by simulation
FIGS. 50A and 50B are graphs showing subthreshold swings which are calculated by simulation
FIGS. 51A and 51B are graphs showing maximum field effect mobilities which are calculated by simulation
FIGS. 52A and 52B are drawings showing an element structure of a thin film transistor and 52 C is an equivalent circuit diagram thereof;
FIG. 53 is a graph illustrating maximum field effect mobilities of a thin film transistor
FIG. 54 is a circuit diagram used for circuit simulation.
FIG. 55 is a graph illustrating thicknesses and donor concentrations of microcrystalline silicon films, and threshold values.
This embodiment mode describes structures of a thin film transistor which has high crystallinity at an interface between a microcrystalline semiconductor film and a gate insulating film, and has higher field effect mobility and higher on-current than a thin film transistor having a conventional microcrystalline semiconductor film in a channel formation region, with reference to FIGS. 1A to 1F , FIGS. 2A to 2F , FIGS. 3A and 3B , FIGS. 4A to 4D , and FIGS. 5A and 5B .
a gate electrode 51 is formed over a substrate 50 ; gate insulating films 52 a and 52 b are formed over the gate electrode 51 ; a microcrystalline semiconductor film 61 including an impurity element which serves as a donor (hereinafter also referred to as the microcrystalline semiconductor film 61 ) is formed over the gate insulating films 52 a and 52 b ; a microcrystalline semiconductor film 58 not including an impurity element which serves as a donor at a higher concentration than the detection limit of SIMS (hereinafter also referred to as the microcrystalline semiconductor film 58 ) is formed over the microcrystalline semiconductor film 61 ; a pair of buffer layers 73 are formed partly over the microcrystalline semiconductor film 58 ; a pair of semiconductor films 72 (hereinafter also referred to as source and drain regions 72 ) to which an impurity element imparting one conductivity type is added are formed over the pair of buffer layers 73 ; and wirings 71 a to 71 c are formed over the
the microcrystalline semiconductor film 61 includes the impurity element which serves as a donor at a peak concentration of from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive. Further, the microcrystalline semiconductor film 61 including the impurity element which serves as a donor has a thickness of from 1 to 50 nm inclusive. Examples of the microcrystalline semiconductor film are a microcrystalline silicon film, a microcrystalline silicon film including germanium, and the like. Further, examples of the impurity element which serves as a donor are phosphorus, arsenic, antimony, and the like.
the concentration of the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, more preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
a peak of a Raman spectrum of microcrystalline silicon lies between 520 cm ⁇ 1 and 480 cm ⁇ 1 , which represent a peak of a Raman spectrum of single crystalline silicon and that of amorphous silicon, respectively.
the microcrystalline semiconductor film includes hydrogen or halogen at 1 at. % or more in order to terminate a dangling bond.
the microcrystalline semiconductor film may further include a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, so that the stability is enhanced and a favorable microcrystalline semiconductor film can be obtained.
a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, so that the stability is enhanced and a favorable microcrystalline semiconductor film can be obtained.
a concentration of oxygen and a concentration of nitrogen in the microcrystalline semiconductor film each be less than ten times that of the impurity element which serves as a donor, typically lower than 3 ⁇ 10 19 atoms/cm 3 , preferably lower than 3 ⁇ 10 18 atoms/cm 3 ; and that a concentration of carbon be lower than or equal to 3 ⁇ 10 18 atoms/cm 3 .
Low concentrations of oxygen, nitrogen, and carbon in the microcrystalline semiconductor film can suppress generation of defects in the microcrystalline semiconductor film.
oxygen and/or nitrogen in the microcrystalline semiconductor film hinders crystallization. Therefore, the microcrystalline semiconductor film includes oxygen and nitrogen at relatively low concentrations and includes the impurity element which serves as a donor, whereby the crystallinity of the microcrystalline semiconductor film can be enhanced.
the microcrystalline semiconductor film including the impurity element which serves as a donor of this embodiment mode includes the impurity element which serves as a donor; therefore, by adding an impurity element which serves as an acceptor to the microcrystalline semiconductor film which serves as the channel formation region of the thin film transistor at the same time as or after formation of the microcrystalline semiconductor film, the threshold value can be controlled.
a typical example of the impurity element which serves as an acceptor is boron, and impurity gas such as B 2 H 6 or BF 3 is preferably mixed into silicon hydride at from 1 to 1000 ppm, preferably from 1 to 100 ppm. Further, a concentration of boron is preferably set to be approximately one-tenth that of the impurity element which serves as a donor, e.g., from 1 ⁇ 10 14 to 6 ⁇ 10 16 atoms/cm 3 .
the pair of buffer layers 73 which are formed of an amorphous semiconductor film, have a larger energy gap and a higher resistivity than the microcrystalline semiconductor film 58 ; further, mobility in the pair of buffer layers 73 is one-fifth to one-tenth that of the microcrystalline semiconductor film 58 . In the thin film transistor which is completed later, therefore, the buffer layers 73 function as high resistant regions and thus can reduce leakage current which is generated between the source and drain regions 72 and the microcrystalline semiconductor film 61 .
an alkali-free glass substrate manufactured by a fusion method or a float method such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass; a ceramic substrate; a plastic substrate which has high heat resistance enough to withstand a process temperature of this manufacturing process; or the like can be used.
a metal (e.g., stainless steel alloy) substrate whose surface is provided with an insulating film may be used.
the gate electrode 51 is formed of a metal material.
a metal material aluminum, chromium, titanium, tantalum, molybdenum, copper, or the like is used.
the gate electrode 51 is preferably formed of aluminum or a stacked-layer structure of aluminum and a barrier metal.
a barrier metal a metal with a high melting point, such as titanium, molybdenum, or chromium, is used.
a barrier metal is preferably provided in order to prevent hillocks and oxidation of aluminum.
the gate electrode 51 is formed with a thickness of from 50 to 300 nm inclusive.
the thickness of from 50 to 100 nm inclusive of the gate electrode 51 can prevent a disconnection of a semiconductor film and a wiring, which are formed later. Further, the thickness of from 150 to 300 nm inclusive of the gate electrode 51 can lower the resistance of the gate electrode 51 , and increase the size of the substrate.
the gate electrode 51 is preferably processed to have a tapered end portion so that the semiconductor film and the wiring thereover are not disconnected. Further, although not illustrated, a wiring or a capacitor wiring which is connected to the gate electrode can also be formed at the same time when the gate electrode is formed.
the gate insulating films 52 a and 52 b can each be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film with a thickness of from 50 to 150 nm.
This embodiment mode presents an example in which a silicon nitride film or a silicon nitride oxide film is formed as the gate insulating film 52 a , and a silicon oxide film or a silicon oxynitride film is formed as the gate insulating film 52 b to form a stacked-layer structure.
the gate insulating film can be formed using a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film.
the gate insulating film 52 a By forming the gate insulating film 52 a using a silicon nitride film or a silicon nitride oxide film, adhesion between the substrate 50 and the gate insulating film 52 a is increased, and further, impurities from the substrate 50 can be prevented from diffusing into the microcrystalline semiconductor film 61 including the impurity element which serves as a donor when a glass substrate is used for the substrate 50 . Furthermore, oxidation of the gate electrode 51 can be prevented. That is to say, film peeling can be prevented, and electric characteristics of the thin film transistor which is completed later can be improved.
the gate insulating films 52 a and 52 b each having a thickness of greater than or equal to 50 nm are preferable because the gate insulating films 52 a and 52 b having the above thickness can alleviate reduction in coverage which is caused by unevenness due to the gate electrode 51 .
a silicon oxynitride film means a film that includes more oxygen than nitrogen, and includes oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 55 to 65 at. %, 1 to 20 at. %, 25 to 35 at. %, and 0.1 to 10 at. %, respectively.
a silicon nitride oxide film means a film that includes more nitrogen than oxygen, and includes oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 15 to 30 at. %, 20 to 35 at. %, 25 to 35 at. %, and 15 to 25 at. %, respectively.
the semiconductor films 72 to which the impurity element imparting one conductivity type is added may be doped with phosphorus, which is a typical impurity element; for example, impurity gas such as PH 3 may be added to silicon hydride.
impurity gas such as PH 3 may be added to silicon hydride.
the semiconductor films 72 to which the impurity element imparting one conductivity type is added may be doped with boron, which is a typical impurity element; for example, impurity gas such as B 2 H 6 may be added to silicon hydride.
the semiconductor films 72 to which the impurity element imparting one conductivity type is added include phosphorus or boron at a concentration of from 1 ⁇ 10 19 to 1 ⁇ 10 21 atoms/cm 3 , thereby having ohmic contact with the conductive film; thus, the semiconductor films 72 to which the impurity element imparting one conductivity type is added function as the source and drain regions.
the semiconductor films 72 to which the impurity element imparting one conductivity type is added can be formed using a microcrystalline semiconductor or an amorphous semiconductor.
the semiconductor films 72 to which the impurity element imparting one conductivity type is added are formed with a thickness of from 2 to 50 nm inclusive. Reduction in the thickness of the semiconductor film to which the impurity element imparting one conductivity type is added can improve the throughput.
the wirings 71 a to 71 c are preferably formed with a single layer or stacked layers using aluminum; copper; or an aluminum alloy to which an element for preventing hillocks or an element for improving heat resistance property, such as silicon, titanium, neodymium, scandium, or molybdenum, is added.
an element for preventing hillocks or an element for improving heat resistance property such as silicon, titanium, neodymium, scandium, or molybdenum
a film in contact with the semiconductor film to which the impurity element imparting one conductivity type is added may be formed of titanium, tantalum, molybdenum, or tungsten, or nitride of such an element; and aluminum or an aluminum alloy may be formed thereover to form a stacked-layer structure.
top and bottom surfaces of aluminum or an aluminum alloy may be each covered with titanium, tantalum, molybdenum, tungsten, or nitride thereof to form a stacked-layer structure.
This embodiment mode shows the conductive film having a three-layer structure of the wirings 71 a to 71 c ; a stacked-layer structure in which the wirings 71 a and 71 c are formed using molybdenum films and the conductive film 71 b is formed using an aluminum film, or a stacked-layer structure in which the wirings 71 a and 71 c are formed using titanium films and the wiring 71 b is formed using an aluminum film is formed.
concentration distribution of the impurity element which serves as a donor in a stacked-layer portion including the gate insulating films 52 a and 52 b , the microcrystalline semiconductor film 61 including the impurity element which serves as a donor, the microcrystalline semiconductor film 58 not including the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, and the buffer layers 73 is schematically shown by curves 41 and 42 in FIGS. 1B and 1C .
a concentration of the impurity element which serves as a donor in the thin film transistor shown in FIG. 1A has a peak value in the microcrystalline semiconductor film 61 including the impurity element which serves as a donor.
a peak of the concentration distribution of the impurity element which serves as a donor may be located in or around the center of the microcrystalline semiconductor film 61 including the impurity element which serves as a donor.
a peak of the concentration distribution of the impurity element which serves as a donor may be located at or around the interface between the gate insulating film 52 b and the microcrystalline semiconductor film 61 including the impurity element which serves as a donor.
an impurity element which serves as a donor in the microcrystalline semiconductor film may be included only in a part on the gate insulating film side.
an impurity element which serves as a donor may be included in an entire microcrystalline semiconductor film. That is to say, a microcrystalline semiconductor film 61 including an impurity element which serves as a donor may be formed between a gate insulating film 52 b and a pair of buffer layers 73 .
a gate electrode 51 is formed over a substrate 50 ; a gate insulating film 52 a and the gate insulating film 52 b are formed over the gate electrode 51 ; the microcrystalline semiconductor film 61 including the impurity element which serves as a donor is formed over the gate insulating film 52 b ; the pair of buffer layers 73 are formed over the microcrystalline semiconductor film 61 including the impurity element which serves as a donor; a pair of semiconductor films 72 to which an impurity element imparting one conductivity type is added are formed over the pair of buffer layers 73 ; and wirings 71 a to 71 c are formed over the pair of semiconductor films 72 to which the impurity element imparting one conductivity type is added.
the microcrystalline semiconductor film 61 including the impurity element which serves as a donor is formed between the gate insulating film 52 b and the pair of buffer layers 73 . It is preferable that the peak concentration of the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, more preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive. Further, the microcrystalline semiconductor film 61 including the impurity element which serves as a donor has a thickness of from 5 to 100 nm inclusive, preferably from 10 to 50 nm inclusive.
the peak concentration of the impurity element which serves as a donor may satisfy the above range in the entire microcrystalline semiconductor film 61 ; or the concentration of the impurity element which serves as a donor may have a peak at or around the interface between the gate insulating film 52 b and the microcrystalline semiconductor film 61 , and may decrease from the gate insulating film 52 b toward the pair of buffer layers 73 .
the peak concentration of oxygen and the peak concentration of nitrogen in the microcrystalline semiconductor film 61 including the impurity element which serves as a donor are each less than ten times that of the impurity element which serves as a donor and further when the peak concentration of the impurity element which serves as an acceptor (a typical example is boron) is less than or equal to one-tenth that of the impurity element which serves as a donor, crystallinity of the microcrystalline semiconductor film including the impurity element which serves as a donor can be increased further.
the peak concentration of the impurity element which serves as a donor and is included in the microcrystalline semiconductor film is set to be in the above range, whereby the interface between the gate insulating film 52 b and the microcrystalline semiconductor film 61 can have improved crystallinity and the microcrystalline semiconductor film 61 can have lower resistivity; thus, a thin film transistor with high field effect mobility and high on-current can be manufactured.
the peak concentration of the impurity element which serves as a donor and is included in the microcrystalline semiconductor film is lower than 6 ⁇ 10 15 atoms/cm 3 , the amount of the impurity element which serves as a donor is insufficient, and thus an increase in the field effect mobility and in the on-current cannot be expected.
the concentration of the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
concentration distribution of the impurity element which serves as a donor in a stacked-layer portion including the gate insulating films 52 a and 52 b , the microcrystalline semiconductor film 61 including the impurity element which serves as a donor, and the buffer layers 73 is schematically shown by curves 47 and 48 in FIGS. 1E and 1F .
a concentration of the impurity element which serves as a donor in the thin film transistor shown in FIG. 1D has a peak value in the microcrystalline semiconductor film 61 which includes the impurity element which serves as a donor and which is provided between the gate insulating film 52 b and the buffer layers 73 .
a peak of the concentration distribution of the impurity element which serves as a donor may be located at or around the interface between the gate insulating film 52 b and the microcrystalline semiconductor film 61 including the impurity element which serves as a donor, and the concentration may decrease toward the buffer layers 73 .
FIG. 2A shows a cross section of a thin film transistor of this embodiment mode.
a gate electrode 51 is formed over a substrate 50 ; a gate insulating film 52 a is formed over the gate electrode 51 ; a gate insulating film 59 including an impurity element which serves as a donor is formed over the gate insulating film 52 a ; a microcrystalline semiconductor film 58 is formed over the gate insulating film 59 ; a pair of buffer layers 73 are formed over the microcrystalline semiconductor film 58 ; a pair of semiconductor films 72 to which an impurity element imparting one conductivity type is added are formed over the pair of buffer layers 73 ; and wirings 71 a to 71 c are formed over the pair of semiconductor films 72 to which the impurity element imparting one conductivity type is added.
the peak concentration of phosphorus in the gate insulating film 59 including the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
the microcrystalline semiconductor film 58 has a thickness of from 1 to 50 nm inclusive.
the gate insulating film 52 a can be formed using a similar material to that of the gate insulating film 52 a shown in FIGS. 1A and 1D .
the gate insulating film 59 including the impurity element which serves as a donor can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or the like including the impurity element which serves as a donor (e.g., phosphorus, arsenic, or antimony).
the curve 44 which shows concentration distribution of the impurity element which serves as a donor, has a peak on the gate electrode side in the gate insulating film 59 a including the impurity element which serves as a donor, and the concentration decreases from the gate electrode side toward the microcrystalline semiconductor film 58 side.
the shape of the curve that shows the concentration distribution of the impurity element which serves as a donor is not limited to that shown in FIG. 2C , and a concentration may have a peak in or around the center of the gate insulating film 59 a including the impurity element which serves as a donor.
positions of the gate insulating film 52 a and the gate insulating film 59 including the impurity element which serves as a donor may be reversed.
the gate insulating film 59 including the impurity element which serves as a donor may be formed over the gate electrode 51
the gate insulating film 52 a may be formed over the gate insulating film 59 including the impurity element which serves as a donor.
the shape of the curve that shows the concentration distribution of the impurity element which serves as a donor is not limited to that shown in FIG. 2D , and a concentration may have a peak in or around the center of the gate insulating film 59 including the impurity element which serves as a donor.
a gate electrode 51 is formed over a substrate 50 ; a gate insulating film 52 a is formed over the gate electrode 51 ; a gate insulating film 59 including an impurity element which serves as a donor is formed over the gate insulating film 52 a ; a microcrystalline semiconductor film 61 including an impurity element which serves as a donor is formed over the gate insulating film 59 including the impurity element which serves as a donor; a pair of buffer layers 73 are formed over the microcrystalline semiconductor film 61 ; a pair of semiconductor films 72 to which an impurity element imparting one conductivity type is added are formed over the pair of buffer layers 73 ; and wirings 71 a to 71 c are formed over the pair of semiconductor films 72 to which the impurity element imparting one conductivity type is added.
concentration distribution of the impurity element which serves as a donor in a stacked-layer portion including the gate insulating film 52 a , the gate insulating film 59 including the impurity element which serves as a donor, the microcrystalline semiconductor film 61 including the impurity element which serves as a donor, and the buffer layers 73 is schematically shown by a curve 35 in FIG. 2F .
the gate insulating film 59 which is in contact with the microcrystalline semiconductor film 58 or the microcrystalline semiconductor film 61 including the impurity element which serves as a donor, includes the impurity element which serves as a donor.
the impurity element which serves as a donor is deposited on a surface of the gate insulating film 59 , whereby crystallinity of the microcrystalline semiconductor film 58 or 61 can be increased in starting deposition of the microcrystalline semiconductor film 58 or 61 .
the gate insulating film on the gate electrode 51 side includes the impurity element which serves as a donor.
the impurity element can be diffused into the gate insulating film on the microcrystalline semiconductor film side at a low concentration. Accordingly, crystallinity can be increased at the interface between the gate insulating film 59 and the microcrystalline semiconductor film 58 or 61 and resistivity of the microcrystalline semiconductor film 58 or 61 can be reduced; thus, a thin film transistor with high field effect mobility and high on-current can be manufactured.
the peak concentration of the impurity element which serves as a donor and is included in the gate insulating film 59 is lower than 6 ⁇ 10 15 atoms/cm 3 , the amount of the impurity element which serves as a donor is insufficient, and thus an increase in the field effect mobility and in the on-current cannot be expected.
the concentration of the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
FIG. 3A shows a cross section of a thin film transistor of this embodiment mode.
a gate electrode 51 is formed over a substrate 50 ; gate insulating films 59 a and 59 b including the impurity element which serves as a donor are formed over the gate electrode 51 ; a microcrystalline semiconductor film 61 including an impurity element which serves as a donor is formed over the gate insulating film 59 b including the impurity element which serves as a donor; a pair of buffer layers 73 are formed over the microcrystalline semiconductor film 61 including the impurity element which serves as a donor; a pair of semiconductor films 72 to which an impurity element imparting one conductivity type is added are formed over the pair of buffer layers 73 ; and wirings 71 a to 71 c are formed over the pair of semiconductor films 72 to which the impurity element imparting one conductivity type is added.
the peak concentration of the impurity element which serves as a donor in the gate insulating films 59 a and 59 b including the impurity element which serves as a donor and in the microcrystalline semiconductor film 61 including the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, more preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
concentration distribution of the impurity element which serves as a donor in a stacked-layer portion including the gate electrode 51 , the gate insulating films 59 a and 59 b including the impurity element which serves as a donor, the microcrystalline semiconductor film 61 including the impurity element which serves as a donor, and the buffer layers 73 is schematically shown by a curve 46 in FIG. 3B .
the concentration of the impurity element which serves as a donor in the thin film transistor shown in FIG. 3A satisfies the above concentration range in the gate insulating films 59 a and 59 b and the microcrystalline semiconductor film 61 , and has a peak therein.
the peak is located at or around the interface between the gate electrode 51 and the gate insulating film 59 a .
the shape of the curve 46 which shows concentration distribution of the impurity element which serves as a donor, is not limited to that shown in FIG.
the concentration may have a peak in or around the center of the gate insulating film 59 a including the impurity element which serves as a donor, in or around the center of the gate insulating film 59 b including the impurity element which serves as a donor, or at or around the interface between the gate insulating films 59 a and 59 b including the impurity element which serves as a donor.
the concentration may have a peak at or around the interface between the gate insulating film 59 b including the impurity element which serves as a donor and the microcrystalline semiconductor film 61 including the impurity element which serves as a donor.
the concentration may have a peak in the center of the microcrystalline semiconductor film 61 including the impurity element which serves as a donor.
the thin film transistor shown in FIG. 3A may have a microcrystalline semiconductor film 58 between the microcrystalline semiconductor film 61 including the impurity element which serves as a donor and the buffer layers 73 (see FIG. 4A ).
the microcrystalline semiconductor film 58 does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS.
the profile should be flat; practically, however, the profile hardly is flat because the signal/noise (S/N) ratio is poor at a low concentration region of ions measured. Therefore, a mean value of the concentrations of ions measured in the low concentration region is set to be the detection limit.
concentration distribution of the impurity element which serves as a donor in a stacked-layer portion including the gate insulating films 59 a and 59 b including the impurity element which serves as a donor, the microcrystalline semiconductor film 61 including the impurity element which serves as a donor, the microcrystalline semiconductor film 58 , and the buffer layers 73 is schematically shown by a curve 33 in FIG. 4B .
the concentration of the impurity element which serves as a donor in the thin film transistor shown in FIG. 4A has a peak value in the gate insulating film 59 a including the impurity element which serves as a donor.
Forming the microcrystalline semiconductor film 58 over the microcrystalline semiconductor film 61 including the impurity element which serves as a donor can prevent the impurity element which serves as a donor in the microcrystalline semiconductor film 61 from being diffused into the pair of buffer layers 73 . If the impurity element which serves as a donor is diffused into the pair of buffer layers 73 , which are high resistant regions, resistance of the pair of buffer layers 73 decreases and leakage current flows between the microcrystalline semiconductor film 61 including the impurity element which serves as a donor and the source and drain regions 72 , thereby degrading switching characteristics.
the microcrystalline semiconductor film 58 not including the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS between the microcrystalline semiconductor film 61 including the impurity element which serves as a donor and the pair of buffer layers 73 .
the shape of the curve 33 which shows concentration distribution of the impurity element which serves as a donor, is not limited to that shown in FIG.
the concentration may have a peak in or around the center of the gate insulating film 59 a including the impurity element which serves as a donor, in or around the center of the gate insulating film 59 b including the impurity element which serves as a donor, or at or around the interface between the gate insulating films 59 a and 59 b including the impurity element which serves as a donor.
the concentration may have a peak at or around the interface between the gate insulating film 59 b including the impurity element which serves as a donor and the microcrystalline semiconductor film 61 including the impurity element which serves as a donor.
the concentration may have a peak in the center of the microcrystalline semiconductor film 61 including the impurity element which serves as a donor.
the microcrystalline semiconductor film 58 may be formed instead of the microcrystalline semiconductor film 61 including the impurity element which serves as a donor (see FIG. 4C ).
concentration distribution of the impurity element which serves as a donor in a stacked-layer portion including the gate insulating films 59 a and 59 b including the impurity element which serves as a donor, the microcrystalline semiconductor film 58 , and the buffer layers 73 is schematically shown by a curve 34 in FIG. 4D .
the concentration of the impurity element which serves as a donor in the thin film transistor shown in FIG. 4C has a peak value in the gate insulating film 59 a including the impurity element which serves as a donor.
FIG. 5A shows a cross section of a thin film transistor of this embodiment mode.
a gate electrode 51 is formed over a substrate 50 ; gate insulating films 52 a and 52 b are formed over the gate electrode 51 ; a first microcrystalline semiconductor film 58 a is formed over the gate insulating film 52 b ; a second microcrystalline semiconductor film 64 including an impurity element which serves as a donor is formed over the first microcrystalline semiconductor film 58 a ; a third microcrystalline semiconductor film 58 b is formed over the second microcrystalline semiconductor film 64 including the impurity element which serves as a donor; a pair of buffer layers 73 are formed over the third microcrystalline semiconductor film 58 b ; a pair of semiconductor films 72 to which an impurity element imparting one conductivity type is added are formed over the pair of buffer layers 73 ; and wirings 71 a to 71 c are formed over the pair of semiconductor films 72 to which the impurity element imparting one conductivity type is added.
a feature of this mode is that the second microcrystalline semiconductor film 64 including the impurity element which serves as a donor is formed between the first microcrystalline semiconductor film 58 a and the third microcrystalline semiconductor film 58 b , which do not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS. It is preferable that the peak concentration of the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, more preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
the concentration of the impurity element which serves as a donor in the thin film transistor shown in FIG. 5A satisfies the above peak concentration in the second microcrystalline semiconductor film 64 including the impurity element which serves as a donor. Further, the concentration has a peak value in the center of the second microcrystalline semiconductor film 64 including the impurity element which serves as a donor. Furthermore, the shape of the curve that shows the concentration distribution of the impurity element which serves as a donor is not limited to that shown in FIG. 5B .
the concentration may have a peak at or around the interface between the first microcrystalline semiconductor film 58 a and the second microcrystalline semiconductor film 64 including the impurity element which serves as a donor, and may decrease toward the third microcrystalline semiconductor film 58 b.
a channel formation region with a microcrystalline semiconductor film suppresses variation in threshold voltage, improves field effect mobility, and lowers subthreshold swing (S value); thus, a thin film transistor can achieve high performance. Accordingly, a display device can be driven at a high frequency, whereby the panel size can be increased and pixels in the display device can be made with high density.
This embodiment mode presents a thin film transistor in which a gate insulating film has a different structure from that of the thin film transistors shown in Embodiment Mode 1, with reference to FIG. 6 and FIGS. 7A to 7D .
the thin film transistor has three gate insulating films instead of the two gate insulating films which are shown in FIGS. 1A to 1F , FIGS. 2A to 2F , FIGS. 3A and 3B , FIGS. 4A to 4D , and FIGS. 5A and 5B .
gate insulating films 52 a and 52 b and a gate insulating film 59 c including an impurity element which serves as a donor may be formed over a substrate 50 and a gate electrode 51 .
a microcrystalline semiconductor film 58 , a pair of buffer layers 73 , a pair of semiconductor films 72 to which an impurity element imparting one conductivity type is added, and wirings 71 a to 71 c can be formed thereover.
a silicon nitride film, a silicon nitride oxide film, a silicon oxide film, or a silicon oxynitride film can be formed by a plasma CVD method or a sputtering method in a similar manner to Embodiment Mode 1.
a silicon nitride film or a silicon nitride oxide film with a thickness of from 1 to 5 nm approximately which includes phosphorus, arsenic, or antimony can be formed.
a microcrystalline semiconductor film 61 including an impurity element which serves as a donor may be formed (see FIG. 7C ).
a microcrystalline semiconductor film 61 including an impurity element which serves as a donor may be formed (see FIG. 7C ).
a microcrystalline semiconductor is deposited under the condition of forming the microcrystalline semiconductor film 58 , with the impurity element which serves as a donor remaining in a reaction chamber.
the concentration of the impurity element which serves as a donor in the thin film transistor shown in FIG. 7C has a peak value in the gate insulating film 59 c including the impurity element which serves as a donor. Further, the peak is present at or around the interface between the gate insulating film 52 b and the gate insulating film 59 c including the impurity element which serves as a donor. Furthermore, the shape of the curve that shows the concentration distribution of the impurity element which serves as a donor is not limited to that shown in FIG. 7D , and the concentration may have a peak in or around the center of the gate insulating film 59 c including the impurity element which serves as a donor.
high-density plasma nitridation a silicon nitride layer that includes nitrogen at a higher concentration can be obtained.
the high-density plasma is generated by use of high-frequency microwaves, for example, microwaves with a frequency of 2.45 GHz.
high-density plasma which has the characteristic of having a low electron temperature, a layer can be formed with less plasma damage and fewer defects compared to a layer formed by conventional plasma treatment because the kinetic energy of an active species is low.
carrier mobility can be increased because the level of roughness on the surface of the gate insulating film 52 b can be reduced.
a microcrystalline semiconductor film is deposited by a plasma CVD method using a deposition gas including silicon or germanium, and hydrogen, whereby a microcrystalline semiconductor film 57 including the impurity element which serves as a donor is formed.
a process for forming a microcrystalline silicon film including phosphorus is described in chronological order with reference to FIG. 8 .
FIG. 8 is a typical example of a timing chart for describing steps of forming the gate insulating films 52 a and 52 b and the microcrystalline semiconductor film 57 including the impurity element which serves as a donor.
FIG. 8 shows a procedure starting from a step of vacuum evacuation 440 from atmospheric pressure in a reaction chamber of a plasma CVD apparatus.
a precoating treatment 441 substrate carrying-in 442 , a film formation treatment ( 1 ) 443 for forming the gate insulating film 52 a , a vacuum evacuation treatment 444 , a film formation treatment ( 2 ) 445 for forming the gate insulating film 52 b , a vacuum evacuation treatment 446 , a flush treatment 447 , a film formation treatment ( 3 ) 448 for forming the microcrystalline semiconductor film 57 including the impurity element which serves as a donor, and substrate carrying-out 449 .
NP Normal Pressure
high vacuum evacuation vacuum evacuation is performed with use of a turbo molecular pump or the like to obtain a pressure lower than 10 ⁇ 1 Pa as a degree of vacuum.
vacuum evacuation may be performed with use of a cryopump to reduce a pressure in the reaction chamber to be lower than 10 ⁇ 5 Pa, i.e., to an ultrahigh vacuum.
a heat treatment is performed to the reaction chamber so as to degas the inner wall of the reaction chamber. Further, the temperature is stabilized by operating a heater for heating the substrate.
the substrate heating temperature is from 100 to 300° C., preferably from 120 to 220° C.
the inner wall of the reaction chamber of the plasma CVD apparatus is precoated with a film having a composition that is the same as or similar to the gate insulating film. Accordingly, it is possible to prevent a metal used to form the reaction chamber from entering the gate insulating film as an impurity. In other words, by covering the inner wall of the reaction chamber with the film having a composition that is the same as or similar to the gate insulating film, the inner wall of the reaction chamber can be prevented from being etched by plasma, and the concentration of the impurity which enters the gate insulating film from the reaction chamber can be reduced.
the substrate is carried into the reaction chamber from a load lock chamber connected to the reaction chamber.
the pressure in the reaction chamber at this time is the same as that in the load lock chamber (hereinafter such a pressure is called as LP (Load Lock Pressure)).
source gases which are hydrogen, silane, and ammonia in this example, are introduced and mixed, so that a pressure in the reaction chamber reaches a predetermined value (hereinafter such a pressure is called as SP (Setting Pressure)), and a silicon nitride film is formed by glow discharge plasma which is generated by application of high-frequency power.
SP Setting Pressure
Nitrogen may also be introduced in addition to the above source gases.
vacuum evacuation treatment 444 vacuum evacuation is performed in the reaction chamber to a predetermined degree of vacuum.
source gases which are hydrogen, silane, and dinitrogen monoxide in this example, are introduced and mixed, and a silicon oxynitride film is formed by glow discharge plasma which is generated by application of high-frequency power.
introduction of the above source gases is halted, and the power is turned off, and then, generation of plasma is halted.
vacuum evacuation treatment 446 vacuum evacuation is performed in the reaction chamber to a predetermined degree of vacuum.
gas including an impurity element which serves as a donor is introduced to the reaction chamber, and the impurity element which serves as a donor is adsorbed onto the surface of the gate insulating film 52 b , furthermore, onto the inner wall of the reaction chamber.
0.001% to 1% phosphine (diluted with hydrogen or silane) is introduced to the reaction chamber. Phosphine is not necessarily diluted with hydrogen or silane.
deposition gas including silicon or germanium may be introduced as designated by a dashed line 461 or hydrogen may be introduced as designated by a dashed line 462 , to the reaction chamber.
the film formation treatment ( 3 ) 448 for forming the microcrystalline semiconductor film 57 including the impurity element which serves as a donor deposition gas including silicon or germanium, which is silane in this example, hydrogen, and/or rare gas are introduced and mixed in the reaction chamber, and a microcrystalline semiconductor film is formed by glow discharge plasma which is generated by application of high-frequency power.
Silane is diluted with hydrogen and/or rare gas to be 10 to 2000 times thinner. Therefore, a large amount of hydrogen and/or rare gas is needed.
the substrate heating temperature is from 100 to 300° C., preferably from 120 to 220° C. It is preferable that the film be formed at temperatures of from 120 to 220° C.
the microcrystalline semiconductor grows using the impurity element which serves as a donor and is adsorbed onto the surface of the gate insulating film 52 b , which is phosphorus in this example, as a crystal nucleus.
an amorphous semiconductor is not formed in an early stage of deposition of the semiconductor film, and crystals grow in a direction of the normal to the gate insulating film 52 b , so that a microcrystalline semiconductor film with high crystallinity in which column-like microcrystalline semiconductors are present can be formed.
the impurity element which serves as a donor and is adsorbed onto the surface of the gate insulating film 52 b is included in the microcrystalline semiconductor film, so that a highly conductive microcrystalline semiconductor film 57 including the impurity element which serves as a donor can be formed.
an energy band width may be adjusted to be from 0.9 to 1.1 eV by mixing germanium hydride or germanium fluoride such as GeH 4 or GeF 4 into gas such as silane. By adding germanium to silicon, the temperature characteristics of a thin film transistor can be changed.
the substrate carrying-out 449 the substrate is carried out of the reaction chamber and carried into the load lock chamber connected to the reaction chamber.
the pressure in the reaction chamber at this time is the same as that in the load lock chamber.
the film formation treatment ( 3 ) 448 for forming the microcrystalline semiconductor film 57 including the impurity element which serves as a donor is carried out after the flush treatment 447 in this embodiment mode.
the microcrystalline semiconductor film 57 including the impurity element which serves as a donor can be formed without the flush treatment 447 as follows: deposition gas including silicon or germanium, hydrogen, and/or rare gas, and gas including an impurity element which serves as a donor are introduced and mixed, and the microcrystalline semiconductor film 57 including the impurity element which serves as a donor is formed by glow discharge plasma which is generated by application of high-frequency power.
an amorphous semiconductor layer is formed in an early stage of deposition due to impurities except the impurity element which serves as a donor, lattice mismatch, or the like.
impurities except the impurity element which serves as a donor, lattice mismatch, or the like.
an inverted-staggered thin film transistor carriers flow in a region of a microcrystalline semiconductor film which is near to the gate insulating film.
microcrystalline semiconductor film including the impurity element which serves as a donor over the gate insulating film as in this embodiment mode, crystallinity in a film thickness direction can be improved, and crystallinity at the interface between the gate insulating film and the microcrystalline semiconductor film can be improved.
a microcrystalline semiconductor film 53 is formed over the microcrystalline semiconductor film 57 including the impurity element which serves as a donor.
the microcrystalline semiconductor film 53 is formed as follows: deposition gas including silicon or germanium, which is silane in this example, hydrogen, and/or rare gas are introduced and mixed in a reaction chamber, and the microcrystalline semiconductor film is formed by glow discharge plasma which is generated by application of high-frequency power. Silane is diluted with hydrogen and/or rare gas to be 10 to 2000 times thinner. Therefore, a large amount of hydrogen and/or rare gas is needed.
the substrate heating temperature is from 100 to 300° C., preferably from 120 to 220° C. It is preferable that the film be formed at temperatures of from 120 to 220° C.
the microcrystalline semiconductor film 53 By forming the microcrystalline semiconductor film 53 in a reaction chamber different from that for forming the microcrystalline semiconductor film 57 including the impurity element which serves as a donor, the microcrystalline semiconductor film 53 , which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed. Also by forming the microcrystalline semiconductor film successively without the substrate carrying-out 449 shown in FIG. 8 , the microcrystalline 53 , which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed. In this case, in the flush treatment 447 , it is preferable to reduce the concentration of the impurity element which serves as a donor and is adsorbed onto the gate insulating film 52 b and the inner wall of the reaction chamber.
a buffer layer 54 and a semiconductor film 55 to which an impurity element imparting one conductivity type is added are formed over the microcrystalline semiconductor film 53 .
a resist mask 56 is formed over the semiconductor film 55 to which the impurity element imparting one conductivity type is added.
an amorphous semiconductor film can be formed by a plasma CVD method using deposition gas including silicon or germanium.
deposition gas including silicon or germanium by diluting deposition gas including silicon or germanium with one or plural kinds of rare gases selected from helium, argon, krypton, and neon, an amorphous semiconductor film can be formed.
an amorphous semiconductor film including hydrogen can be formed using hydrogen with a flow rate of 1 to 10 times, preferably 1 to 5 times as high as that of deposition gas including silicon or germanium.
halogen such as fluorine or chlorine, or nitrogen may be added to the above hydrogenated semiconductor film.
an amorphous semiconductor film can be formed by sputtering a semiconductor such as silicon or germanium, which is used as a target, with hydrogen or rare gas.
the buffer layer 54 is preferably formed using an amorphous semiconductor film which does not include crystal grains. Therefore, if the buffer layer 54 is formed by a high-frequency plasma CVD method with a frequency of several tens of MHz to several hundreds MHz or a microwave plasma CVD method, film formation conditions are preferably controlled such that an amorphous semiconductor film does not include crystal grains.
the buffer layer 54 is partly etched to be a pair of buffer layers in a later step for forming source and drain regions.
the pair of buffer layers function as high resistant regions; thus, typically, it is preferable to form the buffer layer 54 with a thickness of from 30 to 500 nm inclusive, preferably from 50 to 200 nm inclusive.
a high voltage e.g., approximately 15 V
the buffer layer 54 is formed thickly, withstand voltage is increased, so that deterioration of the thin film transistor can be prevented even if a high voltage is applied to the thin film transistor.
the buffer layer 54 Since the buffer layer 54 is formed using an amorphous semiconductor film or an amorphous semiconductor film including hydrogen, nitrogen, or halogen, the buffer layer 54 has a larger energy gap and higher resistivity than the microcrystalline semiconductor film 53 and low mobility which is one-fifth to one-tenth that of the microcrystalline semiconductor film 53 . Therefore, in a thin film transistor to be completed later, the buffer layers formed between the source and drain regions and the microcrystalline semiconductor film 53 function as high resistant regions and the microcrystalline semiconductor film 57 including the impurity element which serves as a donor functions as a channel formation region. Accordingly, off-current of the thin film transistor can be reduced. In addition, when the thin film transistor is used as a switching element of a display device, the display device can have an improved contrast.
the buffer layer 54 can also be formed at temperatures of from 300 to 400° C. by a plasma CVD method after forming the microcrystalline semiconductor film 53 . By this treatment, hydrogen is supplied to the microcrystalline semiconductor film 53 , and the same effect as hydrogenizing the microcrystalline semiconductor film 53 can be obtained. In other words, by depositing the buffer layer 54 over the microcrystalline semiconductor film 53 , hydrogen is diffused into the microcrystalline semiconductor film 53 , so that a dangling bond can be terminated.
the thin film transistor as shown in FIG. 1D can be manufactured.
the semiconductor film 55 to which the impurity element imparting one conductivity type is added in the case where an n-channel thin film transistor is formed, phosphorus may be added as a typical impurity element, and impurity gas such as PH 3 may be added to silicon hydride.
impurity gas such as PH 3
boron may be added as a typical impurity element
impurity gas such as B 2 H 6 may be added to silicon hydride.
the semiconductor film 55 to which the impurity element imparting one conductivity type is added can be formed of a microcrystalline semiconductor or an amorphous semiconductor.
the semiconductor film 55 to which the impurity element imparting one conductivity type is added is formed with a thickness of from 2 to 50 nm inclusive. By forming a semiconductor film to which an impurity element imparting one conductivity type is added with a small thickness, throughput can be improved.
the resist mask 56 is formed over the semiconductor film 55 to which the impurity element imparting one conductivity type is added.
the resist mask 56 is formed by a photolithography technique.
the resist mask 56 is formed by exposing a resist that is applied on the semiconductor film 55 to which the impurity element imparting one conductivity type is added to light and developing the resist.
the microcrystalline semiconductor film 58 and the source and drain regions have a larger distance therebetween, so that leakage current between the microcrystalline semiconductor film 61 and the source and drain regions formed over the buffer layer can be prevented.
leakage current between wirings and the microcrystalline semiconductor film 61 can also be prevented.
the inclination angle of the side surfaces of the end portions of the microcrystalline semiconductor film 61 , the microcrystalline semiconductor film 58 , and the buffer layer 62 is from 30° to 90°, preferably from 45° to 80°. With such an angle, disconnection of the wirings due to a step shape can be prevented.
conductive films 65 a to 65 c are formed over the semiconductor film 63 to which the impurity element imparting one conductivity type is added and the gate insulating film 52 b , and then, a resist mask 66 is formed over the conductive films 65 a to 65 c .
the conductive films 65 a to 65 are formed by a sputtering method, a CVD method, a printing method, a droplet discharge method, a vapor deposition method, or the like.
the resist mask 66 can be formed in a manner similar to the resist mask 56 .
the conductive films 65 a to 65 c are partly etched to form pairs of wirings 71 a to 71 c (functioning as source and drain electrodes).
the conductive films 65 a to 65 c are etched by wet etching using the resist mask 66 that is formed by a photolithography process using a third photomask, so that the conductive films 65 a to 65 c are etched as selected. Consequently, since the conductive films 65 a to 65 c are etched isotropically, the wirings 71 a to 71 c , which have smaller areas than the resist mask 66 , can be formed.
the semiconductor film 63 to which the impurity element imparting one conductivity type is added is etched to be separated using the resist mask 66 .
a pair of source and drain regions 72 can be formed as shown in FIG. 10C .
the buffer layer 62 is also etched partly to form a pair of buffer layers 73 .
the microcrystalline semiconductor film 58 may be overetched so as to form the pair of buffer layers 73 .
the resist mask 66 is removed.
dry etching is performed under such a condition that the exposed microcrystalline semiconductor film 58 is not damaged and an etching rate with respect to the microcrystalline semiconductor film 58 is low.
an etching residue on the microcrystalline semiconductor film 58 between the source region and the drain region, a residue of the resist mask, and a contamination source in an apparatus used for removal of the resist mask can be removed, whereby the source region and the drain region can be insulated surely.
leakage current of the thin film transistor can be reduced, so that a thin film transistor with small off-current and high withstand voltage can be manufactured.
a chlorine gas can be used for an etching gas, for example.
a channel-etched thin film transistor 74 can be formed.
a protective insulating film 76 is formed over the wirings 71 a to 71 c , the source and drain regions 72 , the pair of buffer layers 73 , the microcrystalline semiconductor film 58 , and the gate insulating film 52 b .
the protective insulating film 76 can be formed in a similar manner to the gate insulating films 52 a and 52 b .
the protective insulating film 76 prevents intrusion of a contaminating impurity such as an organic matter, a metal, or water vapor included in the air; thus, a dense film is preferably used for the protective insulating film 76 .
the oxygen concentration in the buffer layers 73 can be set to be less than or equal to 5 ⁇ 10 19 atoms/cm 3 , preferably less than or equal to 1 ⁇ 10 19 atoms/cm 3 , which prevents the pair of buffer layers 73 from being oxidized.
FIG. 11B is a cross-sectional view taken along a line A-B in FIG. 12C .
the pixel electrode 77 can be formed of a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.
a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.
the pixel electrode 77 can be formed using a conductive composition including a conductive high-molecular compound (also referred to as a conductive polymer). It is preferable that a pixel electrode formed using a conductive composition have sheet resistance of less than or equal to 10000 ⁇ /square, and light transmittance of greater than or equal to 70% at a wavelength of 550 nm. In addition, the resistivity of the conductive high-molecular compound which is included in the conductive composition is preferably less than or equal to 0.1 ⁇ cm.
a “ ⁇ electron conjugated conductive high-molecular compound” can be used as the conductive high-molecular compound.
examples thereof include polyaniline and derivatives thereof, polypyrrole and derivatives thereof, polythiophene and derivatives thereof, and copolymers of two or more kinds of them.
the pixel electrode 77 is formed as follows: an ITO film is formed by a sputtering method, and a resist is applied on the ITO film, exposed to light, and developed using a fifth photomask, thereby forming a resist mask; then, the ITO film is etched using the resist mask to form the pixel electrode 77 .
a gate electrode 51 is formed over a substrate 50 , and a gate insulating film 52 a is formed over the gate electrode 51 .
a gate insulating film 59 including an impurity element which serves as a donor is formed over the gate insulating film 52 a , and a microcrystalline semiconductor film 53 is formed over the gate insulating film 59 by a plasma CVD method using deposition gas including silicon or germanium, and hydrogen.
FIG. 13 is a typical example of a timing chart for describing steps of forming the gate insulating film 52 a , the gate insulating film 59 including the impurity element which serves as a donor, and the microcrystalline semiconductor film 53 .
FIG. 13 shows a procedure starting from a step of vacuum evacuation 440 from atmospheric pressure in a reaction chamber.
the precoating treatment 441 , the substrate carrying-in 442 , the film formation treatment ( 1 ) 443 for forming the gate insulating film 52 a , the vacuum evacuation treatment 444 , the vacuum evacuation treatment 446 , and the substrate carrying-out 449 are the same as in FIG. 8 , and the film formation treatment ( 2 ) 450 for forming the gate insulating film 59 including the impurity element which serves as a donor and the film formation treatment ( 3 ) 451 for forming the microcrystalline semiconductor film 53 are carried out between the vacuum evacuation treatment 444 and the substrate carrying-out 449 .
gas including the impurity element which serves as a donor is introduced to source gas for forming the gate insulating film.
silane, dinitrogen monoxide, and 0.001% to 1% phosphine are introduced to the reaction chamber, and a silicon oxynitride film including phosphorus is formed by glow discharge plasma.
deposition gas including silicon or germanium, which is silane in this example, hydrogen, and/or rare gas are introduced and mixed in the reaction chamber, and a microcrystalline semiconductor film is formed by glow discharge plasma which is generated by application of high-frequency power.
Silane is diluted with hydrogen and/or rare gas to be 10 to 2000 times thinner. Therefore, a large amount of hydrogen and/or rare gas is needed.
the substrate heating temperature is from 100 to 300° C., preferably from 120 to 220° C.
the substrate is carried out of the reaction chamber, and the microcrystalline semiconductor film 53 is formed in a different reaction chamber, whereby the microcrystalline semiconductor film 53 , which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed.
the thin film transistor as shown in FIG. 2A can be manufactured.
an element substrate which can be used for a display device can be formed.
FIG. 15 is a typical example of a timing chart for describing steps of forming the gate insulating film 52 a , the gate insulating film 59 including the impurity element which serves as a donor, and the microcrystalline semiconductor film 53 .
FIG. 15 shows a procedure starting from a step of vacuum evacuation 440 from atmospheric pressure in a reaction chamber.
a precoating treatment 441 substrate carrying-in 442 , a film formation treatment ( 1 ) 443 for forming the gate insulating film 52 a , a vacuum evacuation treatment 444 , a flush treatment 447 , a film formation treatment ( 2 ) 457 for forming the gate insulating film 59 including the impurity element which serves as a donor, a vacuum evacuation treatment 446 , a film formation treatment ( 3 ) 451 for forming the microcrystalline semiconductor film 53 , and substrate carrying-out 449 .
the precoating treatment 441 , the substrate carrying-in 442 , the film formation treatment ( 1 ) 443 for forming the gate insulating film 52 a , the vacuum evacuation treatment 444 , the vacuum evacuation treatment 446 , the film formation treatment ( 3 ) 451 for forming the microcrystalline semiconductor film 53 , and the substrate carrying-out 449 are the same as in FIG. 13 , and the flush treatment 447 and the film formation treatment ( 2 ) 457 for forming the gate insulating film 59 including the impurity element which serves as a donor are carried out between the vacuum evacuation treatment 444 and the vacuum evacuation treatment 446 .
gas including the impurity element which serves as a donor is introduced to the reaction chamber, and the impurity element which serves as a donor is adsorbed onto the surface of the gate insulating film 52 a , furthermore, onto the inner wall of the reaction chamber.
0.001% to 1% phosphine (diluted with hydrogen or silane) is introduced to the reaction chamber.
hydrogen may be introduced as designated by a dashed line 462
deposition gas including silicon or germanium may be introduced as designated by a dashed line 461 , to the reaction chamber.
source gases which are hydrogen, silane, and dinitrogen monoxide in this example
a silicon oxynitride film is formed by glow discharge plasma which is generated by application of high-frequency power.
the silicon oxynitride film is deposited while taking in the impurity element which serves as a donor and is deposited over the surface of the gate insulating film 52 a and is adsorbed onto the surface of the inner wall of the reaction chamber, which is phosphorus in this example.
a silicon oxynitride film including phosphorus can be formed.
the film formation treatment ( 3 ) 451 for forming the microcrystalline semiconductor film 53 in order to form a microcrystalline semiconductor film which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, the following process is carried out.
gas including the impurity element which serves as a donor which is phosphine in this example, is introduced to the reaction chamber, and then, introduction of phosphine is shalted, and a silicon oxynitride film is formed, so that almost all phosphorus in the reaction chamber is included in the silicon oxynitride film.
the microcrystalline semiconductor film 53 which is formed later, does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS.
the substrate is carried out of the reaction chamber, and the inside of the reaction chamber is cleaned, and then, the substrate is carried into the reaction chamber again, and the microcrystalline semiconductor film 53 is formed, whereby the microcrystalline semiconductor film 53 , which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed.
the substrate is carried out of the reaction chamber, and the microcrystalline semiconductor film 53 is formed in a different reaction chamber, whereby the microcrystalline semiconductor film 53 , which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed.
the thin film transistor as shown in FIG. 2A can be manufactured.
an element substrate which can be used for a display device can be formed.
the thin film transistor as shown in FIG. 2E can be manufactured in which the microcrystalline semiconductor film 61 including the impurity element which serves as a donor is formed over the gate insulating film 59 including the impurity element which serves as a donor.
the microcrystalline semiconductor film 61 including the impurity element which serves as a donor may be formed in such a manner that after phosphine is introduced to a reaction chamber in forming the gate insulating film 59 including the impurity element which serves as a donor, a microcrystalline semiconductor film is formed while taking in phosphine remaining in the reaction chamber.
phosphine when the microcrystalline semiconductor film is formed, phosphine may be introduced to the reaction chamber in addition to silane and hydrogen and/or argon. Further alternatively, after the gate insulating film 59 including the impurity element which serves as a donor is formed, phosphine may be supplied to the reaction chamber and attached to the inner wall of the reaction chamber, and then, the microcrystalline semiconductor film is formed.
a gate electrode 51 is formed over a substrate 50 .
the substrate 50 is carried into the reaction chamber, and then, gate insulating films and a microcrystalline semiconductor film are deposited over the gate electrode 51 .
the impurity element which serves as a donor is released from the protective film formed on the inner wall of the reaction chamber to the inside of the reaction chamber.
the gate insulating films and the microcrystalline semiconductor film are formed while taking in the impurity element which serves as a donor and is released from the protective film, so that gate insulating films each including the impurity element which serves as a donor and a microcrystalline semiconductor film including the impurity element which serves as a donor can be formed over the gate electrode 51 .
a process for forming a silicon nitride film including phosphorus, a silicon oxynitride film including phosphorus, and a microcrystalline silicon film including phosphorus is described in chronological order with reference to FIG. 16 .
FIG. 16 is a typical example of a timing chart for describing steps of forming gate insulating films 59 a and 59 b and a microcrystalline semiconductor film 67 each including an impurity element which serves as a donor.
FIG. 16 shows a procedure starting from a step of vacuum evacuation 440 from atmospheric pressure in a reaction chamber.
a precoating treatment 452 substrate carrying-in 442 , a film formation treatment ( 1 ) 453 for forming the gate insulating film 59 a including the impurity element which serves as a donor, a vacuum evacuation treatment 444 , a film formation treatment ( 2 ) 454 for forming the gate insulating film 59 b including the impurity element which serves as a donor, a vacuum evacuation treatment 446 , a film formation treatment ( 3 ) 455 for forming the microcrystalline semiconductor film 67 including the impurity element which serves as a donor, and substrate carrying-out 449 .
the inner wall of the reaction chamber of the plasma CVD apparatus is precoated with, as a protective film, a film having composition that is the same as or similar to the gate insulating film including the impurity element which serves as a donor.
a protective film a film having composition that is the same as or similar to the gate insulating film including the impurity element which serves as a donor.
deposition gas including silicon or germanium, which is silane in this example, hydrogen, and at least one of ammonia, dinitrogen monoxide, and nitrogen are introduced to the reaction chamber.
a silicon oxynitride film including phosphorus, a silicon oxide film including phosphorus, a silicon nitride film including phosphorus, or a silicon nitride oxide film including phosphorus is formed. Accordingly, it is possible to prevent a metal used to form the reaction chamber from entering the gate insulating films as an impurity and to add the impurity element which serves as a donor to the gate insulating films and the microcrystalline semiconductor film, which are formed later.
the substrate carrying-in 442 the substrate is carried into the reaction chamber from a load lock chamber connected to the reaction chamber. Before and after the substrate carrying-in, the pressure in the reaction chamber is reduced for performing vacuum evacuation. At that time, the impurity element which serves as a donor is released from the precoating protective film formed on the inner wall of the reaction chamber into the inside of the reaction chamber.
source gases which are hydrogen, silane, and ammonia in this example
source gases which are hydrogen, silane, and ammonia in this example
a silicon nitride film is deposited by glow discharge plasma which is generated by application of high-frequency power, while taking in the impurity element which serves as a donor and is released into the inside of the reaction chamber, which is phosphorus in this example.
glow discharge plasma spreads to the inner wall of the reaction chamber, the impurity element which serves as a donor, which is phosphorus in this example, is released from the precoating protective film formed on the inner wall of the reaction chamber, in addition to the above source gases.
a silicon nitride film including phosphorus can be formed.
Nitrogen may also be introduced to the reaction chamber in addition to the above source gases.
vacuum evacuation treatment 444 vacuum evacuation is performed in the reaction chamber to a predetermined degree of vacuum.
source gases which are hydrogen, silane, and dinitrogen monoxide in this example
source gases which are hydrogen, silane, and dinitrogen monoxide in this example
a silicon oxynitride film is deposited by glow discharge plasma which is generated by application of high-frequency power, while taking in the impurity element which serves as a donor and is released into the inside of the reaction chamber, which is phosphorus in this example.
introduction of the above source gases is halted, and the power is turned off, and then, generation of plasma is halted.
vacuum evacuation treatment 446 vacuum evacuation is performed in the reaction chamber to a predetermined degree of vacuum.
the film formation treatment ( 3 ) 455 for forming the microcrystalline semiconductor film 67 including the impurity element which serves as a donor deposition gas including silicon or germanium, which is silane in this example, hydrogen, and/or rare gas are introduced and mixed in the reaction chamber, and a microcrystalline semiconductor film is formed by glow discharge plasma which is generated by application of high-frequency power.
Silane is diluted with hydrogen and/or rare gas to be 10 to 2000 times thinner. Therefore, a large amount of hydrogen and/or rare gas is needed.
the substrate heating temperature is from 100 to 300° C., preferably from 120 to 220° C.
the microcrystalline semiconductor film is deposited while taking in the impurity element which serves as a donor and is released into the inside of the reaction chamber, and thus, a microcrystalline semiconductor film including phosphorus is formed. Therefore, an amorphous semiconductor is not formed in an early stage of deposition of the semiconductor film, and crystals grow in a direction of the normal to the gate insulating film 59 b, and a microcrystalline semiconductor film with high crystallinity in which column-like microcrystalline semiconductors are present can be formed. Further, a highly conductive microcrystalline semiconductor film including the impurity element which serves as a donor can be formed.
This mode has a feature that the gate insulating films 59 a and 59 b and the microcrystalline semiconductor film 67 each including the impurity element which serves as a donor are formed. It is preferable that a peak concentration of the impurity element which serves as a donor be from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, more preferably 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
the substrate is carried out of the reaction chamber and carried into a load lock chamber connected to the reaction chamber.
the pressure in the reaction chamber at this time is the same as that in the load lock chamber.
a buffer layer 54 and a semiconductor film 55 to which an impurity element imparting one conductivity type is added are formed over the microcrystalline semiconductor film 67 including the impurity element which serves as a donor.
the thin film transistor as shown in FIG. 3A can be manufactured.
an element substrate which can be used for a display device can be formed.
the thin film transistor as shown in FIG. 4C can be manufactured. In order to form the microcrystalline semiconductor film 53 , the following process is carried out.
the gate insulating film 59 b including the impurity element which serves as a donor begins to be deposited, gas including the impurity element which serves as a donor, which is phosphine in this example, is introduced to a reaction chamber, and then, introduction of phosphine is stopped, and a silicon oxynitride film is formed, so that almost all phosphorus in the reaction chamber is included in the silicon oxynitride film. Therefore, the microcrystalline semiconductor film 53 , which is formed later, does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS.
the microcrystalline semiconductor film 53 which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed in such a manner that after the gate insulating film 59 b including the impurity element which serves as a donor is formed, the substrate is carried out of the reaction chamber, and the inside of the reaction chamber is cleaned, and then, the substrate is carried into the reaction chamber again and the microcrystalline semiconductor film 53 is formed.
the microcrystalline semiconductor film 53 which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed in such a manner that after the gate insulating film 59 b including the impurity element which serves as a donor is formed, the substrate is carried out of the reaction chamber, and the microcrystalline semiconductor film 53 is formed in a different reaction chamber.
FIG. 18 is a typical example of a timing chart for describing steps of forming the gate insulating films 59 a and 59 b each including the impurity element which serves as a donor and the microcrystalline semiconductor film 67 including the impurity element which serves as a donor as shown in FIG. 17A .
FIG. 18 shows a procedure starting from a step of vacuum evacuation 440 from atmospheric pressure in a reaction chamber.
the precoating treatment 441 , the substrate carrying-in 442 , and the substrate carrying-out 449 are the same as in FIG. 13 , and the flush treatment 447 , the film formation treatment ( 1 ) 456 for forming the gate insulating film 59 a including the impurity element which serves as a donor, the vacuum evacuation treatment 444 , the film formation treatment ( 2 ) 457 for forming the gate insulating film 59 b including the impurity element which serves as a donor, the vacuum evacuation treatment 446 , and the film formation treatment ( 3 ) 455 for forming the microcrystalline semiconductor film 67 including the impurity element which serves as a donor are carried out between the substrate carrying-in 442 and the substrate carrying-out 449 .
gas including an impurity element which serves as a donor is introduced to a reaction chamber, and the impurity element which serves as a donor is adsorbed onto the substrate 50 , the surface of the gate electrode 51 , and furthermore, onto the inner wall of the reaction chamber.
0.001% to 1% phosphine (diluted with hydrogen) is introduced to the reaction chamber.
hydrogen may be introduced as designated by a dashed line 462
deposition gas including silicon or germanium may be introduced as designated by a dashed line 461 , to the reaction chamber.
source gases which are hydrogen, silane, and ammonia in this example
source gases which are hydrogen, silane, and ammonia in this example
a silicon nitride film is formed by glow discharge plasma which is generated by application of high-frequency power.
Nitrogen may be introduced to the reaction chamber in addition to the above source gases.
the silicon nitride film is deposited while taking in the impurity element which serves as a donor and is adsorbed onto the substrate 50 , the gate electrode 51 , and furthermore, the surface of the inner wall of the reaction chamber, which is phosphorus in this example.
a silicon nitride film including phosphorus can be formed.
vacuum evacuation treatment 444 vacuum evacuation is performed in the reaction chamber to a predetermined degree of vacuum.
the film formation treatment ( 2 ) 457 for forming the gate insulating film 59 b including the impurity element which serves as a donor source gases, which are hydrogen, silane, and dinitrogen monoxide in this example, are introduced and mixed, and a silicon oxynitride film is formed by glow discharge plasma which is generated by application of high-frequency power.
the silicon oxynitride film is deposited while taking in the impurity element which serves as a donor and is deposited over the surface of the gate insulating film 59 a including the impurity element which serves as a donor, and the impurity element which serves as a donor and is adsorbed onto the surface of the inner wall of the reaction chamber, which is phosphorus in this example.
the film formation treatment ( 3 ) 455 for forming the microcrystalline semiconductor film 67 including the impurity element which serves as a donor deposition gas including silicon or germanium, which is silane in this example, hydrogen, and/or rare gas are introduced and mixed in the reaction chamber, and a microcrystalline semiconductor film is formed by glow discharge plasma which is generated by application of high-frequency power.
Silane is diluted with hydrogen and/or rare gas to be 10 to 2000 times thinner. Therefore, a large amount of hydrogen and/or rare gas is needed.
the substrate heating temperature is from 100 to 300° C., preferably from 120 to 220° C. It is preferable that the film be formed at temperatures of from 120 to 220° C.
This mode has a feature that the gate insulating films 59 a and 59 b and the microcrystalline semiconductor film 67 each including the impurity element which serves as a donor are formed. It is preferable that a peak concentration of the impurity element which serves as a donor is from 6 ⁇ 10 15 to 3 ⁇ 10 18 atoms/cm 3 inclusive, more preferably from 3 ⁇ 10 16 to 3 ⁇ 10 17 atoms/cm 3 inclusive.
the substrate is carried out of the reaction chamber and carried into a load lock chamber connected to the reaction chamber.
the pressure in the reaction chamber at this time is the same as that in the load lock chamber.
a buffer layer 54 and a semiconductor film 55 to which an impurity element imparting one conductivity type is added are formed over the microcrystalline semiconductor film 67 including the impurity element which serves as a donor.
the thin film transistor as shown in FIG. 3A can be manufactured.
an element substrate which can be used for a display device can be formed.
the thin film transistor as shown in FIG. 4C can be manufactured. In order to form the microcrystalline semiconductor film 53 , the following process is carried out.
the microcrystalline semiconductor film 53 which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed in such a manner that after the gate insulating film 59 b including the impurity element which serves as a donor is formed, the substrate is carried out of the reaction chamber, and the inside of the reaction chamber is cleaned, and then, the substrate is carried into the reaction chamber again and the microcrystalline semiconductor film 53 is formed.
the microcrystalline semiconductor film 53 which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed in such a manner that after the gate insulating film 59 b including the impurity element which serves as a donor is formed, the substrate is taken out of the reaction chamber, and the microcrystalline semiconductor film 53 is formed in a different reaction chamber.
FIG. 20 is a typical example of a timing chart for describing steps of forming the gate insulating films 52 a and 52 b , the gate insulating film 59 c including the impurity element which serves as a donor, and a microcrystalline semiconductor film 53 over a gate electrode 51 and a substrate 50 as shown in FIG. 21 .
FIG. 20 shows a procedure starting from a step of vacuum evacuation 440 from atmospheric pressure in a reaction chamber.
a precoating treatment 441 substrate carrying-in 442 , a film formation treatment ( 1 ) 443 for forming the gate insulating film 52 a , a vacuum evacuation treatment 444 , a film formation treatment ( 2 ) 445 for forming the gate insulating film 52 b , a vacuum evacuation treatment 446 , a flush treatment 447 , a film formation treatment ( 4 ) 458 for forming the gate insulating film 59 c including the impurity element which serves as a donor, a vacuum evacuation treatment 459 , a film formation treatment ( 3 ) 451 for forming the microcrystalline semiconductor film 53 , and substrate carrying-out 449 .
the precoating treatment 441 , the substrate carrying-in 442 , the film formation treatment ( 1 ) 443 for forming the gate insulating film 52 a , the vacuum evacuation treatment 444 , the film formation treatment ( 2 ) 445 for forming the gate insulating film 52 b , the vacuum evacuation treatment 446 , and the substrate carrying-out 449 are the same as in FIG. 8 ; the film formation treatment ( 3 ) 451 for forming the microcrystalline semiconductor film 53 is the same as in FIG.
gas including an impurity element which serves as a donor is introduced to the reaction chamber, and the impurity element which serves as a donor is adsorbed onto the surface of the gate insulating film 52 b , furthermore, onto the inner wall of the reaction chamber.
0.001% to 1% phosphine (diluted with hydrogen) is introduced to the reaction chamber.
hydrogen may be introduced as designated by a dashed line 462 , or deposition gas including silicon or germanium may be introduced as designated by a dashed line 461 , to the reaction chamber.
the film formation treatment ( 4 ) 458 for forming the gate insulating film 59 c including the impurity element which serves as a donor source gases of the gate insulating film, which are hydrogen, silane, and ammonia in this example, are introduced and mixed, and a silicon nitride film is formed by glow discharge plasma which is generated by application of high-frequency power.
the silicon nitride film is deposited while taking in the impurity element which serves as a donor and is deposited over the surface of the gate insulating film 59 b, and the impurity element which serves as a donor and is adsorbed onto the surface of the inner wall of the reaction chamber, which is phosphorus here.
a silicon nitride film including phosphorus can be formed.
vacuum evacuation treatment 459 vacuum evacuation is performed in the reaction chamber to a predetermined degree of vacuum.
the microcrystalline semiconductor film 53 is formed over the gate insulating film 59 c including the impurity element which serves as donor.
the amount of gas including the impurity element which serves as a donor, which is phosphine in this example, to be introduced to the reaction chamber is controlled in the flush treatment 447 , so that the microcrystalline semiconductor film 53 , which is formed later, does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS.
the substrate is carried out of the reaction chamber, and the inside of the reaction chamber is cleaned, and then, the substrate is carried into the reaction chamber again, and the microcrystalline semiconductor film 53 is formed, whereby the microcrystalline semiconductor film 53 , which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed.
the substrate is carried out of the reaction chamber, and the microcrystalline semiconductor film 53 is formed in a different reaction chamber, whereby the microcrystalline semiconductor film 53 , which does not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS, can be formed.
the gate insulating film 52 b may be nitrided with high-density plasma, whereby a silicon nitride layer including the impurity element which serves as a donor can be formed on the surface of the gate insulating film 52 b .
the high-density plasma is generated by use of high-frequency microwaves, for example, microwaves with a frequency of 2.45 GHz.
high-density plasma which has the characteristic of having a low electron temperature
a layer can be formed with less plasma damage and fewer defects compared to a layer formed by conventional plasma treatment because the kinetic energy of an active species is low.
carrier mobility can be increased because the level of roughness on the surface of the gate insulating film 52 b can be reduced.
the gate insulating film 59 c including the impurity element which serves as a donor can also be formed using gas including the impurity element which serves as a donor as designated by a dashed line 463 shown in FIG. 20 in addition to the source gas for forming the gate insulating film, without performing the flush treatment 447 shown in FIG. 20 .
the thin film transistor as shown in FIG. 7C can be manufactured.
glow discharge plasma is generated by applying high-frequency power with a frequency of from 1 to 20 MHz, typically 13.56 MHz; or high-frequency power with a frequency in the VHF band of 20 to 120 MHz approximately.
helium may be added as rare gas to reaction gas, in addition to silane and hydrogen.
Helium has an ionization energy of 24.5 eV, which is the highest among all the gases, and a metastable state thereof lies in a level of 20 eV approximately, which is a little lower than the above ionization energy; thus, to be ionized, helium requires as low as 4 eV, which is the difference between the ionization energy and the metastable energy, while keeping electric discharge. Therefore, helium starts to discharge electricity at the lowest voltage among all the gases. Because of the above property, helium can stably retain plasma. Further, uniform plasma can be formed with helium, and thus a plasma density can be uniform even when a microcrystalline silicon film is deposited over a large substrate.
the gate insulating film and/or the microcrystalline semiconductor film includes the impurity element which serves as a donor.
crystallinity of the microcrystalline semiconductor film at the interface with the gate insulating film is high and crystallinity of the microcrystalline semiconductor film can be improved.
a thin film transistor including the microcrystalline semiconductor film has higher field effect mobility and higher on-current than a thin film transistor including an amorphous semiconductor film or a conventional microcrystalline semiconductor film.
the area of the channel formation region that is, the area of the thin film transistor can be decreased.
the area of the thin film transistor in each pixel is reduced, whereby the aperture ratio of the pixel can be increased. Accordingly, the display device can have high definition.
an amorphous semiconductor film with high resistivity is formed as the buffer layer between the microcrystalline semiconductor film which serves as a channel formation region and the semiconductor film to which the impurity element imparting one conductivity type is added and which functions as source and drain regions.
FIG. 22 shows an example of a multi-chamber plasma CVD apparatus including a plurality of reaction chambers.
the apparatus is provided with a common chamber 423 , a load/unload chamber 422 , a first reaction chamber 400 a , a second reaction chamber 400 b , and a third reaction chamber 400 c .
This apparatus is a single-wafer processing type in which a substrate set in a cassette in the load/unload chamber 422 is transferred to/from each reaction chamber by a transfer unit 426 provided for the common chamber 423 .
a gate valve 425 is provided between the common chamber 423 and each chamber such that treatments performed in different reaction chambers do not interfere each other.
Each reaction chamber is used for a different purpose, depending on the kind of a thin film to be formed.
an insulating film such as a gate insulating film is formed in the first reaction chamber 400 a ; a microcrystalline semiconductor film which forms a channel and a buffer layer are formed in the second reaction chamber 400 b ; and a semiconductor film to which an impurity element imparting one conductivity type is added and which forms a source and a drain is formed in the third reaction chamber 400 c.
the number of the reaction chambers is not limited to three, and can be increased or decreased as needed.
One film may be formed in one reaction chamber, or a plurality of films may be formed in one reaction chamber.
a turbo-molecular pump 419 and a dry pump 420 are connected to each reaction chamber as an exhaust unit.
the exhaust unit is not limited to a combination of these vacuum pumps and can employ other vacuum pumps as long as they can evacuate the reaction chamber to a degree of vacuum of approximately 10 ⁇ 5 to 10 ⁇ 1 Pa.
a butterfly valve 417 is provided between the exhaust unit 430 and each reaction chamber, which can interrupt vacuum evacuation, and a conductance valve 418 can control exhaust velocity to adjust the pressure in each reaction chamber.
phosphine which is one of gases including an impurity element which serves as a donor, is supplied to the first reaction chamber 400 a and the second reaction chamber 400 b .
a gas supply unit 408 a supplies argon, and a gas supply unit 408 f supplies etching gas used for cleaning the inside of the reaction chambers.
the gas supply units 408 a and 408 f are provided in common for each reaction chamber.
a high-frequency power supply unit 403 for generating plasma is connected to each reaction chamber.
the high-frequency power supply unit 403 includes a high-frequency power source 404 and a matching box 406 .
FIG. 23 shows a structure in which a fourth reaction chamber 400 d is added to the structure of the multi-chamber plasma CVD apparatus of FIG. 22 .
a gas supply unit 408 b is connected to the fourth reaction chamber 400 d.
High-frequency power supply units and evacuation units have the same structure as those of FIG. 22 .
Each reaction chamber can be used for a different purpose, depending on the kind of a thin film to be formed.
an insulating film such as a gate insulating film can be formed in the first reaction chamber 400 a ; a semiconductor film and a microcrystalline semiconductor film for forming a channel formation region can be formed in the second reaction chamber 400 b ; a buffer layer that protects the microcrystalline semiconductor film for forming a channel formation region can be formed in the fourth reaction chamber 400 d; and a semiconductor film to which an impurity element imparting one conductivity type is added and which forms a source and a drain can be formed in the third reaction chamber 400 c. Since each thin film has an optimum temperature for being formed, each thin film is formed in a different reaction chamber, whereby film formation temperatures can be easily controlled. Further, the same kind of films can be formed repeatedly, so that an influence of residual impurities due to a film which has been formed can be eliminated.
a microcrystalline semiconductor film, a buffer layer, and a semiconductor film to which an impurity element imparting one conductivity type is added may be formed successively in one reaction chamber. Specifically, a substrate provided with a gate insulating film is carried into a reaction chamber, and a microcrystalline semiconductor film, a buffer layer, and a semiconductor film to which an impurity element imparting one conductivity type is added are formed therein successively. Then, after the substrate is carried out of the reaction chamber, the inside of the reaction chamber is cleaned with fluorine radicals. However, even when the inside of the reaction chamber is cleaned, an impurity element which serves as a donor remains in the reaction chamber in some cases.
the microcrystalline semiconductor film When a substrate provided with a gate insulating film is carried into such a reaction chamber and a microcrystalline semiconductor film is formed, the microcrystalline semiconductor film includes the impurity element which serves as a donor. Accordingly, a microcrystalline semiconductor film which has high crystallinity at the interface with a gate insulating film and includes an impurity element which serves as a donor can be formed.
FIGS. 24A and 24B a method for manufacturing a thin film transistor which is different from that in the above mode is described with reference to FIGS. 24A and 24B , FIGS. 25A to 25D , FIGS. 26A to 26C , FIGS. 27A and 27B , FIGS. 28A and 28B , FIGS. 29A to 29C , and FIGS. 30A to 30C .
a process is shown through which the number of photomasks can be smaller than that used in the above modes and through which a thin film transistor can be manufactured.
a manufacturing process of the thin film transistor shown in FIG. 1A is described here; however, the following mode can be applied to the manufacturing processes of the thin film transistors shown in FIG. 1D , FIGS. 2A and 2E , FIG. 3A , FIGS. 4A and 4C , and FIG. 5A .
a conductive film is formed over a substrate 50 ; a resist is applied on the conductive film; and a part of the conductive film is etched using a resist mask that is formed by a photolithography process using a first photomask, so that a gate electrode 51 is formed. Then, as shown in FIG. 24A , gate insulating films 52 a and 52 b are formed over the gate electrode 51 . In a similar manner to FIGS. 9B and 9C , a microcrystalline semiconductor film 57 including an impurity element which serves as a donor is formed.
the resist 80 can be a positive type or a negative type. In this case, a positive resist is used.
the resist 80 is irradiated with light using a multi-tone photomask 159 as a second photomask, to expose the resist 80 to light.
a multi-tone photomask can achieve three levels of light exposure to obtain an exposed portion, a half-exposed portion, and an unexposed portion; one-time exposure and development process allows a resist mask with regions of plural thicknesses (typically, two kinds of thicknesses) to be formed. Thus, the use of a multi-tone photomask can reduce the number of photomasks.
Typical examples of a multi-tone photomask include a gray-tone mask 159 a shown in FIG. 25A and a half-tone mask 159 b shown in FIG. 25C .
the gray-tone mask 159 a includes a light-transmitting substrate 163 provided with a light-blocking portion 164 and a diffraction grating 165 .
the light transmittance of the light-blocking portion 164 is 0%.
the diffraction grating 165 has a light-transmitting portion in a slit form, a dot form, a mesh form, or the like with intervals which are less than or equal to the resolution limit of light used for the exposure, whereby the light transmittance can be controlled.
the diffraction grating 165 can be in a slit form, a dot form, or a mesh form with regular intervals; or in a slit form, a dot form, or a mesh form with irregular intervals.
a substrate having a light-transmitting property such as a quartz substrate
the light-blocking portion 164 and the diffraction grating 165 can be formed using a light-blocking material such as chromium or chromium oxide, which absorbs light.
a light transmittance 166 of the light-blocking portion 164 is 0% and that of a region where neither the light-blocking portion 164 nor the diffraction grating 165 is provided is 100%, as shown in FIG. 25B .
the light transmittance of the diffraction grating 165 can be controlled in a range of from 10 to 70%.
the light transmittance of the diffraction grating 165 can be controlled with an interval or a pitch of slits, dots, or meshes of the diffraction grating 165 .
the half-tone mask 159 b includes a light-transmitting substrate 163 provided with a semi-light-transmitting portion 167 and a light-blocking portion 168 .
MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like can be used for the semi-light-transmitting portion 167 .
the light-blocking portion 168 can be formed using a light-blocking material such as chromium or chromium oxide, which absorbs light.
a light transmittance 169 of the light blocking portion 168 is 0% and that of a region where neither the light-blocking portion 168 nor the semi-light-transmitting portion 167 is provided is 100%, as shown in FIG. 25D .
the light transmittance of the semi-light-transmitting portion 167 can be controlled in a range of from 10 to 70%.
the light transmittance of the semi-light-transmitting portion 167 can be controlled with the material of the semi-light-transmitting portion 167 .
FIG. 26A is a cross-sectional view taken along a line A-B in FIG. 30A (except for the resist mask 81 ).
the conductive films 85 a to 85 c are etched to be separated using the resist mask 86 , whereby pairs of wirings 92 a to 92 c can be formed as shown in FIG. 26B .
the conductive films 85 a to 85 c are etched as selected.
the wirings 92 a to 92 c with smaller areas than the resist mask 86 can be formed.
the semiconductor film 63 to which the impurity element imparting one conductivity type is added is etched using the resist mask 86 , so that a pair of source and drain regions 88 are formed.
a part of the buffer layer 62 is also etched to form a pair of buffer layers 87 .
the source and drain regions and the pair of buffer layer can be formed in the same process.
the end portions of the wirings 92 a to 92 c are not aligned with those of the source and drain regions 88 , and the end portions of the source and drain regions 88 are formed outside those of the wirings 92 a to 92 c .
the resist mask 86 is removed.
dry etching is performed under such a condition that the exposed microcrystalline semiconductor film 61 is not damaged and an etching rate with respect to the microcrystalline semiconductor film 61 is low.
an etching residue on the microcrystalline semiconductor film 61 between the source region and the drain region, a residue of the resist mask, and a contamination source in an apparatus used for removal of the resist mask can be removed, whereby the source region and the drain region can be insulated surely.
leakage current of the thin film transistor can be reduced, so that a thin film transistor with small off-current and high withstand voltage can be manufactured.
a chlorine gas can be used for an etching gas, for example.
the end portions of the wirings 92 a to 92 c are not aligned with those of the source and drain regions 88 , whereby the end portions of the wirings 92 a to 92 c can have a larger distance therebetween; thus, leakage current or short circuit between the wirings can be prevented. Accordingly, an inverted-staggered thin film transistor can be manufactured.
a channel-etched thin film transistor 83 can be formed.
the thin film transistor can be formed using two photomasks.
a protective insulating film 76 s is formed over the wirings 92 a to 92 c , the source and drain regions 88 , the pair of buffer layers 87 , the microcrystalline semiconductor film 61 , the microcrystalline semiconductor film 58 including the impurity element which serves as a donor, and the gate insulating film 52 b .
the protective insulating film 76 a can be formed in a similar manner to the gate insulating films 52 a and 52 b.
FIG. 27B is a cross-sectional view taken along a line A-B in FIG. 30C .
a thin film transistor and an element substrate which has the thin film transistor and can be used for a display device can be formed.
an insulating film 101 is formed over the protective insulating film 76 a as shown in FIG. 28A .
the insulating film 101 is formed using a photosensitive organic resin here.
the insulating film 101 is exposed to light using a multi-tone photomask 160 and developed, whereby an insulating film 102 having a recessed portion 111 a that exposes the protective insulating film 76 a covering the wirings of the thin film transistor and a recessed portion 111 b over a capacitor wiring 51 c is formed as shown in FIG. 28B .
the multi-tone photomask 160 the insulating film 101 can be exposed to light by 100% over the wirings of the thin film transistor, and the insulating film 101 can be exposed to light by from 10 to 70% over the capacitor wiring 51 c.
the contact hole connecting the pixel electrode and the wiring, and the capacitor element can be formed with the use of only one multi-tone photomask.
the resist mask 66 or 86 may be removed, and the semiconductor film 63 to which the impurity element imparting one conductivity type is added may be etched using the wirings 71 a to 71 c or 92 a to 92 c as masks.
a thin film transistor in which end portions of the wirings 71 a to 71 c or 92 a to 95 c are aligned with those of the source and drain regions 72 or 88 can be formed.
the semiconductor film 63 to which the impurity element imparting one conductivity type is added is etched using the wirings 71 a to 71 c as masks, so that a thin film transistor in which end portions of source and drain regions 89 are aligned with those of the wirings 71 a to 71 c can be formed as shown in FIG. 31 .
a microcrystalline semiconductor film can also be used for a channel formation region of a channel protective thin film transistor.
an inverted-staggered thin film transistor with high electric characteristics and an element substrate provided with the inverted-staggered thin film transistor can be manufactured.
This embodiment mode describes an inverted-staggered thin film transistor as a thin film transistor, but the present invention is not limited thereto.
a method for forming an insulating film and a microcrystalline semiconductor film each including an impurity element which serves as a donor can be applied to a staggered thin film transistor, a top gate thin film transistor, and the like.
an insulating film functioning as a base film and/or a microcrystalline semiconductor film is made to include an impurity element which serves as a donor, and a gate insulating film and a gate electrode are formed over the microcrystalline semiconductor film, whereby a thin film transistor having a microcrystalline semiconductor film with high crystallinity at the interface with the insulating film can be manufactured. Accordingly, a thin film transistor with excellent electric characteristics can be formed.
a liquid crystal display device including the thin film transistor described in Embodiment Mode 1 is described below as one mode of a display device.
a vertical alignment (VA) mode liquid crystal display device is described with reference to FIGS. 32 to 34 .
the VA mode liquid crystal display device employs a method of controlling alignment of liquid crystal molecules of a liquid crystal panel.
liquid crystal molecules are aligned in a vertical direction with respect to a panel surface when a voltage is not applied.
a pixel is divided into some regions (subpixels), and molecules are aligned in different directions in their respective regions. This is referred to as multi-domain or multi-domain design.
a liquid crystal display device of multi-domain design is described.
FIGS. 32 and 33 show a pixel structure of a VA mode liquid crystal panel.
FIG. 33 is a plan view of a substrate 600 .
FIG. 32 shows a cross-sectional structure taken along a line Y-Z in FIG. 33 . The following description is made with reference to both the drawings.
a pixel of multi-domain design has a structure in which a signal applied to each of the pixel electrodes 624 and 626 is independently controlled.
the pixel electrode 624 is connected to the thin film transistor 628 through a wiring 618 in a contact hole 623 .
the pixel electrode 626 is connected to the thin film transistor 629 through a wiring 619 .
a gate wiring 602 of the thin film transistor 628 and a gate wiring 603 of the thin film transistor 629 are separated so that different gate signals can be given thereto.
a wiring 616 functioning as a data line is used in common for the thin film transistors 628 and 629 .
the thin film transistors 628 and 629 can be manufactured by the methods described in Embodiment Mode 3.
the pixel electrodes 624 and 626 have different shapes and are separated by a slit 625 .
the pixel electrode 626 surrounds the pixel electrode 624 , which has a V-shape.
the thin film transistors 628 and 629 make the timing of applying voltages to the pixel electrodes 624 and 626 different from each other, thereby controlling alignment of liquid crystals. By supplying different gate signals to the gate wirings 602 and 603 , operation timing of the TFTs 628 and 629 can be different. Further, an alignment film 648 is formed over the pixel electrodes 624 and 626 .
a counter substrate 601 is provided with a light-blocking film 632 , a coloring film 636 , and a counter electrode 640 .
a planarizing film 637 is formed between the coloring film 636 and the counter electrode 640 , thereby preventing alignment disorder of liquid crystals.
an alignment film 646 is formed on the counter electrode 640 .
FIG. 34 shows a structure of a counter substrate side.
the counter electrode 640 is shared by plural pixels, and a slit 641 is formed in the counter electrode 640 .
the slit 641 and the slit 625 on the pixel electrodes 624 and 626 side are disposed so as not to overlap with each other, thereby effectively generating an oblique electric field to control the alignment of the liquid crystals. Accordingly, the direction in which the liquid crystals are aligned can be different depending on the location, and thus a viewing angle is increased.
a substrate, a coloring film, a light-blocking film, and a planarization film form a color filter. Either the light-blocking film or the planarization film, or neither of them is not necessarily formed over the substrate.
the coloring film has a function of preferentially transmitting light of a predetermined wavelength range among light of the wavelength range of visible light.
a coloring film which preferentially transmits light of a wavelength range of red light, a coloring film which preferentially transmits light of a wavelength range of blue light, and a coloring film which preferentially transmits light of a wavelength range of green light are combined to be used for a color filter.
the combination of the coloring films is not limited to the above.
the pixel electrode 624 , a liquid crystal layer 650 , and the counter electrode 640 overlap with each other to form a first liquid crystal element. Further, the pixel electrode 626 , the liquid crystal layer 650 , and the counter electrode 640 overlap with each other to form a second liquid crystal element. Furthermore, the multi-domain structure is made in which the first liquid crystal element and the second liquid crystal element are provided for one pixel.
the element substrate formed in accordance with Embodiment Mode 1 can also be applied to an FFS mode liquid crystal display device, an IPS mode liquid crystal display device, a TN mode liquid crystal display device, and the like.
the liquid crystal display device can be manufactured through the above process. Since an inverted-staggered thin film transistor with small off-current and high electric characteristics is used for the liquid crystal display device of this embodiment mode, the liquid crystal display device has high contrast and high visibility.
FIG. 35A shows one mode of a top view of a pixel.
FIG. 35B shows one mode of a cross-sectional structure of the pixel taken along a line A-B in FIG. 35A .
a display device including a light-emitting element utilizing electroluminescence is shown as a light-emitting device.
Light-emitting elements utilizing electroluminescence are classified into two types according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter as an inorganic EL element.
the process for manufacturing the thin film transistor in accordance with Embodiment Mode 1 can be used.
an organic EL element voltage is applied to the light-emitting element, so that electrons are injected from an electrode into a layer including a light-emitting organic compound, and holes are injected from the other electrode into the layer including the light-emitting organic compound, and there flows electric current. These carriers (electrons and holes) are recombined, so that the light-emitting organic compound is placed in an excited state. The light-emitting organic compound emits light in returning to a ground state from the excited state. Because of such mechanism, such a light-emitting element is called a “light-emitting element of a current excitation type.”
Inorganic EL elements are classified into dispersive inorganic EL elements and thin film inorganic EL elements.
a dispersive inorganic EL element includes a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and light emission mechanism thereof is donor-acceptor recombination light emission, in which a donor level and an acceptor level are utilized.
a light-emitting layer is sandwiched between dielectric layers, and the dielectric layers are sandwiched between electrodes.
Light emission mechanism of the thin film inorganic EL element is local light emission, in which inner-shell electron transition of a metal ion is utilized.
an organic EL element is described as a light-emitting element.
a channel protective thin film transistor can also be used as appropriate.
a first thin film transistor 74 a is a switching thin film transistor for controlling input of a signal to a first electrode
a second thin film transistor 74 b is a driving thin film transistor for controlling current or voltage supply to a light-emitting element 94 .
a gate electrode of the first thin film transistor 74 a is connected to a scanning line 51 a .
One of a source and a drain is connected to wirings 71 a to 71 c which functions as a signal line.
the other of the source and the drain is electrically connected to a gate electrode 51 b of the second thin film transistor 74 b .
One of a source and a drain of the second thin film transistor 74 b is connected to power supply lines 93 a to 93 c , and the other of the source and the drain is electrically connected to a first electrode 79 of a display device.
a gate electrode, a gate insulating film, and the power supply line 93 a of the second thin film transistor 74 b form a capacitor element 96 , and the other of the source and the drain of the first thin film transistor 74 a is electrically connected to the capacitor element 96 .
the capacitor element 96 corresponds to a capacitor element for holding a voltage between the gate and the source or between the gate and the drain (hereinafter referred to as a gate voltage) of the second thin film transistor 74 b when the first thin film transistor 74 a is in an off-state, and is not necessarily provided.
the first thin film transistor 74 a and the second thin film transistor 74 b can be each formed using the thin film transistor described in Embodiment Mode 1.
each of the first thin film transistor 74 a and the second thin film transistor 74 b is an n-channel thin film transistor in this example
the first thin film transistor 74 a and the second thin film transistor 74 b may also be formed using an n-channel thin film transistor and a p-channel thin film transistor, respectively.
both the first thin film transistor 74 a and the second thin film transistor 74 b may be formed using p-channel thin film transistors.
a protective insulating film 76 is formed over the first thin film transistor 74 a and the second thin film transistor 74 b .
a planarization film 78 is formed over the protective insulating film 76 .
the first electrode 79 is formed to be connected to a wiring 93 f in a contact hole formed in the planarization film 78 and the protective insulating film 76 .
the planarization film 78 is preferably formed using an organic resin such as acrylic, polyimide, or polyamide, or a siloxane polymer. Since the first electrode 79 has a recessed portion in the contact hole, a partition wall 91 having an opening is provided to cover the recessed portion of the first electrode 79 .
an EL layer 92 is formed so as to be in contact with the first electrode 79 , and a second electrode 93 is formed so as to cover the EL layer 92 . Further, a protective insulating film 95 is formed so as to cover the second electrode 93 and the partition wall 91 .
a light-emitting element 94 having a top emission structure is shown as a light-emitting element.
the light-emitting element 94 with a top emission structure can emit light even over the first thin film transistor 74 a or the second thin film transistor 74 b ; thus, a light emission area can be increased.
the layers located under the EL layer 92 are uneven, the thickness is nonuniform due to unevenness, and the second electrode 93 and the first electrode 79 are short-circuited, so that a display defect is caused. Therefore, it is preferable to provide the planarization film 78 .
the light-emitting element 94 corresponds to a region where the first electrode 79 and the second electrode 93 sandwich the EL layer 92 .
light from the light-emitting element 94 is emitted to the second electrode 93 side as shown by an outline arrow.
the first electrode 79 functioning as a cathode a known conductive film can be used as long as it has a low work function and reflects light.
Ca, Al, CaF, MgAg, AlLi, or the like is preferably used.
the EL layer 92 may be formed using a single layer or by stacking a plurality of layers. When the EL layer 92 is formed using a plurality of layers, an electron-injection layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer are stacked in this order over the first electrode 79 . It is not necessary to form all of these layers.
the second electrode 93 functioning as an anode is formed using a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.
a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.
a light-emitting element having a top emission structure, in which light is emitted from a side opposite to a substrate is described here; however, a light-emitting element having a bottom emission structure, in which light is emitted from the substrate side, or a light-emitting element having a dual emission structure, in which light is emitted from both the substrate side and the side opposite to the substrate, can also be employed as appropriate.
an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.
This embodiment mode describes an example in which a thin film transistor for controlling the driving of a light-emitting element (the driving thin film transistor) is electrically connected to the light-emitting element; however, a thin film transistor for controlling current may be connected between the driving thin film transistor and the light-emitting element.
the light-emitting display device of this embodiment mode can have high contrast and high visibility because an inverted-staggered thin film transistor with small off-current and excellent electric characteristics is used.
This embodiment mode describes a structure of a display panel which is one mode of a display device of the present invention.
FIG. 36A illustrates a mode of a display panel in which a pixel portion 6012 formed over a substrate 6011 is connected to a signal line driver circuit 6013 that is formed separately.
the pixel portion 6012 and a scanning line driver circuit 6014 are formed using thin film transistors in which a microcrystalline semiconductor film is used for channel formation regions.
the signal line driver circuit 6013 may be formed using a thin film transistor in which a single-crystalline semiconductor is used for a channel formation region, a thin film transistor in which a polycrystalline semiconductor is used for a channel formation region, or a thin film transistor in which an SOI is used for a channel formation region.
the pixel portion 6012 , the signal line driver circuit 6013 , and the scanning line driver circuit 6014 are each supplied with potential of a power source, a variety of signals, and the like through an FPC 6015 . Further, a protection circuit may be provided between the signal line driver circuit 6013 and the FPC 6015 or between the signal line driver circuit 6013 and the pixel portion 6012 .
the protection circuit includes one or more elements selected from a thin film transistor, a diode, a resistor element, a capacitor element, and the like.
a diode obtained by connecting the thin film transistor described in Embodiment Mode 1 or 2 can also be used as a diode.
Both the signal line driver circuit and the scanning line driver circuit may be formed over the same substrate as the pixel portion.
FIG. 36B shows a mode of a display panel in which a signal line driver circuit 6023 is formed separately and is connected to a pixel portion 6022 and a scanning line driver circuit 6024 that are formed over a substrate 6021 .
the pixel portion 6022 and the scanning line driver circuit 6024 are each formed using a thin film transistor in which a microcrystalline semiconductor film is used for a channel formation region.
the signal line driver circuit 6023 is connected to the pixel portion 6022 through an FPC 6025 .
the pixel portion 6022 , the signal line driver circuit 6023 , and the scanning line driver circuit 6024 are each supplied with potential of a power source, a variety of signals, and the like through the FPC 6025 . Further, a protection circuit may be provided between the signal line driver circuit 6023 and the FPC 6025 or between the signal line driver circuit 6023 and the pixel portion 6022 .
FIG. 36C shows a mode of a display panel in which an analog switch 6033 a included in the signal driver circuit is formed over a substrate 6031 , over which a pixel portion 6032 and a scanning line driver circuit 6034 are formed, and a shift register 6033 b included in the signal line driver circuit is formed separately over a different substrate and then attached to the substrate 6031 .
the pixel portion 6032 and the scanning line driver circuit 6034 are each formed using a thin film transistor in which a microcrystalline semiconductor film is used for a channel formation region.
the shift register 6033 b included in the signal line driver circuit is connected to the pixel portion 6032 through an FPC 6035 .
the pixel portion 6032 , the signal line driver circuit, and the scanning line driver circuit 6034 are each supplied with a potential of a power source, a variety of signals, and the like through the FPC 6035 . Further, a protection circuit may be provided between the signal line driver circuit 6033 and the FPC 6035 or between the signal line driver circuit 6033 and the pixel portion 6032 .
an entire driver circuit or a part thereof can be formed over the same substrate as a pixel portion, using a thin film transistor in which a microcrystalline semiconductor films is used for a channel formation region.
connection method of the substrate formed separately there is no particular limitation on a connection method of the substrate formed separately, and a known method such as a COG method, a wire bonding method, or a TAB method can be used. Further, a connection position is not limited to the position illustrated in FIGS. 36A to 36C as long as electrical connection is possible. Furthermore, a controller, a CPU, a memory, and/or the like may be formed separately and connected.
the signal line driver circuit used in the present invention includes a shift register and an analog switch.
another circuit such as a buffer, a level shifter, or a source follower may be included.
the shift register and the analog switch are not necessarily provided.
a different circuit such as a decoder circuit by which a signal line can be selected may be used instead of the shift register, or a latch or the like may be used instead of the analog switch.
Display devices or the like that are obtained according to the present invention can be used for active matrix display panels. That is to say, the present invention can be carried out in all electronic devices in which these display panels are incorporated into display portions.
Examples of such electronic devices include cameras such as video cameras and digital cameras, displays that can be mounted on a person's head (goggle-type displays), car navigation systems, projectors, car stereos, personal computers, portable information terminals (e.g., mobile computers, mobile phones, and electronic books). Examples of these devices are illustrated in FIGS. 37A to 37D .
FIG. 37A illustrates a television device.
a television device can be completed by incorporating a display panel into a chassis as illustrated in FIG. 37A .
a main screen 2003 is formed with a display panel.
a speaker unit 2009 is provided as accessory equipment. In this manner, a television device can be completed.
a display panel 2002 including display elements is incorporated into a chassis 2001 .
communication of information in one direction (from a transmitter to a receiver) or in two directions (between a transmitter and a receiver or between receivers) can be performed by connection to a wired or wireless communication network through a modem 2004 .
the television device can be operated using switches that are incorporated in the chassis or with a remote control device 2006 that is provided separately, and a display portion 2007 that displays output information may be provided for the remote control device.
a sub-screen 2008 may be formed using a second display panel and may be used to display channel number, volume, and the like, in addition to the main screen 2003 .
the main screen 2003 may be formed with a liquid crystal display panel
the sub-screen 2008 may be formed with a light-emitting display panel.
the main screen 2003 may be formed with a light-emitting display panel
the sub-screen 2008 may be formed with a light-emitting display panel
the sub-screen 2008 may be configured to be capable of flashing on and off.
FIG. 38 is a block diagram showing a main structure of the television device.
a pixel portion 901 is formed in a display panel 900 .
a signal line driver circuit 922 and a scanning line driver circuit 923 may be mounted on the display panel 900 by a COG method.
a video signal amplifier circuit 925 that amplifies a video signal among signals received by a tuner 924 , a video signal process circuit 926 that converts the signals output from the video signal amplifier circuit 925 into color signals corresponding to their respective colors of red, green, and blue, a control circuit 927 that converts the video signal so that the video signal can match input specification of the driver IC, and the like are provided on an input side of the video signal.
the control circuit 927 outputs signals to both a scanning line side and a signal line side.
a signal divide circuit 928 may be provided on the signal line side and an input digital signal may be divided into m pieces and supplied.
an audio signal is sent to an audio signal amplifier circuit 929 and is supplied to a speaker 933 through an audio signal process circuit 930 .
a control circuit 931 receives control information of a receiving station (reception frequency) or sound volume from an input portion 932 and transmits signals to the tuner 924 and the audio signal process circuit 930 .
the present invention is not limited to a use for television devices, and can be applied to a variety of applications such as monitors of personal computers, or display media that have a large area, such as information display boards in railway stations, airports, and the like, or street-side advertisement display boards.
the display device described in any of the preceding embodiment modes is applied to the main screen 2003 and the sub-screen 2008 , so that mass productivity of the television device can be improved.
FIG. 37B illustrates one mode of a mobile phone 2301 .
the mobile phone 2301 includes a display portion 2302 , an operation portion 2303 , and the like.
the display device described in any of the preceding embodiment modes is applied to the display portion 2302 , so that mass productivity of the mobile phone can be improved.
a portable computer illustrated in FIG. 37C includes a main body 2401 , a display portion 2402 , and the like.
the display device described in any of the preceding embodiment modes is applied to the display portion 2402 , so that mass productivity of the computer can be improved.
FIG. 37D illustrates a desk lamp including a lighting portion 2501 , a lampshade 2502 , an adjustable arm 2503 , a support 2504 , a base 2505 , and a power supply 2506 .
the desk lamp is manufactured with the use of a light-emitting device of the present invention for the lighting portion 2501 .
the lighting equipment includes a ceiling light, a wall light, and the like in its category. Use of the light-emitting device shown in any of the preceding embodiment modes can improve mass productivity and thus can provide inexpensive desk lamps.
a silicon oxynitride film with a thickness of 100 nm was formed over a glass substrate with a thickness of 0.7 mm by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 50 W; the film formation temperature was 280° C.; the flow rates of silane gas and dinitrogen monoxide were 30 sccm and 1200 sccm, respectively; and the pressure was 40 Pa.
gas including phosphine was introduced to a reaction chamber to perform flushing treatment.
the conditions at this time were as follows:
a microcrystalline silicon film with a thickness of 50 nm was formed over the gate insulating film by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 50 W; the film formation temperature was 280° C.; the flow rates of silane gas and hydrogen were 10 sccm and 1500 sccm, respectively; and the pressure was 280 Pa.
the substrate was carried out of the reaction chamber and the inside of the reaction chamber was cleaned with fluorine radicals. Then, the substrate was carried in the reaction chamber again.
an amorphous silicon film was formed as a buffer layer over the microcrystalline silicon film.
the amorphous silicon film was formed with a thickness of 100 nm over the microcrystalline silicon film by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 60 W; the film formation temperature was 280° C.; the flow rates of silane gas and hydrogen were 280 sccm and 300 sccm, respectively; and the pressure was 170 Pa.
SIMS secondary ion mass spectroscopy
a vertical axis represents a concentration (atoms/cm 3 ) of phosphorus and a horizontal axis represents a depth (nm) to which a sample was etched.
the film at depths of up to approximately 70 nm was the amorphous silicon film, which was the buffer layer; the film at depths of approximately 70 to 120 nm was the microcrystalline silicon film; and the film at depths of approximately 120 to 220 nm was the silicon oxynitride film, which was the gate insulating film.
Concentrations of phosphorus in the microcrystalline silicon films in FIG. 39 are presented below.
the concentration of phosphorus at the interface between the microcrystalline silicon film and the silicon oxynitride film is excluded because the ionic strength of silicon is not in a normal condition at the peak of phosphorus concentration at the interface between the microcrystalline silicon film and the silicon oxynitride film.
the microcrystalline silicon film including phosphorus can be formed.
FIG. 40 shows a result of measuring peak concentrations of phosphorus by SIMS.
a silicon oxynitride film was formed as a first gate insulating film so as to include phosphorus, and a silicon oxynitride film was formed as a second gate insulating film.
a silicon oxynitride film including phosphorus with a thickness of 10 nm was formed over a glass substrate with a thickness of 0.7 mm by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 50 W; the film formation temperature was 280° C.; and the pressure was 40 Pa.
the conditions of the flow rates of source gases were as follows:
a microcrystalline silicon film with a thickness of 50 nm was formed over the gate insulating film by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 50 W; the film formation temperature was 280° C.; the flow rates of silane gas and hydrogen were 10 sccm and 1500 sccm, respectively; and the pressure was 280 Pa.
the substrate was carried out of the reaction chamber and the inside of the reaction chamber was cleaned with fluorine radicals. Then, the substrate was carried in the reaction chamber again.
a vertical axis represents a concentration (atoms/cm 3 ) of phosphorus and a horizontal axis represents a depth (nm) to which a sample was etched.
the film at depths of up to approximately 70 nm was the amorphous silicon film, which was the buffer layer; the film at depths of approximately 70 to 120 nm was the microcrystalline silicon film; and the film at depths of approximately 120 to 220 nm was the silicon oxynitride film, which was the gate insulating film.
the concentration of phosphorus in the silicon oxynitride film cannot be measured accurately in FIG. 40 because it was quantified with the use of a silicon standard sample, the peak form makes it possible to estimate whether phosphorus was included or not. There is a large peak of the phosphorus concentration also at depths of 200 to 230 nm, which demonstrates that the gate insulating film, which was not in contact with the microcrystalline silicon film, included phosphorus.
FIG. 41 shows a result of measuring peak concentrations of phosphorus by SIMS.
a silicon nitride film was formed as the first gate insulating film
a silicon oxynitride film was formed as the second gate insulating film.
the inside of the reaction chamber was precoated with the protective film.
the condition at this time was as follows:
An amorphous silicon film including phosphorus with a thickness of 50 nm was formed as the protective film on an inner wall of a reaction chamber under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 370 W; and the pressure was 170 Pa. Further, the conditions of the flow rates of source gases were as follows:
the silicon oxynitride film was formed with a thickness of 110 nm over the silicon nitride film by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 50 W; the film formation temperature was 280° C.; the flow rates of silane gas and dinitrogen monoxide were 30 sccm and 1200 sccm, respectively; and the pressure was 40 Pa.
the amorphous silicon film was formed with a thickness of 200 nm over the silicon oxynitride film by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 120 W; the film formation temperature was 280° C.; the flow rate of silane gas was 300 sccm; and the pressure was 170 Pa.
a microcrystalline silicon film with a thickness of 50 nm was formed over the gate insulating film by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 50 W; the film formation temperature was 280° C.; the flow rates of silane gas and hydrogen were 10 sccm and 1500 sccm, respectively; and the pressure was 280 Pa.
the substrate was carried out of the reaction chamber and the inside of the reaction chamber was cleaned with fluorine radicals. Then, the substrate was carried in the reaction chamber again.
an amorphous silicon film was formed as a buffer layer over the microcrystalline silicon film.
the amorphous silicon film was formed with a thickness of 100 nm over the microcrystalline silicon film by a plasma CVD method under the following condition: the RF power source frequency was 13.56 MHz; the power of the RF power source was 60 W; the film formation temperature was 280° C.; the flow rates of silane gas and hydrogen were 280 sccm and 300 sccm, respectively; and the pressure was 170 Pa.
FIG. 41 shows the measurement results.
a vertical axis represents a concentration (atoms/cm 3 ) of phosphorus and a horizontal axis represents a depth (nm) to which a sample was etched.
the film at depths of up to approximately 70 nm was the amorphous silicon film, which was the buffer layer; the film at depths of approximately 70 to 120 nm was the microcrystalline silicon film; and the film at depths of approximately 120 to 220 nm was the silicon oxynitride film, which was the gate insulating film.
Concentrations of phosphorus in the microcrystalline silicon films in FIG. 41 are presented below.
the concentration of phosphorus at the interface between the microcrystalline silicon film and the silicon oxynitride film is excluded because the ionic strength of silicon is not in a normal condition at the peak of phosphorus concentration at the interface between the microcrystalline silicon film and the silicon oxynitride film.
the microcrystalline silicon film can include phosphorus.
the lifetime of carriers which are included in a microcrystalline silicon film formed over an insulating film was measured.
An influence of the insulating film on the microcrystalline silicon film is described below.
FIG. 42A shows a cross-sectional structure of Sample 1.
a silicon nitride film 122 with a thickness of 110 nm was formed over a glass substrate 121 ; a silicon oxynitride film 123 with a thickness of 110 nm was formed thereover; and a microcrystalline silicon film 124 with a thickness of 95 nm was formed thereover.
FIG. 42B shows a cross-sectional structure of Sample 2.
a silicon nitride film 122 with a thickness of 110 nm was formed over a glass substrate 121 ; a silicon oxynitride film 123 with a thickness of 110 nm was formed thereover; a silicon nitride film 125 with a thickness of 1 nm was formed thereover; and a microcrystalline silicon film 124 with a thickness of 95 nm was formed thereover.
FIG. 42D shows a cross-sectional structure of Sample 4.
a silicon nitride film 122 with a thickness of 110 nm was formed over a glass substrate 121 ; a silicon oxynitride film 123 with a thickness of 110 nm was formed thereover; a silicon nitride film 127 with a thickness of 5 nm was formed thereover; and a microcrystalline silicon film 124 with a thickness of 95 nm was formed thereover.
FIG. 42E shows a cross-sectional structure of Sample 5.
a silicon nitride film 122 with a thickness of 110 nm was formed over a glass substrate 121 , and a microcrystalline silicon film 124 with a thickness of 95 nm was formed thereover.
the lifetime of carriers included in the microcrystalline silicon film was measured by a microwave photoconductivity decay method (a ⁇ -PCD method).
a ⁇ -PCD method the microcrystalline silicon film was irradiated with pulsed laser beams to measure the lifetime of carriers from when an excessive amount of carriers are generated in the microcrystalline silicon film and until when the carriers are recombined and disappear.
Generation of the carriers increases the conductivity of the microcrystalline silicon film, and thus the reflectance of microwaves with which the microcrystalline silicon film is irradiated changes in accordance with the excessive carrier density.
the time of decrease in the reflectance of the microwaves is measured, whereby the lifetime of carriers can be measured.
FIG. 43 demonstrates that in Sample 1, i.e., in a sample in which a base film for the microcrystalline silicon film is a silicon oxynitride film, the peak value is higher and the lifetime is longer than a sample in which a base film is a silicon nitride film; further, the lifetime of carriers is long also in the case where a highly thin silicon nitride film is formed over the silicon oxynitride film.
a thin film transistor utilizing such a stacked-layer structure can have a higher on-current and a lower off-current, and thus can have excellent current-voltage characteristics.
This embodiment presents calculation results of a donor concentration of a microcrystalline semiconductor film including an impurity element which functions as the donor in a thin film transistor, and of electric characteristics of the thin film transistor.
a microcrystalline semiconductor film to which an impurity element is not added is referred to as ⁇ c-Si (i); a microcrystalline semiconductor film to which an impurity element (e.g., phosphorus) which serves as a donor is added is referred to as ⁇ c-Si (n ⁇ ); a buffer layer to which an impurity element is not added is referred to as a-Si (i); an amorphous semiconductor film to which an impurity element (e.g., phosphorus) imparting one conductivity type is added is referred to as a-Si (n ⁇ ); and an amorphous semiconductor film to which a large amount of impurity element (e.g., phosphorus) imparting one conductivity type is added so that the amorphous semiconductor film can have conductivity is referred to as a-Si (n+).
model parameter of ⁇ c-Si was defined so that the maximum filed effect mobility which was determined by the DC characteristics of the inverted-staggered ⁇ c-Si TFT which was calculated with a device simulator may be approximately 10 times as high as the maximum filed effect mobility which was determined by the DC characteristics of the inverted-staggered a-Si TFT which was calculated with a device simulator.
FIG. 44 shows a structure of a device which was used for the simulation.
a gate electrode with a stacked-layer structure of aluminum (Al) and molybdenum (Mo) (with a total thickness of 150 nm) is formed over the insulating substrate.
the work function of molybdenum (Mo) is assumed to be 4.6 eV.
the TFT characteristics do not depend on the material of a lower layer (aluminum (Al) in this case) of the gate electrode. For the above reason, calculation was performed on the assumption that the gate electrode is formed of only molybdenum (Mo) (with a thickness of 150 nm) for sake of simplification of the calculation.
a ⁇ c-Si (n ⁇ ) (with a thickness varied to be 10 nm, 20 nm, and 50 nm; and a donor concentration varied to be 1 ⁇ 10 15 to 5 ⁇ 10 17 atoms/cm 3 ) and a ⁇ c-Si (i) (with a thickness varied to be 90 nm, 80 nm, and 50 nm) are stacked over the gate insulating film.
a first a-Si (i) (with a thickness of 50 nm) is formed on the left and a second a-Si (i) (with a thickness of 50 nm) is formed on the right.
Vg-Id characteristics are presented below based on the result of the device simulation.
a shift in the threshold voltage which is caused by adding an impurity element to a semiconductor layer corresponds to a minus shift in the Id curve in the direction of the Vg axis which is caused by increasing the donor concentration in the Vg-Id characteristics.
FIGS. 45A and 45B , FIGS. 46A and 46B , and FIGS. 47A and 47B which show the above calculation results, apparently show such a tendency.
a larger thickness of the semiconductor layer to which the impurity element is added leads to a further minus shift of the Id curve in the direction of the Vg axis, which is caused by the fact that the total number of donors increases and the number of donor levels increases, whereby the Fermi energy comes to be closer to the conduction band energy Ec; i.e., by the fact that an inversion layer can be formed at lower gate potential.
the drain current Id is a monotone increasing function with respect to the gate voltage Vd in an on state.
the reason is that the number of conduction electrons in the semiconductor layer which are induced at an interface between the semiconductor layer and the gate insulating film increases as the gate voltage Vg increases. Therefore, when an increase in the donor concentration shifts the Id curve toward the minus side in the direction of the Vg axis, the on-current (the drain current when the gate voltage Vg is 20 V) increases.
FIGS. 48A and 48B which show the above calculation results, apparently show such a tendency.
the microcrystalline semiconductor film substantially does not include a donor, i.e., an impurity element which serves as a donor.
FIGS. 48A and 48B demonstrate that the donor in the microcrystalline semiconductor film increases the on-current.
FIGS. 50A and 50B which show the above calculation results, apparently show such a tendency. Further, the subthreshold swing also increases by increasing the thickness of the semiconductor layer to which the impurity element is added. A probable cause of this is that the total number of impurity element increases and the number of donor levels increases, whereby the conduction electrons are more likely to be diffused.
the portion of the first semiconductor layer 206 which is inverted means a portion of the first semiconductor layer 206 in a state where conduction electrons are induced at the interface between the first semiconductor layer 206 and the gate insulating film 204 by applying potential to the gate electrode 202 . It can be considered that the resistance Rs is much smaller than the resistance Rd or the resistance Rc(on).
the resistance Rd is formed in the second semiconductor layer 208 with a thickness of approximately 200 nm.
the resistance Rc(on) is formed in the first semiconductor layer 206 with a length of approximately 6 ⁇ m. Therefore, when the resistance value per unit length of the portion of the second semiconductor layer 208 which is depleted is approximately 30 times or more as high as that of the portion of the first semiconductor layer 206 which is inverted, it is probable that the resistance Rd will have the greatest influence on the drain current.
the resistance value per unit length of the portion of the second semiconductor layer 208 which is depleted is approximately 30 times or less as high as that of the portion of the first semiconductor layer 206 which is inverted, it is probable that the resistance Rc(on) will have the greatest influence on the drain current.
the resistance Rc(on) decreases from a value which is much higher than the resistance Rd to a value which is as high as or almost as high as the resistance Rd, and further to a value which is much lower than the resistance Rd as the gate voltage increases. Further, it is probable that the drain current increases suddenly as the resistance Rc(on) decreases from a value much higher than the resistance Rd to a value which is as high as or almost as high as the resistance Rd. On the other hand, when the resistance Rc(on) comes to have a value which is much lower than the resistance Rd, a decrease in the resistance Rc(on) has less influence on the drain current. Further, it is probable that the resistance Rd decreases as the drain voltage increases.
FIGS. 51A and 51B show the calculation results of the above.
the semiconductor layer to which the impurity element is added has a large thickness, for example, in the result of ⁇ c-Si (n ⁇ ) with a thickness of 50 nm in FIG. 51A , the maximum filed effect mobility increases as the donor concentration increases.
a region of the semiconductor layer which contributes to conduction increases.
the field effect mobility increases. It is probable that a cause of the result of ⁇ c-Si (n ⁇ ) with a thickness of 50 nm in FIG. 51A is that improvement in the field effect mobility which is due to an increase in the thickness of the semiconductor layer counteracts a decrease in the field effect mobility which is due to diffusion of the impurity element.
the microcrystalline semiconductor film can be regarded as not including a donor substantially, i.e., not including the impurity element which serves as a donor substantially.
FIGS. 51A and 51B demonstrate that the maximum filed effect mobility increases when the microcrystalline semiconductor film includes the donor.
the frame frequency can be increased in operating a liquid crystal display device.
characteristics of a thin film transistor which can be manufactured in a pixel portion of a liquid crystal display device in which display characteristics of moving images are improved and which is capable of smooth display by quadrupling the frame frequency (e.g., 480 Hz or 400 Hz) and interpolating image data, and the concentration of the impurity element which serves as a donor which is included in a channel formation region and contributes to achieving the characteristics were calculated.
FIG. 54 is a circuit diagram which is used for the circuit simulation.
a pixel TFT 228 is used in which there occurs maximum signal delay because of parasitic capacitance and wiring resistance of a video signal line 224 and a gate signal line 226 .
Cg, Rg, Cs, and Rs represent parasitic capacitance of the video signal line 224 , wiring resistance of the video signal line 224 , parasitic capacitance of the gate signal line 226 , and wiring resistance of the gate signal line 226 , respectively.
the circuit simulation was carried out using a double- ⁇ circuit.
a curve shows a threshold value which is obtained when the thickness of the microcrystalline silicon film including the impurity element which serves as a donor is set to be from 10 to 50 nm and the donor concentration is set to be from 1 ⁇ 10 15 to 5 ⁇ 10 17 atoms/cm 3 in the thin film transistors of the models used in Embodiment 5.
the threshold value is from ⁇ 3 to 1 V inclusive according to the above requisites of the TFT characteristics; thus, when the thickness of the microcrystalline silicon film including the impurity element which serves as a donor is from 10 to 50 nm, the donor concentration which satisfies the above range is from 6 ⁇ 10 15 to 5 ⁇ 10 17 atoms/cm 3 .
the donor concentration is shown here, which is different from the concentration of the impurity element which serves as a donor in that the donor concentration depends on the activation rate of the impurity element which serves as a donor.
a liquid crystal display device capable of quadruple frame rate display can be manufactured.

Landscapes

Thin Film Transistor (AREA)
Liquid Crystal (AREA)
Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Dram (AREA)
Engineering & Computer Science (AREA)
Power Engineering (AREA)
Chemical & Material Sciences (AREA)
Crystallography & Structural Chemistry (AREA)

US12/238,517 2007-10-05 2008-09-26 Thin film transistor, display device having thin film transistor, and method for manufacturing the same Abandoned US20090090915A1 (en)

Priority Applications (1)

Application Number	Priority Date	Filing Date	Title
US13/845,443 US8945962B2 (en)	2007-10-05	2013-03-18	Thin film transistor, display device having thin film transistor, and method for manufacturing the same

Applications Claiming Priority (4)

Application Number	Priority Date	Filing Date	Title
JP2007262739		2007-10-05
JP2007-262739		2007-10-05
JP2007-267085		2007-10-12
JP2007267085		2007-10-12

Related Child Applications (1)

Application Number	Title	Priority Date	Filing Date
US13/845,443 Continuation US8945962B2 (en)	2007-10-05	2013-03-18	Thin film transistor, display device having thin film transistor, and method for manufacturing the same

Publications (1)

Publication Number	Publication Date
US20090090915A1 true US20090090915A1 (en)	2009-04-09

Family

ID=40522487

Family Applications (2)

Application Number	Title	Priority Date	Filing Date
US12/238,517 Abandoned US20090090915A1 (en)	2007-10-05	2008-09-26	Thin film transistor, display device having thin film transistor, and method for manufacturing the same
US13/845,443 Expired - Fee Related US8945962B2 (en)	2007-10-05	2013-03-18	Thin film transistor, display device having thin film transistor, and method for manufacturing the same

Family Applications After (1)

Application Number	Title	Priority Date	Filing Date
US13/845,443 Expired - Fee Related US8945962B2 (en)	2007-10-05	2013-03-18	Thin film transistor, display device having thin film transistor, and method for manufacturing the same

Country Status (5)

Country	Link
US (2)	US20090090915A1 (zh)
JP (1)	JP5497279B2 (zh)
KR (2)	KR101551294B1 (zh)
CN (1)	CN101404294B (zh)
TW (2)	TWI470805B (zh)

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US20090101916A1 (en) *	2007-10-23	2009-04-23	Semiconductor Energy Laboratory Co., Ltd.	Microcrystalline semiconductor film, thin film transistor, and display device including thin film transistor
US20090114921A1 (en) *	2007-11-01	2009-05-07	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, and display device having the thin film transistor
US20090140256A1 (en) *	2007-12-03	2009-06-04	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor and semiconductor device
US20100213459A1 (en) *	2007-09-28	2010-08-26	Canon Kabushiki Kaisha	Thin film transistor, manufacturing method therefor, and display apparatus using the same
US20100301328A1 (en) *	2009-05-29	2010-12-02	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20110062435A1 (en) *	2009-09-16	2011-03-17	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20110101335A1 (en) *	2009-10-30	2011-05-05	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20120298997A1 (en) *	2011-05-24	2012-11-29	Sharp Kabushiki Kaisha	Semiconductor device
US8735897B2 (en)	2010-03-15	2014-05-27	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device
US20150008434A1 (en) *	2013-07-03	2015-01-08	Samsung Display Co., Ltd.	Thin film transistor array panel and method of manufacturing the same
US20150123112A1 (en) *	2013-11-07	2015-05-07	Samsung Display Co., Ltd.	Thin film transistor substrate, display apparatus having the same, and manufacturing method thereof
US9130041B2 (en)	2009-09-04	2015-09-08	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20160079435A1 (en) *	2009-02-20	2016-03-17	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US9720277B2 (en)	2010-08-06	2017-08-01	Semiconductor Energy Laboratory Co., Ltd.	Liquid crystal display device having optical sensor
US9911856B2 (en) *	2009-10-09	2018-03-06	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device
US20190123064A1 (en) *	2017-10-19	2019-04-25	Samsung Display Co., Ltd.	Transistor display panel
US10804075B2 (en) *	2013-07-18	2020-10-13	Varian Semiconductor Equipment Associates, Inc.	Method of improving ion beam quality in an implant system
US10943547B2 (en)	2010-07-02	2021-03-09	Semiconductor Energy Laboratory Co., Ltd.	Liquid crystal display device
CN113111498A (zh) *	2021-03-26	2021-07-13	中山大学	一种偏栅晶体管进行建模的方法及电路仿真方法
US11374026B2 (en) *	2019-12-25	2022-06-28	Tcl China Star Optoelectronics Technology Co., Ltd.	TFT array substrate and manufacturing method thereof
US11710715B2 (en)	2020-06-09	2023-07-25	Samsung Electronics Co., Ltd.	Semiconductor package
US11710795B2 (en)	2009-11-28	2023-07-25	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device comprising oxide semiconductor with c-axis-aligned crystals

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
KR101084233B1 (ko)	2009-10-13	2011-11-16	삼성모바일디스플레이주식회사	박막트랜지스터 및 그 제조 방법
US8598586B2 (en) *	2009-12-21	2013-12-03	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor and manufacturing method thereof
KR101836067B1 (ko) *	2009-12-21	2018-03-08	가부시키가이샤 한도오따이 에네루기 켄큐쇼	박막 트랜지스터와 그 제작 방법
KR101588355B1 (ko)	2009-12-23	2016-02-15	삼성디스플레이 주식회사	터치스크린 기판, 이의 제조 방법 및 표시 패널
US8476744B2 (en) *	2009-12-28	2013-07-02	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor with channel including microcrystalline and amorphous semiconductor regions
JP5961391B2 (ja) *	2011-01-26	2016-08-02	株式会社半導体エネルギー研究所	半導体装置の作製方法
CN102629555B (zh) *	2011-10-11	2014-11-26	北京京东方光电科技有限公司	栅极绝缘层、tft、阵列基板、显示装置以及制备方法
CN102646676B (zh) *	2011-11-03	2015-06-10	京东方科技集团股份有限公司	一种tft阵列基板
US9236243B2 (en)	2014-01-09	2016-01-12	Stmicroelectronics Pte Ltd	Method for making semiconductor devices including reactant treatment of residual surface portion
CN105093816B (zh) *	2015-09-23	2019-08-02	武汉华星光电技术有限公司	一种显示面板的信号线的制程方法及显示面板
KR102477608B1 (ko)	2017-12-12	2022-12-14	삼성디스플레이 주식회사	표시 기판, 표시 기판의 제조 방법 및 표시 기판을 포함하는 표시 장치
JP2020004861A (ja) *	2018-06-28	2020-01-09	堺ディスプレイプロダクト株式会社	薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法
JP2020086346A (ja) *	2018-11-30	2020-06-04	セイコーエプソン株式会社	導光装置及び虚像表示装置
CN109659235B (zh) *	2018-12-14	2021-12-03	武汉华星光电半导体显示技术有限公司	Tft的制备方法、tft、阵列基板及显示装置
CN109671623B (zh) *	2018-12-21	2020-11-24	深圳市华星光电技术有限公司	栅极与薄膜晶体管的制造方法
TWI894815B (zh) *	2023-03-20	2025-08-21	元太科技工業股份有限公司	半導體結構

Citations (14)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4409134A (en) *	1980-03-03	1983-10-11	Shunpei Yamazaki	Photoelectric conversion semiconductor and manufacturing method thereof
US5453858A (en) *	1990-12-25	1995-09-26	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device constructed with thin film transistors
US5591987A (en) *	1980-03-03	1997-01-07	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor MIS field effect transistor with semi-amorphous semiconductor material
US5648662A (en) *	1991-06-19	1997-07-15	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device with amorphous and crystalline shift registers
US5766989A (en) *	1994-12-27	1998-06-16	Matsushita Electric Industrial Co., Ltd.	Method for forming polycrystalline thin film and method for fabricating thin-film transistor
US5825050A (en) *	1995-05-25	1998-10-20	Nec Corporation	Thin film transistor having tapered active layer formed by controlling defect density and process of fabrication thereof
US20040207023A1 (en) *	2003-01-21	2004-10-21	Kabushiki Kaisha Toshiba	Complementary field effect transistor and its manufacturing method
US20050012097A1 (en) *	2003-07-14	2005-01-20	Semiconductor Energy Laboratory Co., Ltd.	Light-emitting device
US20060091394A1 (en) *	2004-10-28	2006-05-04	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20070035676A1 (en) *	2005-08-12	2007-02-15	Semiconductor Energy Laboratory Co., Ltd.	Liquid crystal display device and method for manufacturing the same
US20070090351A1 (en) *	2005-10-22	2007-04-26	Samsung Sdi Co., Ltd.	Organic thin film transistor and flat panel display device having the same
US20080188050A1 (en) *	2003-07-23	2008-08-07	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20090200551A1 (en) *	2008-02-11	2009-08-13	Tae Kyung Won	Microcrystalline silicon thin film transistor
US7824952B2 (en) *	2006-03-22	2010-11-02	Samsung Electronics Co., Ltd.	Display apparatus and method of manufacturing thereof

Family Cites Families (62)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS6098680A (ja)	1983-11-04	1985-06-01	Seiko Instr & Electronics Ltd	電界効果型薄膜トランジスタ
JPS60160170A (ja)	1984-01-31	1985-08-21	Seiko Instr & Electronics Ltd	薄膜トランジスタ
JPS6187371A (ja)	1984-10-05	1986-05-02	Hitachi Ltd	薄膜半導体装置
JPS6267872A (ja)	1985-09-20	1987-03-27	Toshiba Corp	非晶質シリコン薄膜トランジスタ
JPS63258072A (ja) *	1987-04-15	1988-10-25	Nec Corp	電界効果トランジスタ
US5256509A (en)	1989-11-20	1993-10-26	Semiconductor Energy Laboratory Co., Ltd.	Image-forming member for electrophotography and manufacturing method for the same
JP2934874B2 (ja) *	1990-05-21	1999-08-16	カシオ計算機株式会社	薄膜トランジスタの製造方法
EP0473988A1 (en)	1990-08-29	1992-03-11	International Business Machines Corporation	Method of fabricating a thin film transistor having amorphous/polycrystalline semiconductor channel region
US7115902B1 (en)	1990-11-20	2006-10-03	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device and method for manufacturing the same
JP2791422B2 (ja)	1990-12-25	1998-08-27	株式会社半導体エネルギー研究所	電気光学装置およびその作製方法
US7576360B2 (en)	1990-12-25	2009-08-18	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device which comprises thin film transistors and method for manufacturing the same
US7098479B1 (en)	1990-12-25	2006-08-29	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device and method for manufacturing the same
KR970002267B1 (en) *	1991-09-30	1997-02-27	Semiconductor Energy Lab Kk	Semiconductor integrated circuit device fabrication process
US5495121A (en)	1991-09-30	1996-02-27	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device
EP0535979A3 (en)	1991-10-02	1993-07-21	Sharp Kabushiki Kaisha	A thin film transistor and a method for producing the same
JPH05226656A (ja) *	1992-02-13	1993-09-03	Hitachi Ltd	薄膜半導体装置及びその製造方法
US6709907B1 (en)	1992-02-25	2004-03-23	Semiconductor Energy Laboratory Co., Ltd.	Method of fabricating a thin film transistor
JP2924441B2 (ja)	1992-04-27	1999-07-26	日本電気株式会社	薄膜トランジスタ及びその製造方法
US6078059A (en)	1992-07-10	2000-06-20	Sharp Kabushiki Kaisha	Fabrication of a thin film transistor and production of a liquid display apparatus
JP3429034B2 (ja) *	1992-10-07	2003-07-22	シャープ株式会社	半導体膜の製造方法
KR0130955B1 (ko)	1992-10-07	1998-04-14	쓰지 하루오	박막 트랜지스터의 제조방법 및 액정표시장치의 제조방법
JPH06326312A (ja)	1993-05-14	1994-11-25	Toshiba Corp	アクティブマトリクス型表示装置
JP2833545B2 (ja) *	1995-03-06	1998-12-09	日本電気株式会社	半導体装置の製造方法
JPH10261801A (ja) *	1997-03-19	1998-09-29	Toshiba Electron Eng Corp	薄膜トランジスタ装置及び薄膜トランジスタ装置の製造方法
KR100257158B1 (ko)	1997-06-30	2000-05-15	김영환	박막 트랜지스터 및 그의 제조 방법
US6197624B1 (en)	1997-08-29	2001-03-06	Semiconductor Energy Laboratory Co., Ltd.	Method of adjusting the threshold voltage in an SOI CMOS
JPH11177094A (ja) *	1997-12-08	1999-07-02	Advanced Display Inc	半導体薄膜トランジスタおよび該半導体薄膜トランジスタを含む半導体薄膜トランジスタアレイ基板
JP4293385B2 (ja)	1998-01-27	2009-07-08	株式会社半導体エネルギー研究所	光電変換装置の作製方法
JP2001007024A (ja)	1999-06-18	2001-01-12	Sanyo Electric Co Ltd	多結晶シリコン膜の形成方法
JP2001077366A (ja)	1999-08-20	2001-03-23	Internatl Business Mach Corp <Ibm>	薄膜トランジスタ、液晶表示装置、及び薄膜トランジスタの製造方法
JP3538088B2 (ja)	1999-10-25	2004-06-14	Ｎｅｃ液晶テクノロジー株式会社	薄膜トランジスタおよびその製造方法
JP2001217424A (ja)	2000-02-03	2001-08-10	Matsushita Electric Ind Co Ltd	薄膜トランジスタおよびそれを用いた液晶表示装置
JP4118485B2 (ja)	2000-03-13	2008-07-16	株式会社半導体エネルギー研究所	半導体装置の作製方法
JP2002246605A (ja)	2001-02-20	2002-08-30	Matsushita Electric Ind Co Ltd	液晶表示用薄膜トランジスタの製造方法
KR100796795B1 (ko) *	2001-10-22	2008-01-22	삼성전자주식회사	반도체 소자의 접촉부 및 그 제조 방법과 이를 포함하는표시 장치용 박막 트랜지스터 어레이 기판 및 그 제조 방법
EP1367659B1 (en)	2002-05-21	2012-09-05	Semiconductor Energy Laboratory Co., Ltd.	Organic field effect transistor
TW577176B (en)	2003-03-31	2004-02-21	Ind Tech Res Inst	Structure of thin-film transistor, and the manufacturing method thereof
JP4748954B2 (ja) *	2003-07-14	2011-08-17	株式会社半導体エネルギー研究所	液晶表示装置
US7314785B2 (en)	2003-10-24	2008-01-01	Semiconductor Energy Laboratory Co., Ltd.	Display device and manufacturing method thereof
JP2005167051A (ja) *	2003-12-04	2005-06-23	Sony Corp	薄膜トランジスタおよび薄膜トランジスタの製造方法
US7205171B2 (en)	2004-02-11	2007-04-17	Au Optronics Corporation	Thin film transistor and manufacturing method thereof including a lightly doped channel
US7642038B2 (en) *	2004-03-24	2010-01-05	Semiconductor Energy Laboratory Co., Ltd.	Method for forming pattern, thin film transistor, display device, method for manufacturing thereof, and television apparatus
JP2005322845A (ja) *	2004-05-11	2005-11-17	Sekisui Chem Co Ltd	半導体デバイスと、その製造装置、および製造方法
KR101009677B1 (ko) *	2004-05-24	2011-01-19	엘지디스플레이 주식회사	액정표시장치 및 이의 제조방법
JP4397753B2 (ja) *	2004-07-28	2010-01-13	株式会社半導体エネルギー研究所	半導体装置
JP4628040B2 (ja)	2004-08-20	2011-02-09	株式会社半導体エネルギー研究所	半導体素子を備えた表示装置の製造方法
JP4882322B2 (ja) *	2004-09-17	2012-02-22	日本電気株式会社	半導体装置、回路、これらを用いた表示装置、及びこれらの駆動方法
KR100645718B1 (ko)	2005-04-28	2006-11-14	삼성에스디아이 주식회사	박막 트랜지스터 및 그 제조방법
JP4577114B2 (ja)	2005-06-23	2010-11-10	ソニー株式会社	薄膜トランジスタの製造方法および表示装置の製造方法
JP2007035964A (ja)	2005-07-27	2007-02-08	Sony Corp	薄膜トランジスタとその製造方法、及び表示装置
CN100529866C (zh) *	2006-04-19	2009-08-19	群康科技(深圳)有限公司	液晶显示器制造方法
KR101266273B1 (ko) *	2006-06-30	2013-05-22	엘지디스플레이 주식회사	액정표시소자의 제조방법
JP2007049171A (ja)	2006-08-30	2007-02-22	Chi Mei Electronics Corp	微結晶薄膜トランジスタを用いた画像表示装置
KR20080056493A (ko) *	2006-12-18	2008-06-23	삼성전자주식회사	박막 트랜지스터 기판 및 이의 제조 방법
JP5331389B2 (ja)	2007-06-15	2013-10-30	株式会社半導体エネルギー研究所	表示装置の作製方法
JP2009049384A (ja)	2007-07-20	2009-03-05	Semiconductor Energy Lab Co Ltd	発光装置
US7633089B2 (en)	2007-07-26	2009-12-15	Semiconductor Energy Laboratory Co., Ltd.	Liquid crystal display device and electronic device provided with the same
KR101446251B1 (ko)	2007-08-07	2014-10-01	가부시키가이샤 한도오따이 에네루기 켄큐쇼	표시 장치, 이 표시 장치를 구비한 전자기기 및 그 제조 방법
JP5395382B2 (ja)	2007-08-07	2014-01-22	株式会社半導体エネルギー研究所	トランジスタの作製方法
US9054206B2 (en)	2007-08-17	2015-06-09	Semiconductor Energy Laboratory Co., Ltd.	Method for manufacturing semiconductor device
US7611930B2 (en)	2007-08-17	2009-11-03	Semiconductor Energy Laboratory Co., Ltd.	Method of manufacturing display device
JP2009071289A (ja)	2007-08-17	2009-04-02	Semiconductor Energy Lab Co Ltd	半導体装置およびその作製方法

2008
- 2008-09-26 US US12/238,517 patent/US20090090915A1/en not_active Abandoned
- 2008-09-28 CN CN200810168087.8A patent/CN101404294B/zh not_active Expired - Fee Related
- 2008-09-30 KR KR1020080096096A patent/KR101551294B1/ko not_active Expired - Fee Related
- 2008-10-02 TW TW97137937A patent/TWI470805B/zh not_active IP Right Cessation
- 2008-10-02 TW TW103137795A patent/TWI557922B/zh not_active IP Right Cessation
- 2008-10-02 JP JP2008257708A patent/JP5497279B2/ja not_active Expired - Fee Related
2013
- 2013-03-18 US US13/845,443 patent/US8945962B2/en not_active Expired - Fee Related
2014
- 2014-12-01 KR KR1020140170040A patent/KR101564006B1/ko not_active Expired - Fee Related

Patent Citations (25)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5591987A (en) *	1980-03-03	1997-01-07	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor MIS field effect transistor with semi-amorphous semiconductor material
US4409134A (en) *	1980-03-03	1983-10-11	Shunpei Yamazaki	Photoelectric conversion semiconductor and manufacturing method thereof
US6306213B1 (en) *	1990-11-20	2001-10-23	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device and method for manufacturing the same
US6252249B1 (en) *	1990-11-20	2001-06-26	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device having crystalline silicon clusters
US5849601A (en) *	1990-12-25	1998-12-15	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device and method for manufacturing the same
US5453858A (en) *	1990-12-25	1995-09-26	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device constructed with thin film transistors
US5701167A (en) *	1990-12-25	1997-12-23	Semiconductor Energy Laboratory Co., Ltd.	LCD having a peripheral circuit with TFTs having the same structure as TFTs in the display region
US6023075A (en) *	1990-12-25	2000-02-08	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device and method for manufacturing the same
US5811328A (en) *	1991-06-19	1998-09-22	Semiconductor Energy Laboratory Co, Ltd.	Electro-optical device and thin film transistor and method forming the same
US6847064B2 (en) *	1991-06-19	2005-01-25	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device having a thin film transistor
US6124155A (en) *	1991-06-19	2000-09-26	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device and thin film transistor and method for forming the same
US6166399A (en) *	1991-06-19	2000-12-26	Semiconductor Energy Laboratory Co., Ltd.	Active matrix device including thin film transistors
US5648662A (en) *	1991-06-19	1997-07-15	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device with amorphous and crystalline shift registers
US6335213B1 (en) *	1991-06-19	2002-01-01	Semiconductor Energy Laboratory Co., Ltd.	Electro-optical device and thin film transistor and method for forming the same
US6756258B2 (en) *	1991-06-19	2004-06-29	Semiconductor Energy Laboratory Co., Ltd.	Method of manufacturing a semiconductor device
US5766989A (en) *	1994-12-27	1998-06-16	Matsushita Electric Industrial Co., Ltd.	Method for forming polycrystalline thin film and method for fabricating thin-film transistor
US5825050A (en) *	1995-05-25	1998-10-20	Nec Corporation	Thin film transistor having tapered active layer formed by controlling defect density and process of fabrication thereof
US20040207023A1 (en) *	2003-01-21	2004-10-21	Kabushiki Kaisha Toshiba	Complementary field effect transistor and its manufacturing method
US20050012097A1 (en) *	2003-07-14	2005-01-20	Semiconductor Energy Laboratory Co., Ltd.	Light-emitting device
US20080188050A1 (en) *	2003-07-23	2008-08-07	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20060091394A1 (en) *	2004-10-28	2006-05-04	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20070035676A1 (en) *	2005-08-12	2007-02-15	Semiconductor Energy Laboratory Co., Ltd.	Liquid crystal display device and method for manufacturing the same
US20070090351A1 (en) *	2005-10-22	2007-04-26	Samsung Sdi Co., Ltd.	Organic thin film transistor and flat panel display device having the same
US7824952B2 (en) *	2006-03-22	2010-11-02	Samsung Electronics Co., Ltd.	Display apparatus and method of manufacturing thereof
US20090200551A1 (en) *	2008-02-11	2009-08-13	Tae Kyung Won	Microcrystalline silicon thin film transistor

Cited By (47)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US20100213459A1 (en) *	2007-09-28	2010-08-26	Canon Kabushiki Kaisha	Thin film transistor, manufacturing method therefor, and display apparatus using the same
US8563977B2 (en) *	2007-09-28	2013-10-22	Canon Kabushiki Kaisha	Thin film transistor having a two-layer semiconductor with columnar structures, manufacturing method therefor, and display apparatus using the same
US8106398B2 (en)	2007-10-23	2012-01-31	Semiconductor Energy Laboratory Co., Ltd.	Microcrystalline semiconductor film, thin film transistor, and display device including thin film transistor
US20090101916A1 (en) *	2007-10-23	2009-04-23	Semiconductor Energy Laboratory Co., Ltd.	Microcrystalline semiconductor film, thin film transistor, and display device including thin film transistor
US20090114921A1 (en) *	2007-11-01	2009-05-07	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, and display device having the thin film transistor
US8304779B2 (en)	2007-11-01	2012-11-06	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, and display device having the thin film transistor
US20090140256A1 (en) *	2007-12-03	2009-06-04	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor and semiconductor device
US7923730B2 (en) *	2007-12-03	2011-04-12	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor and semiconductor device
US8063403B2 (en)	2007-12-03	2011-11-22	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor and semiconductor device
US11824062B2 (en)	2009-02-20	2023-11-21	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US9859306B2 (en)	2009-02-20	2018-01-02	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US12136629B2 (en)	2009-02-20	2024-11-05	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US11011549B2 (en) *	2009-02-20	2021-05-18	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US10096623B2 (en)	2009-02-20	2018-10-09	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US9443981B2 (en) *	2009-02-20	2016-09-13	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US20160079435A1 (en) *	2009-02-20	2016-03-17	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US10586811B2 (en)	2009-02-20	2020-03-10	Semiconductor Energy Laboratory Co., Ltd.	Thin film transistor, method for manufacturing the same, and semiconductor device
US8872171B2 (en)	2009-05-29	2014-10-28	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US9947797B2 (en)	2009-05-29	2018-04-17	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20100301328A1 (en) *	2009-05-29	2010-12-02	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US9537012B2 (en)	2009-09-04	2017-01-03	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device with oxide semiconductor layer
US9130041B2 (en)	2009-09-04	2015-09-08	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US20110062435A1 (en) *	2009-09-16	2011-03-17	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US9911856B2 (en) *	2009-10-09	2018-03-06	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device
US20110101335A1 (en) *	2009-10-30	2011-05-05	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device and method for manufacturing the same
US10566459B2 (en)	2009-10-30	2020-02-18	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device having a first region comprising silicon, oxygen and at least one metal element formed between an oxide semiconductor layer and an insulating layer
US12080802B2 (en)	2009-11-28	2024-09-03	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device comprising silicon and oxide semiconductor in channel formation region
US11710795B2 (en)	2009-11-28	2023-07-25	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device comprising oxide semiconductor with c-axis-aligned crystals
US8735897B2 (en)	2010-03-15	2014-05-27	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device
US11289031B2 (en)	2010-07-02	2022-03-29	Semiconductor Energy Laboratory Co., Ltd.	Liquid crystal display device
US10943547B2 (en)	2010-07-02	2021-03-09	Semiconductor Energy Laboratory Co., Ltd.	Liquid crystal display device
US9720277B2 (en)	2010-08-06	2017-08-01	Semiconductor Energy Laboratory Co., Ltd.	Liquid crystal display device having optical sensor
US9525023B2 (en) *	2011-05-24	2016-12-20	Semiconductor Energy Laboratory Co., Ltd.	Semiconductor device
US20120298997A1 (en) *	2011-05-24	2012-11-29	Sharp Kabushiki Kaisha	Semiconductor device
US9252158B2 (en) *	2013-07-03	2016-02-02	Samsung Display Co., Ltd.	Thin film transistor array panel and method of manufacturing the same
US20150008434A1 (en) *	2013-07-03	2015-01-08	Samsung Display Co., Ltd.	Thin film transistor array panel and method of manufacturing the same
US10825653B2 (en)	2013-07-18	2020-11-03	Varian Semiconductor Equipment Associates, Inc.	Method of improving ion beam quality in an implant system
US10804075B2 (en) *	2013-07-18	2020-10-13	Varian Semiconductor Equipment Associates, Inc.	Method of improving ion beam quality in an implant system
US20150123112A1 (en) *	2013-11-07	2015-05-07	Samsung Display Co., Ltd.	Thin film transistor substrate, display apparatus having the same, and manufacturing method thereof
US9472577B2 (en) *	2013-11-07	2016-10-18	Samsung Display Co., Ltd.	Thin film transistor substrate, display apparatus having the same, and manufacturing method thereof
US10515985B2 (en) *	2017-10-19	2019-12-24	Samsung Display Co., Ltd.	Transistor display panel including transistor having auxiliary layer overlapping edge of gate electrode
US11552108B2 (en)	2017-10-19	2023-01-10	Samsung Display Co., Ltd.	Transistor display panel having an auxiliary layer overlapping portions of source and gate electrodes
US20190123064A1 (en) *	2017-10-19	2019-04-25	Samsung Display Co., Ltd.	Transistor display panel
US10872909B2 (en)	2017-10-19	2020-12-22	Samsung Display Co., Ltd.	Transistor display panel having an auxiliary layer overlapping portions of source and gate electrodes
US11374026B2 (en) *	2019-12-25	2022-06-28	Tcl China Star Optoelectronics Technology Co., Ltd.	TFT array substrate and manufacturing method thereof
US11710715B2 (en)	2020-06-09	2023-07-25	Samsung Electronics Co., Ltd.	Semiconductor package
CN113111498A (zh) *	2021-03-26	2021-07-13	中山大学	一种偏栅晶体管进行建模的方法及电路仿真方法

Also Published As

Publication number	Publication date
CN101404294B (zh)	2013-11-06
KR20090035431A (ko)	2009-04-09
TWI557922B (zh)	2016-11-11
US20130217191A1 (en)	2013-08-22
TWI470805B (zh)	2015-01-21
JP5497279B2 (ja)	2014-05-21
KR101551294B1 (ko)	2015-09-08
US8945962B2 (en)	2015-02-03
TW201507167A (zh)	2015-02-16
TW200933893A (en)	2009-08-01
JP2009111365A (ja)	2009-05-21
KR101564006B1 (ko)	2015-10-27
CN101404294A (zh)	2009-04-08
KR20140147071A (ko)	2014-12-29

Publication	Publication Date	Title
US8945962B2 (en)	2015-02-03	Thin film transistor, display device having thin film transistor, and method for manufacturing the same
US7989332B2 (en)	2011-08-02	Thin film transistor, display device having thin film transistor, and method for manufacturing the same
US8304779B2 (en)	2012-11-06	Thin film transistor, and display device having the thin film transistor
US8030147B2 (en)	2011-10-04	Method for manufacturing thin film transistor and display device including the thin film transistor
US8030655B2 (en)	2011-10-04	Thin film transistor, display device having thin film transistor
US7786482B2 (en)	2010-08-31	Diode and display device including diode
US8558236B2 (en)	2013-10-15	Semiconductor device
US8187956B2 (en)	2012-05-29	Method for manufacturing microcrystalline semiconductor film, thin film transistor having microcrystalline semiconductor film, and photoelectric conversion device having microcrystalline semiconductor film
US8106398B2 (en)	2012-01-31	Microcrystalline semiconductor film, thin film transistor, and display device including thin film transistor
US20090140251A1 (en)	2009-06-04	Thin film transistor, display device including thin film transistor, and method for manufacturing the same
JP5314870B2 (ja)	2013-10-16	薄膜トランジスタの作製方法
JP2026015452A (ja)	2026-01-29	表示装置

Legal Events

Date	Code	Title	Description
2008-09-26	AS	Assignment	Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAZAKI, SHUNPEI;KUROKAWA, YOSHIYUKI;JINBO, YASUHIRO;AND OTHERS;REEL/FRAME:021589/0837;SIGNING DATES FROM 20080916 TO 20080918
2013-06-28	STCB	Information on status: application discontinuation	Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

Date

Code

Title

Description