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US20080070483A1 - Method For Polishing A Semiconductor Wafer And Polished Semiconductor Wafer Producible According To The Method - Google Patents

Method For Polishing A Semiconductor Wafer And Polished Semiconductor Wafer Producible According To The Method Download PDF

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Publication number
US20080070483A1
US20080070483A1 US11/853,103 US85310307A US2008070483A1 US 20080070483 A1 US20080070483 A1 US 20080070483A1 US 85310307 A US85310307 A US 85310307A US 2008070483 A1 US2008070483 A1 US 2008070483A1
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United States
Prior art keywords
polishing
semiconductor wafer
polishing step
polished
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Abandoned
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US11/853,103
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English (en)
Inventor
Klaus Roettger
Vladimir Dutschke
Leszek Mistur
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Siltronic AG
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Siltronic AG
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Publication date
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Assigned to SILTRONIC AG reassignment SILTRONIC AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DUTSCHKE, VLADIMIR, MISTUR, LESZEK, ROETTGER, KLAUS
Publication of US20080070483A1 publication Critical patent/US20080070483A1/en
Abandoned legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • H10P52/00—
    • H10P90/129—

Definitions

  • the invention relates to a method for polishing a semiconductor wafer, in particular a silicon semiconductor wafer, which is intended to provide a semiconductor wafer having an improved planarity, especially in the edge region, which has not yet been achievable.
  • the invention relates specifically to a method for polishing a semiconductor wafer between an upper polishing plate and a lower polishing plate, the semiconductor wafer being polished on both sides while lying in a recess of a carrier by supplying a polishing agent, and to a semiconductor wafer, in particular a silicon semiconductor wafer, having an improved planarity expressed in the form of the SFQR value and the SBIR value.
  • the planarity of the semiconductor wafer is a central quality parameter for assessing the basic suitability of the semiconductor wafer as a substrate for producing electronic components of the most modern generation.
  • An ideally plane semiconductor wafer having entirely plane side surfaces lying mutually parallel would cause no focusing difficulties for the stepper during the lithography for producing components. Attempts are therefore made to approximate this ideal shape as far as possible.
  • a semiconductor wafer cut from the crystal is subjected to a series of processing steps, and in particular the mechanical processing implemented at the start of the process serves to shape the side surfaces by lapping and/or grinding. Subsequent steps, such as etching the semiconductor wafer and polishing the side surface, are carried out primarily to remove superficial damage which the mechanical processing steps have imparted, and to smooth the side surfaces.
  • DSP polishing A machine suitable for DSP polishing is described, for example, in DE 100 07 390 A1.
  • the semiconductor wafer lies in a recess of a carrier acting as a guide cage, and between an upper polishing plate and a lower polishing plate.
  • At least one polishing plate and the carrier are rotated and the semiconductor wafer is moved, while supplying a polishing agent, on a path predetermined by a milling curve relative to the polishing plates covered with polishing cloth.
  • the polishing pressure, with which the polishing plates press onto the semiconductor wafer, and the duration of the polishing are parameters which jointly determine crucially the material abrasion caused by polishing.
  • DE 199 56 250 C1 describes a method in which a mechanically processed and etched silicon semiconductor wafer is subjected first to DSP polishing and subsequently to quality control, in which the planarity is tested and compared with a setpoint value. If the required planarity has not yet been achieved, it is repolished by further, shorter DSP polishing.
  • DSP polishing is carried out in a first polishing step in order to give the semiconductor wafer a concave shape, differing from the ideal shape.
  • the concave shape of the polished side surface is removed by a subsequent one-sided polishing, referred to below as CMP polishing.
  • CMP polishing This exploits the fact that CMP polishing applied to a plane side surface tends to impart a convexly polished side surface, and the CMP polishing can produce a plane side surface if the side surface to be polished is shaped concavely.
  • the method mentioned above has the disadvantage that only an insufficient planarity of the side surface can be achieved thereby in the region of the wafer edge.
  • the CMP polishing thus reduces the local planarity already achieved by the DSP polishing in this region.
  • the region of the wafer edge is becoming ever more important for the producers of electronic components, however, since attempts are being made to extend the usable area of the polished side surface, referred to below as the “Fixed Quality Area”, or to recoup the economic value of the FQA at the cost of a conventional edge exclusion, referred to below as EE.
  • the edge roll-off referred to below as ERO, is responsible for non-planarity of the side surface in the edge region of the semiconductor wafer.
  • the ERO can be derived from the SFQR value of the partial sites.
  • the SFQR value describes the local planarity in a measurement field with a particular size, for example an area of 20 mm ⁇ 20 mm, and specifically in the form of the maximum height deviation of the front side of the semiconductor wafer from a reference surface of the same size obtained by least squares minimization.
  • Partial sites are measurement fields in the edge region which are no longer fully part of the FQA, but whose center still lies in the FQA.
  • the SFQR value of the partial sites will be referred to below as the PSFQR value.
  • Standardized parameters for such evaluation are the GBIR value and the SBIR value which is correlated therewith. Both values express the maximum height deviation of the front side relative to a back side of the semiconductor wafer, assumed to be ideally plane, and differ in that the FQA is used for calculation in the case of the GBIR value and the area restricted to the measurement field is used for calculation in the case of the SBIR value. Should the definitions given here differ from those of the SEMI standards, especially standards M59, M1 and M1530 in the current version, then the definitions of the standards should take precedence.
  • a method for polishing a semiconductor wafer between an upper polishing plate and a lower polishing plate, the semiconductor wafer being polished on both sides while lying in a recess of a carrier while supplying a polishing agent comprising double-sided polishing of the semiconductor wafer in a first polishing step, which is concluded with a negative overhang, the overhang being the difference between the thickness of the semiconductor wafer and the thickness of the carrier after the first polishing step, and double-sided polishing of the semiconductor wafer in a second polishing step, in which less than 1 ⁇ m of material is polished from the side surfaces of the semiconductor wafer.
  • FIG. 1A-1C illustrate the various polishing steps in one embodiment of the subject invention
  • FIG. 2 illustrates a concavity across the wafer surface achieved during a first polishing
  • FIG. 3 illustrates the planarity of a substantially planar wafer obtained after removing the concavity of FIG. 2 .
  • the local planarity achieved after the first polishing step, particularly in the edge region, can be preserved in the second polishing step and the global planarity can be improved, which leads overall to a planarity that satisfies the requirements of the component generation with a 32 nm line width.
  • the method described in the aforementioned DE 199 56 250 C1 and the method described in the aforementioned WO 00/47369 are not capable of doing this.
  • the global planarity achieved in the first polishing step is however reduced in the second polishing step.
  • the local planarity achieved by the first polishing step, particularly in the edge region is reduced by the second polishing step.
  • a silicon semiconductor wafer produced by the method according to the invention has a planarity which could not previously be achieved.
  • the invention therefore also relates to a silicon semiconductor wafer having a polished front side and a polished rear side with a front side global planarity expressed by an SBIRmax value of less than 100 nm, and with a front side local planarity expressed by a PSFQR value of 35 nm or less in an edge region, an edge exclusion of 2 mm being considered in each case.
  • the SBIRmax value is furthermore related to a measurement field area of 26 ⁇ 33 mm and an arrangement of the measurement field grid with offsets of 13 and 16.5 mm in the x and y directions.
  • the SBIRmax value describes the SBIR value of the measurement field with the greatest value among all the measurement fields.
  • the specification of the PSFQR value relates to a measurement field area of 20 ⁇ 20 mm and an arrangement of the measurement field grid with an offset of 10 mm in both the x and y directions.
  • the PSQR value is given by the sum of the PSFQR values of the partial sites divided by their number.
  • the starting product of the method is preferably a semiconductor wafer cut from a crystal, in particular from a silicon single crystal, which has been mechanically processed by lapping and/or grinding the side surfaces i.e. the front and rear sides of the semiconductor wafer.
  • the front side refers to the side surface which is intended to form the surface for providing structured electronic components.
  • the edge of the semiconductor wafer may already be rounded, in order to make it less sensitive to impact damage. Superficial damage due to the previous mechanical processing has furthermore been substantially removed by etching in an acidic and/or alkaline etchant.
  • the semiconductor wafer may already have been subjected to further processing steps, in particular cleaning steps or polishing the edge.
  • the semiconductor wafer is polished simultaneously on both sides in a first polishing step, in which case in order to increase the productivity, DSP polishing is preferably carried out as multi-wafer polishing in which a plurality of carriers are used, each with a plurality of recesses for semiconductor wafers.
  • a particular feature of the first DSP polishing is that a negative overhang is achieved, the overhang being the difference D 1 W-D 1 L between a thickness D 1 W of the semiconductor wafer after polishing has been concluded and a thickness D 1 L of the carrier used for polishing the semiconductor wafer.
  • the overhang is preferably less than 0 ⁇ m to ⁇ 4 ⁇ m, more preferably ⁇ 0.5 to ⁇ 4 ⁇ m, and preferably from 15 ⁇ m to 30 ⁇ m of material is abraded from the side surfaces overall.
  • the effect of the first polishing step is that the semiconductor wafer is curved concavely in a horizontally symmetrical way, so that the SBIR values lie in an unfavorably regarded range of more than 100 nm, and the SFQR values describing the local planarity, particularly the PSFQR values of the semiconductor wafer already lie in a favorably regarded range of 35 nm or less.
  • the aim of the second polishing step which is likewise carried out as DSP polishing, is to improve the global planarity and to preserve or likewise improve the local planarity already achieved, especially that in the edge region.
  • a particular feature of the second DSP polishing is that the desired effect is achieved by polishing less than 1 ⁇ m of material overall from the two sides of the semiconductor wafer.
  • the averaged material abrasion lies in the range of less than 1 ⁇ m, preferably in a range of from 0.2 ⁇ m to less than 1 ⁇ m.
  • the indicated upper limit should not be exceeded because this would detrimentally affect the global planarity of the semiconductor wafer.
  • the overhang is ⁇ 0 ⁇ m, the overhang being the difference D 2 W-D 2 L between a thickness D 2 W of the semiconductor wafer after the polishing has been concluded and a thickness of the carrier D 2 L used for polishing the semiconductor wafer.
  • the overhang is more preferably from 0 to 2 ⁇ m.
  • the effect of the second polishing step is that the SBIR values lie in a favorably regarded range of less than 100 nm, and that the SFQR values describing the local planarity, and in particular the PSFQR values, lie in a favorably regarded range of 35 nm or less.
  • the semiconductor wafer's concavity thereby achieved is determined, for example by measuring the GBIR value.
  • the measured value is used as an input value for calculating the duration of the second polishing step, via which the material abrasion to be achieved by the second polishing step is in turn established.
  • FIG. 1 schematically shows the semiconductor wafer lying between the polishing plates at various times in the method.
  • the semiconductor wafer 1 has a thickness DW which is greater than a thickness D 1 L of the carrier 21 .
  • the semiconductor wafer is polished in the first polishing step between an upper polishing plate 3 and a lower polishing plate 4 by using a particular polishing pressure and supplying a polishing agent, until a time b) is reached at which the difference between the thickness D 1 W of the polished semiconductor wafer and the thickness D 1 L of the carrier 21 has become negative.
  • the semiconductor wafer is subsequently subjected to the second DSP polishing with a carrier 22 , which is concluded at a time c).
  • FIGS. 2 and 3 show line scans along a diameter of the semiconductor wafer.
  • the semiconductor wafer After the first polishing step ( FIG. 2 ), the semiconductor wafer has a concave shape which is essentially attributable to raised material in a region which extends to about 100 mm inward. Only a slight edge roll-off still exists at the outer edge of the FQA. The consequence of the concavity of the semiconductor wafer is that the global planarity is unsatisfactory.
  • This changes after the second polishing step ( FIG. 3 ) which utilizes an initial effect of double-sided polishing, namely that raised material detrimentally affecting the global planarity is preferentially removed and the local planarity in the edge region thereof remains substantially unaffected.
  • Silicon semiconductor wafers having a diameter of 300 mm were cut from a single crystal and respectively pretreated in the same way by mechanical processing and etching. They were subsequently polished in a type AC 2000 double-sided polishing machine from Peter Wolters AG, until a negative overhang (underhang) had been reached (Example E and comparative example C2) or until a positive overhang (comparative example C1) had been reached. Some of the semiconductor wafers (C1) were subsequently subjected to a second DSP polishing, which was concluded with a positive overhang and material abrasion of more than 1 ⁇ m. Other semiconductor wafers (C2) were subjected to CMP polishing, which was concluded with material abrasion of less than 1 ⁇ m.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
US11/853,103 2006-09-20 2007-09-11 Method For Polishing A Semiconductor Wafer And Polished Semiconductor Wafer Producible According To The Method Abandoned US20080070483A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006044367A DE102006044367B4 (de) 2006-09-20 2006-09-20 Verfahren zum Polieren einer Halbleiterscheibe und eine nach dem Verfahren herstellbare polierte Halbleiterscheibe
DE102006044367.5 2006-09-20

Publications (1)

Publication Number Publication Date
US20080070483A1 true US20080070483A1 (en) 2008-03-20

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US11/853,103 Abandoned US20080070483A1 (en) 2006-09-20 2007-09-11 Method For Polishing A Semiconductor Wafer And Polished Semiconductor Wafer Producible According To The Method

Country Status (7)

Country Link
US (1) US20080070483A1 (zh)
JP (1) JP2008078660A (zh)
KR (2) KR100915433B1 (zh)
CN (1) CN101148025B (zh)
DE (1) DE102006044367B4 (zh)
SG (2) SG169385A1 (zh)
TW (1) TWI336280B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100055908A1 (en) * 2008-08-27 2010-03-04 Siltronic Ag Method for producing a semiconductor wafer
DE102009049330B3 (de) * 2009-10-14 2011-02-17 Siltronic Ag Verfahren zum Nachpolieren einer Halbleiterscheibe
US20120028547A1 (en) * 2009-05-08 2012-02-02 Sumco Corporation Semiconductor wafer polishing method and polishing pad shaping jig
US10189142B2 (en) 2012-12-04 2019-01-29 Siltronic Ag Method for polishing a semiconductor wafer
US11145556B2 (en) * 2019-11-21 2021-10-12 Carl Zeiss Smt Gmbh Method and device for inspection of semiconductor samples
CN115427193A (zh) * 2020-05-13 2022-12-02 信越半导体株式会社 双面研磨方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008045534B4 (de) * 2008-09-03 2011-12-01 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe
DE102009025243B4 (de) * 2009-06-17 2011-11-17 Siltronic Ag Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe aus Silicium
DE102009030292B4 (de) * 2009-06-24 2011-12-01 Siltronic Ag Verfahren zum beidseitigen Polieren einer Halbleiterscheibe
DE102009037281B4 (de) * 2009-08-12 2013-05-08 Siltronic Ag Verfahren zur Herstellung einer polierten Halbleiterscheibe
JP5423384B2 (ja) 2009-12-24 2014-02-19 株式会社Ｓｕｍｃｏ 半導体ウェーハおよびその製造方法
US8952496B2 (en) 2009-12-24 2015-02-10 Sumco Corporation Semiconductor wafer and method of producing same
DE102010013520B4 (de) * 2010-03-31 2013-02-07 Siltronic Ag Verfahren zur beidseitigen Politur einer Halbleiterscheibe
KR101660900B1 (ko) * 2015-01-16 2016-10-10 주식회사 엘지실트론 웨이퍼 연마 장치 및 이를 이용한 웨이퍼 연마 방법
CN111479654B (zh) * 2017-12-22 2022-07-01 东京毅力科创株式会社 基板处理系统、基板处理方法以及计算机存储介质

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US6051498A (en) * 1997-02-06 2000-04-18 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag Method for manufacturing a semiconductor wafer which is coated on one side and provided with a finish
US6299514B1 (en) * 1999-03-13 2001-10-09 Peter Wolters Werkzeugmachinen Gmbh Double-disk polishing machine, particularly for tooling semiconductor wafers
US20030045089A1 (en) * 1999-02-11 2003-03-06 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag Semiconductor wafer with improved flatness, and process for producing the semiconductor wafer
US6566267B1 (en) * 1999-11-23 2003-05-20 WACKER SILTRONIC GESELLSCHAFT FüR HALBLEITERMATERIALIEN AG Inexpensive process for producing a multiplicity of semiconductor wafers
US20030186624A1 (en) * 2002-03-29 2003-10-02 Hoya Corporation Method of determining a flatness of an electronic device substrate, method of producing the substrate, method of producing a mask blank, method of producing a transfer mask, polishing method, electronic device substrate, mask blank, transfer mask, and polishing apparatus
US20080096474A1 (en) * 2004-10-27 2008-04-24 Shin-Etsu Handotai Co., Ltd. Method for Producing Semiconductor Wafer and Semiconductor Wafer

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JPH05177539A (ja) * 1991-12-24 1993-07-20 Sumitomo Electric Ind Ltd 両面ポリッシュ装置によるウェハ研磨方法
WO2000047369A1 (en) * 1999-02-12 2000-08-17 Memc Electronic Materials, Inc. Method of polishing semiconductor wafers
DE10007390B4 (de) * 1999-03-13 2008-11-13 Peter Wolters Gmbh Zweischeiben-Poliermaschine, insbesondere zur Bearbeitung von Halbleiterwafern
JP4280397B2 (ja) * 1999-10-21 2009-06-17 スピードファム株式会社 ワークの研磨方法
DE10023002B4 (de) * 2000-05-11 2006-10-26 Siltronic Ag Satz von Läuferscheiben sowie dessen Verwendung
JP4352229B2 (ja) * 2003-11-20 2009-10-28 信越半導体株式会社 半導体ウェーハの両面研磨方法
JP2006198751A (ja) * 2005-01-24 2006-08-03 Showa Denko Kk 磁気ディスク用サブストレート基板の製造方法及び研磨装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051498A (en) * 1997-02-06 2000-04-18 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag Method for manufacturing a semiconductor wafer which is coated on one side and provided with a finish
US20030045089A1 (en) * 1999-02-11 2003-03-06 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag Semiconductor wafer with improved flatness, and process for producing the semiconductor wafer
US6299514B1 (en) * 1999-03-13 2001-10-09 Peter Wolters Werkzeugmachinen Gmbh Double-disk polishing machine, particularly for tooling semiconductor wafers
US6566267B1 (en) * 1999-11-23 2003-05-20 WACKER SILTRONIC GESELLSCHAFT FüR HALBLEITERMATERIALIEN AG Inexpensive process for producing a multiplicity of semiconductor wafers
US20030186624A1 (en) * 2002-03-29 2003-10-02 Hoya Corporation Method of determining a flatness of an electronic device substrate, method of producing the substrate, method of producing a mask blank, method of producing a transfer mask, polishing method, electronic device substrate, mask blank, transfer mask, and polishing apparatus
US20080096474A1 (en) * 2004-10-27 2008-04-24 Shin-Etsu Handotai Co., Ltd. Method for Producing Semiconductor Wafer and Semiconductor Wafer

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100055908A1 (en) * 2008-08-27 2010-03-04 Siltronic Ag Method for producing a semiconductor wafer
DE102008044646A1 (de) 2008-08-27 2010-03-25 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe
DE102008044646B4 (de) * 2008-08-27 2011-06-22 Siltronic AG, 81737 Verfahren zur Herstellung einer Halbleiterscheibe
US8242020B2 (en) 2008-08-27 2012-08-14 Siltronic Ag Method for producing a semiconductor wafer
US20120028547A1 (en) * 2009-05-08 2012-02-02 Sumco Corporation Semiconductor wafer polishing method and polishing pad shaping jig
US8647174B2 (en) * 2009-05-08 2014-02-11 Sumco Corporation Semiconductor wafer polishing method and polishing pad shaping jig
DE102009049330B3 (de) * 2009-10-14 2011-02-17 Siltronic Ag Verfahren zum Nachpolieren einer Halbleiterscheibe
US10189142B2 (en) 2012-12-04 2019-01-29 Siltronic Ag Method for polishing a semiconductor wafer
US11145556B2 (en) * 2019-11-21 2021-10-12 Carl Zeiss Smt Gmbh Method and device for inspection of semiconductor samples
CN115427193A (zh) * 2020-05-13 2022-12-02 信越半导体株式会社 双面研磨方法

Also Published As

Publication number Publication date
KR20080026485A (ko) 2008-03-25
SG141306A1 (en) 2008-04-28
DE102006044367B4 (de) 2011-07-14
SG169385A1 (en) 2011-03-30
KR100915433B1 (ko) 2009-09-03
JP2008078660A (ja) 2008-04-03
TWI336280B (en) 2011-01-21
CN101148025A (zh) 2008-03-26
TW200815153A (en) 2008-04-01
KR100945774B1 (ko) 2010-03-08
DE102006044367A1 (de) 2008-04-03
CN101148025B (zh) 2010-06-23
KR20090020671A (ko) 2009-02-26

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Owner name: SILTRONIC AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROETTGER, KLAUS;DUTSCHKE, VLADIMIR;MISTUR, LESZEK;REEL/FRAME:019807/0779;SIGNING DATES FROM 20070824 TO 20070827

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