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US20070249111A1 - TFT array substrate and photo-masking method for fabricating same - Google Patents

TFT array substrate and photo-masking method for fabricating same Download PDF

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Publication number
US20070249111A1
US20070249111A1 US11/788,908 US78890807A US2007249111A1 US 20070249111 A1 US20070249111 A1 US 20070249111A1 US 78890807 A US78890807 A US 78890807A US 2007249111 A1 US2007249111 A1 US 2007249111A1
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photo
gate
pattern
layer
forming
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US11/788,908
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Yao-Nan Lin
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Innolux Corp
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Innolux Display Corp
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Publication of US20070249111A1 publication Critical patent/US20070249111A1/en
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Assigned to Innolux Corporation reassignment Innolux Corporation CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: CHIMEI INNOLUX CORPORATION
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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/0001—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings specially adapted for lighting devices or systems
    • G02B6/0011—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings specially adapted for lighting devices or systems the light guides being planar or of plate-like form
    • G02B6/0081—Mechanical or electrical aspects of the light guide and light source in the lighting device peculiar to the adaptation to planar light guides, e.g. concerning packaging
    • G02B6/0083—Details of electrical connections of light sources to drivers, circuit boards, or the like

Definitions

  • the present invention relates to thin film transistor (TFT) array substrates used in liquid crystal displays (LCDs) and methods of fabricating these substrates, and particularly to a TFT array substrate and a method for fabricating the substrate which efficiently uses minimal photo-masking.
  • TFT thin film transistor
  • a typical liquid crystal display is capable of displaying a clear and sharp image through millions of pixels that make up the complete image.
  • the liquid crystal display has thus been applied to various electronic equipments in which messages or pictures need to be displayed, such as mobile phones and notebook computers.
  • a liquid crystal panel is a major component of the LCD, and generally includes a thin film transistor (TFT) array substrate, a color filter substrate opposite to the TFT array substrate, and a liquid crystal layer sandwiched between the two substrates.
  • TFT thin film transistor
  • the TFT array substrate 100 includes a substrate 101 , a gate electrode 102 formed on the substrate 101 , a gate insulating layer 103 formed on the substrate 101 having the gate electrode 102 , a semiconducting layer 104 formed on the gate insulating layer 103 , a source electrode 105 and a drain electrode 106 formed on the gate insulating layer 103 and the semiconducting layer 104 , a passivation layer 107 formed on the gate insulating layer 103 , the source electrode 105 and the drain electrode 106 , and a pixel electrode 108 formed on the passivation layer 107 .
  • this is a flowchart summarizing a typical method for fabricating the TFT array substrate 100 .
  • the flowchart and the following description are couched in terms that relate to the part of the TFT array substrate 100 shown in FIG. 19 .
  • the method includes: step S 10 , forming a gate metal layer; step S 11 , forming a gate electrode; step S 12 , forming a gate insulating layer and an amorphous silicon (a-Si) and doped a-Si layer; step S 13 , forming a semiconducting layer on the gate insulating layer; step S 14 , forming a source/drain metal layer; step S 15 , forming source/drain electrodes; step S 16 , forming a passivation material layer; step S 17 , forming a passivation layer; step S 18 , forming a transparent conductive layer; and step S 19 , forming a pixel electrode.
  • step S 10 forming a gate metal layer
  • step S 11 forming a gate electrode
  • step S 12 forming a gate insulating layer and an amorphous silicon (a-Si) and doped a-Si layer
  • step S 13 forming a semiconducting layer on the gate insulating
  • an insulating substrate is provided.
  • the substrate may be made from glass or quartz.
  • a gate metal layer and a first photo-resist layer are formed on the substrate.
  • step S 11 the first photo-resist layer is exposed by a first photo-mask, and then is developed, thereby forming a first photo-resist pattern.
  • the gate metal layer is etched, thereby forming a pattern of the gate electrode 102 , which corresponds to the first photo-resist pattern.
  • the residual first photo-resist layer is then removed by an acetone solution.
  • step S 12 a gate insulating layer 103 , an a-Si and doped a-Si layer, and a second photo-resist layer are sequentially formed on the substrate 101 having the gate electrode 102 .
  • step S 13 the second photo-resist layer is exposed by a second photo-mask, and then is developed, thereby forming a second photo-resist pattern.
  • the a-Si and doped a-Si layer is etched, thereby forming a pattern of the semiconducting layer 104 , which corresponds to the second photo-resist pattern.
  • the residual second photo-resist layer is then removed by an acetone solution.
  • step S 14 a source/drain metal layer and a third photo-resist layer are sequentially formed on the semiconducting layer 104 .
  • step S 15 the third photo-resist layer is exposed by a third photo-mask, and then is developed, thereby forming a third photo-resist pattern.
  • the source/drain metal layer is etched, thereby forming a pattern of the source electrode 105 and the drain electrode 106 , which corresponds to the third photo-resist pattern.
  • the residual third photo-resist layer is then removed by an acetone solution.
  • step S 16 a passivation material layer and a fourth photo-resist layer are sequentially formed on the substrate 101 having the three electrodes 102 , 105 , 106 formed thereon.
  • step S 17 the fourth photo-resist layer is exposed by a fourth photo-mask, and then is developed, thereby forming a fourth photo-resist pattern.
  • the passivation material layer is etched, thereby forming a pattern of the passivation layer 107 , which corresponds to the fourth photo-resist pattern.
  • the residual fourth photo-resist layer is then removed by an acetone solution.
  • step S 18 a transparent conductive layer and a fifth photo-resist layer are sequentially formed on the passivation layer 107 .
  • step S 19 the fifth photo-resist layer is exposed by a fifth photo-mask, and then is developed, thereby forming a fifth photo-resist pattern.
  • the transparent conductive layer is etched, thereby forming a pattern of the pixel electrode 108 , which corresponds to the fifth photo-resist pattern.
  • the residual fifth photo-resist layer is then removed by an acetone solution.
  • the method includes five photo-mask processes, each of which is rather complicated and costly.
  • the method for fabricating the TFT array substrate 100 is correspondingly complicated and costly.
  • a method for fabricating a thin film transistor (TFT) array substrate includes providing an insulating substrate; forming a transparent conductive metal layer and a gate metal layer on the insulating substrate; forming a gate electrode, a gate line and a pixel electrode through a first photolithograph process; forming a gate insulating layer, an amorphous silicon pattern, and a doped amorphous silicon pattern through a second photolithograph process; forming a photo-resist pattern on the gate electrode through a third photolithograph process, using the gate electrode as a photo-mask; forming a source/drain metal layer on the insulating substrate, the doped amorphous silicon layer, the photo-resist pattern and the pixel electrode; forming a source/drain metal pattern through removing the photo-resist pattern and a portion of the source/drain metal layer on the photo-resist pattern; and forming a passivation layer pattern, a source/drain electrode through a fourth photo
  • An exemplary TFT array substrate includes an insulating substrate; a transparent conductive line formed on the insulating substrate; a plurality of gate lines formed on the transparent conductive line, that are parallel to each other and that each extend along a first direction; a plurality of data lines formed on the insulating substrate, that are parallel to each other and that each extend along a second direction orthogonal to the first direction.
  • the gate line at an intersection point of the gate line and the data line are disconnected.
  • FIG. 1 is a schematic, top view of a pixel of a TFT array substrate according to an exemplary embodiment of the present invention.
  • FIG. 2 is a schematic, side cross-sectional view of the TFT array substrate of FIG. 1 , taken along the line II-II.
  • FIG. 3 is a schematic, side cross-sectional view of the TFT array substrate of FIG. 1 , taken along the line III-III.
  • FIG. 4 is a flowchart summarizing an exemplary method for fabricating the TFT array substrate of FIG. 1 .
  • FIG. 5 is a schematic, side cross-sectional view relating to a step of providing a substrate and forming a transparent conductive metal layer, a gate metal layer, and a first photo-resist layer on the substrate according to the method of FIG. 4 .
  • FIG. 6 is a schematic, side cross-sectional view relating to a next step of exposing a first photo-resist layer using a slit photo-mask according to the method of FIG. 4 .
  • FIG. 7 is a schematic, side cross-sectional view relating to a next step of forming a first photo-resist pattern according to the method of FIG. 4 .
  • FIG. 8 is a schematic, side cross-sectional view relating to a next step of forming a gate electrode pattern and a transparent conductive metal layer pattern according to the method of FIG. 4 .
  • FIG. 9 is a schematic, side cross-sectional view relating to a next step of forming a gate electrode and a gate line according to the method of FIG. 4 .
  • FIG. 10 is a schematic, side cross-sectional view relating to a next step of forming a gate insulating layer on the substrate having the gate electrode according to the method of FIG. 4 .
  • FIG. 11 is a schematic, side cross-sectional view relating to a next step of forming a third photo-resist layer on the substrate according to the method of FIG. 4 .
  • FIG. 12 is a schematic, side cross-sectional view relating to a next step of exposing the third photo-resist layer from a bottom side of the substrate according to the method of FIG. 4 .
  • FIG. 13 is a schematic, side cross-sectional view relating to a next step of forming a third photo-resist pattern according to the method of FIG. 4 .
  • FIG. 14 is a schematic, side cross-sectional view relating to a next step of depositing a source/drain metal layer on the substrate and the third photo-resist pattern according to the method of FIG. 4 .
  • FIG. 15 is a schematic, side cross-sectional view relating to a next step of removing the third photo-resist pattern and a portion of the source/drain metal layer on the photo-resist pattern according to the method of FIG. 4 .
  • FIG. 16 is a schematic, side cross-sectional view relating to a next step of depositing a passivation layer and a fourth photo-resist layer on the substrate according to the method of FIG. 4 .
  • FIG. 17 is a schematic, side cross-sectional view relating to a step of etching away a portion of the passivation material layer and a portion of the source/drain metal layer pattern according to the method of FIG. 2 .
  • FIG. 18 is a schematic, side cross-sectional view relating to a step of removing the remained fourth photo-resist layer according to the method of FIG. 2 .
  • FIG. 19 is a schematic, side cross-sectional view of part of a conventional TFT array substrate.
  • FIG. 20 is a flowchart summarizing a conventional method for fabricating the TFT array substrate of FIG. 17 .
  • the TFT array substrate 2 includes a plurality of gate lines 210 that are parallel to each other and that each extend along a first direction, a plurality of data lines 220 that are parallel to each other and that each extend along a second direction orthogonal to the first direction, and a plurality of common line 225 .
  • the smallest rectangular area formed by any two adjacent gate lines 210 together with any two adjacent data lines 220 defines a pixel region thereat.
  • a TFT 230 is provided in the vicinity of a respective point of intersection of one of the gate lines 210 and one of the data lines 220 .
  • a pixel electrode 222 is connected to the TFT 230 .
  • Each TFT 230 has a gate electrode 223 electrically connecting with the gate line 210 , a source electrode 227 electrically connecting with the data line 220 , and a drain electrode 228 connected to the pixel electrode 222 .
  • the common line 225 is disposed between the pixel electrode 222 and its adjacent gate line 210 , extending along a direction parallel to the gate line 210 .
  • a storage capacitor 240 is parallel to the gate lines 210 above part of the common line 225 .
  • the storage capacitor 240 has a capacitor electrode 229 , which is connected to one side of the pixel electrode 222 , far away the corresponding TFT 230 .
  • the TFT array substrate 2 further includes an insulating substrate 201 , a transparent conductive line 221 , a gate insulating pattern 214 , an amorphous silicon (a-Si) pattern 215 , a doped a-Si pattern 216 and a passivation layer 219 .
  • the transparent conductive line 221 , the pixel electrode 222 and the common line 225 are formed on the insulating substrate 201 .
  • the gate electrode 223 and the gate line 210 are formed on the transparent conductive line 221 .
  • the gate insulating pattern 214 is formed on a part of the intersections of the gate electrode 212 , the common line 225 , the gate line 210 with the data line 220 .
  • the a-Si pattern 215 and the doped a-Si pattern 216 are orderly formed on the gate insulating layer pattern 214 .
  • the source electrode 227 and the drain electrode 228 are formed on the doped a-Si pattern 216 .
  • the capacitor electrode 229 are disposed on the doped amorpuous silicon pattern 216 , corresponding to the common line 225 .
  • the passivation layer 219 is formed on the TFT 230 and the storage capacitor 240 .
  • the gate line 210 at the intersection point of the gate line 210 and the data line 220 are disconnected, forming a disconnected region thereat.
  • the gate line 210 keeps electrical connection through the underlie transparent conductive line 221 .
  • the disconnected region of the gate line 210 can prevent a short circuit or open circuit between the gate line 210 and the corresponding data line 220 .
  • this is a flowchart summarizing an exemplary method for fabricating the TFT array substrate 2 .
  • the flowchart and the following description are couched in terms that relate to the part of the TFT array substrate 2 shown in FIG. 1 .
  • the method includes: step S 201 , forming a transparent conductive metal layer and a gate metal layer; step S 202 , forming a gate electrode (gate line) and a pixel electrode; step S 203 , forming a gate insulating layer, an a-Si layer, and a doped a-Si layer; step S 204 , forming a gate insulating pattern, an a-Si pattern, and a doped a-Si pattern; step S 205 , forming a source/drain metal pattern; step S 206 , forming a passivation layer, a source electrode and a drain electrode.
  • an insulating substrate 201 is provided.
  • the substrate 201 may be made from glass or quartz.
  • a transparent conductive metal layer 202 , a gate metal layer 203 , and a first photo-resist layer 231 are sequentially formed on the substrate 201 .
  • the trans parent conductive metal layer 202 may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
  • the gate metal layer 203 may be made from material including any one or more items selected from the group consisting of aluminum (Al), molybdenum (Mo), copper (Cu), chromium (Cr), and tantalum (Ta).
  • a light source (not shown) and a first photo-mask 250 are used to expose the first photo-resist layer 231 .
  • the first photo mask 250 is a slit mask having a light shield area 251 , a slit area 252 , and a transparent area 253 .
  • the first photo-resist layer 231 is exposed using the first photo mask 250 .
  • the exposed second photo-resist layer is developed, thereby forming a first photo-resist pattern.
  • a first thickness of a first part 233 of the first photo-resist pattern, corresponding to the shield area 251 is greater than a second thickness of a second part 232 of the first photo-resist pattern, corresponding to the slit area 252 , because the slit area 252 has a larger luminous flux.
  • the transparent conductive metal layer 202 and the gate metal layer 203 are etched, thereby forming a gate electrode pattern 213 and a transparent conductive metal pattern 212 .
  • the transparent conductive metal pattern 212 includes the pixel electrode 222 , the common line 225 and the transparent conductive line 221 .
  • the second part 232 of the first photo-resist pattern, part of the first part 232 of the first photo-resist pattern, a part of the gate metal pattern 213 corresponding to the second part 232 are etched away. And then, the remained first part 232 of the first photo-resist pattern is removed away, thereby forming the gate electrode 223 and the gate line 210 on the transparent conductive line 221 .
  • the gate line 210 at the intersection point of the gate line 210 and the data line 220 are disconnected, forming a disconnected region thereat.
  • the gate line 210 keeps electrical connection through the underlie transparent conductive line 221 .
  • the gate metal line 203 are formed on the transparent conductive metal layer 202 , and the gate electrode 223 and the pixel electrode 222 don't overlap with each other, only one photo-mask process is used to form the gate electrode 223 and the pixel electrode 222 , thus saving one photo-mask process.
  • a gate insulating layer 204 is formed on the substrate 201 having the gate electrode 223 , the pixel electrode 222 and the common line 225 by a chemical vapor deposition (CVD) process.
  • silane (SiH 4 ) reacts with alkaline air (NH4+) to obtain silicon nitride (SiN x ), a material of the gate insulating layer 204 .
  • An amorphous silicon (a-Si) material is deposited on the gate insulating layer 204 by a CVD process.
  • the a-Si layer is doped, thereby respectively forming the a-Si layer 205 and the doped a-Si layer 206 .
  • a second photo-resist layer is coated on the doped a-Si layer 206 .
  • An ultra violet (UV) light source and a photo-mask are used to expose the second photo-resist layer. Then the exposed second photo-resist layer is developed, thereby forming a second photo-resist pattern.
  • UV ultra violet
  • portions of the gate insulating layer 204 , the a-Si layer 205 and the doped a-Si layer 206 which are not covered by the second photo-resist pattern are etched away, thereby forming a gate insulating layer pattern 214 , an a-Si pattern 215 and a doped a-Si pattern 216 .
  • a third photo-resist layer 241 is coated on the gate insulating layer pattern 214 , the substrate 201 and the pixel electrode 222 .
  • An ultra violet (UV) light source is used to expose the third photo-resist layer 241 , from a bottom side of the substrate 201 which is opposite to a top side where the gate electrode 223 and the pixel electrode 22 are formed thereon, using the gate electrode 223 as a photo-mask.
  • the exposed third photo-resist layer 241 is developed, thereby forming a third photo-resist pattern 242 (as shown in FIG. 13 ). Referring to FIG.
  • a source/drain metal layer 207 is then deposited on the doped a-Si pattern 216 , the substrate 201 , the third photo-resist pattern 242 and the pixel electrode 222 .
  • the source/drain metal layer 207 may be made from material including any one or more items selected from the group consisting of aluminum, aluminum alloy, molybdenum, tantalum, and molybdenum-tungsten alloy.
  • portions of the doped a-Si pattern 216 which are not covered by the source/drain metal pattern 217 are etched away, thereby forming a groove 226 thereof (as shown in FIG. 15 ).
  • step S 206 referring to FIG. 16 , a passivation material layer 209 and a fourth photo-resist layer (not labeled) are deposited on the source/drain metal layer pattern 217 and the groove 226 .
  • a light source and a third photo-mask are used to expose the fourth photo-resist layer, thereby forming a fourth photo-resist pattern 252 .
  • a portion of the passivation material layer 209 and a portion of the source/drain metal layer pattern 217 which are not covered by the fourth photo-resist pattern 252 is etched away; thereby exposing a portion of the pixel electrode 222 and forming the source electrode 227 , the drain electrode 228 and the capacitor electrode 229 and the passivation layer 219 (as shown in FIG. 18 ).
  • the above-described exemplary method for fabricating the TFT array substrate 2 compared to the above-described conventional method, only one photo-mask process is used to form the gate electrode 223 and the pixel electrode 222 .
  • the gate electrode 223 is used as a mask, thereby a predetermined mask is saved. That is, the method for fabricating the TFT array substrate 2 only includes a total of four photo-mask processes. Therefore, a simplified method at a reduced cost is provided.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Planar Illumination Modules (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
US11/788,908 2006-04-21 2007-04-23 TFT array substrate and photo-masking method for fabricating same Abandoned US20070249111A1 (en)

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TW095114351A TWI326375B (en) 2006-04-21 2006-04-21 Liquid crystal display device
TW95114351 2006-04-21

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Cited By (2)

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US20100009481A1 (en) * 2008-07-09 2010-01-14 Au Optronics Corporation Method for fabricating thin film transistor array substrate
DE102009060066A1 (de) * 2009-09-25 2011-03-31 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen eines elektronischen Bauelements sowie elektronisches Bauelement

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101338996B1 (ko) * 2008-12-26 2013-12-09 엘지디스플레이 주식회사 액정표시장치

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US5926702A (en) * 1996-04-16 1999-07-20 Lg Electronics, Inc. Method of fabricating TFT array substrate
US6358773B1 (en) * 2000-12-27 2002-03-19 Vincent Lin Method of making substrate for use in forming image sensor package
US7001796B2 (en) * 2003-10-28 2006-02-21 Lg.Philips Lcd Co., Ltd. Method for fabricating array substrate of liquid crystal display device
US7202502B2 (en) * 1998-11-26 2007-04-10 Samsung Electronics Co., Ltd. Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films

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TWI286629B (en) * 2000-07-20 2007-09-11 Samsung Electronics Co Ltd Liquid crystal display device and flexible circuit board
TWI230827B (en) 2004-02-12 2005-04-11 Au Optronics Corp Liquid crystal display module
KR100719923B1 (ko) * 2005-03-10 2007-05-18 비오이 하이디스 테크놀로지 주식회사 액정표시모듈
US7646450B2 (en) * 2005-12-29 2010-01-12 Lg Display Co., Ltd. Light emitting diode array, method of manufacturing the same, backlight assembly having the same, and LCD having the same

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US5926702A (en) * 1996-04-16 1999-07-20 Lg Electronics, Inc. Method of fabricating TFT array substrate
US7202502B2 (en) * 1998-11-26 2007-04-10 Samsung Electronics Co., Ltd. Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
US6358773B1 (en) * 2000-12-27 2002-03-19 Vincent Lin Method of making substrate for use in forming image sensor package
US7001796B2 (en) * 2003-10-28 2006-02-21 Lg.Philips Lcd Co., Ltd. Method for fabricating array substrate of liquid crystal display device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100009481A1 (en) * 2008-07-09 2010-01-14 Au Optronics Corporation Method for fabricating thin film transistor array substrate
US8058087B2 (en) * 2008-07-09 2011-11-15 Au Optronics Corporation Method for fabricating thin film transistor array substrate
US20110318856A1 (en) * 2008-07-09 2011-12-29 Au Optronics Corporation Method for fabricating thin film transistor array substrate
US8349631B2 (en) * 2008-07-09 2013-01-08 Au Optronics Corporation Method for fabricating thin film transistor array substrate
DE102009060066A1 (de) * 2009-09-25 2011-03-31 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen eines elektronischen Bauelements sowie elektronisches Bauelement
US9203029B2 (en) 2009-09-25 2015-12-01 Osram Opto Semiconductors Gmbh Method for producing an electronic component
US9583729B2 (en) 2009-09-25 2017-02-28 Osram Oled Gmbh Method for producing an electronic component
DE102009060066B4 (de) 2009-09-25 2017-03-30 Osram Oled Gmbh Verfahren zum Herstellen eines elektronischen Bauelements sowie elektronisches Bauelement

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TW200741290A (en) 2007-11-01
US20070247563A1 (en) 2007-10-25
US7724339B2 (en) 2010-05-25
TWI326375B (en) 2010-06-21

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