US20050277282A1 - Method of manufacturing wiring substrate - Google Patents
Method of manufacturing wiring substrate Download PDFInfo
- Publication number
- US20050277282A1 US20050277282A1 US11/135,350 US13535005A US2005277282A1 US 20050277282 A1 US20050277282 A1 US 20050277282A1 US 13535005 A US13535005 A US 13535005A US 2005277282 A1 US2005277282 A1 US 2005277282A1
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- United States
- Prior art keywords
- conductive parts
- substrate
- resin layer
- core substrate
- manufacturing
- Prior art date
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Links
- 239000000758 substrate Substances 0.000 title claims description 187
- 238000004519 manufacturing process Methods 0.000 title claims description 41
- 229920005989 resin Polymers 0.000 claims description 92
- 239000011347 resin Substances 0.000 claims description 92
- 239000002184 metal Substances 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 22
- 239000012212 insulator Substances 0.000 claims description 10
- 229920005992 thermoplastic resin Polymers 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 238000003780 insertion Methods 0.000 claims description 7
- 230000037431 insertion Effects 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 229920006122 polyamide resin Polymers 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 1
- 238000007772 electroless plating Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 239000007864 aqueous solution Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- 229910021592 Copper(II) chloride Inorganic materials 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 1
- 239000012935 ammoniumperoxodisulfate Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000010808 liquid waste Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10242—Metallic cylinders
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
Definitions
- the present invention relates to a method of manufacturing a wiring substrate and, more particularly, a method of manufacturing a wiring substrate having a structure that enable conduction of both surface sides of a core substrate via through holes provided in the core substrate.
- the wiring substrate having the structure in which the wiring patterns formed on both surface sides of the core substrate are connected mutually via the conductors provided in the through holes in the core substrate.
- FIG. 1A As the method of manufacturing such wiring substrate, as shown in FIG. 1A , at first through holes 100 x are formed in a core substrate 100 made of a glass epoxy resin, or the like, and then insides of the through holes 100 x are cleaned by a desmear process using a permanganic acid, or the like. Then, as shown in FIG. 1B , a seed layer (not shown) is formed on both surfaces of the core substrate 100 and side surfaces of the through holes 100 x by the electroless plating, and then a metal layer (not shown) is formed on the seed layer by the electroless plating utilizing the seed layer as a plating-power feeding layer, and thus first conductive layers 102 are obtained. Accordingly, both surface sides of the core substrate 100 can be brought into a conductive condition via the first conductive layer 102 provided in the through holes 100 x . At this time, cavity is left in the through holes 100 x in the core substrate 100 respectively.
- an insulating resin body 104 is filled in the cavities of the through holes 100 x .
- projected portions of the insulating resin bodies 104 projected from the first conductive layer 102 are polished on both surface sides of the core substrate 100 respectively.
- an upper surface and a lower surface of the insulating resin body 104 are planarized to get substantially coplanar surfaces with exposed surfaces of the first conductive layers 102 on the upper side and the lower side of the core substrate 100 respectively.
- a resultant structure in FIG. 1D is cleaned by applying the desmear process thereto, then a seed layer (not shown) is formed on the first conductive layer 102 on both surface sides of the core substrate 100 by the electroless plating respectively, and then a metal layer (not shown) is formed on the seed layer by the electroplating utilizing the seed layer as the plating-power feeding layer, and thus a second conductive layer 106 is obtained on both surface sides respectively.
- wiring patterns 108 each composed of the first and second conductive layers 102 , 106 are formed on both surfaces by patterning the second conductive layer 106 and the first conductive layer 102 .
- the wiring patterns 108 on both surface sides of the core substrate 100 are connected mutually via the first conductive layers 102 in the through holes 100 x in the core substrate 100 .
- the steps of the desmear process, the electroless plating, and the electroplating are required in the case of forming the first conductive layers 102 for enabling conduction of both surface sides of the core substrate mutually, in the through holes 100 x respectively.
- the manufacturing steps become complicated because many manufacturing steps are needed, and the heavy burden of the chemicals preparation and the liquid waste processing is imposed.
- the through holes 100 x are formed in the core substrate 100 , and then metal posts 110 are inserted into the through holes 100 x .
- a conductive layer 112 is formed on both surfaces of the core substrate 100 by the electroless plating and the electroplating respectively, and then wiring patterns 114 are formed by patterning the conductive layer 112 on both surfaces respectively. Accordingly, the wiring patterns 114 formed on both surfaces of the core substrate 100 respectively are connected mutually via the metal posts 110 in the through holes 100 x.
- Patent Literature 1 Patent Application Publication (KOKAI) 2002-289999
- Patent Literature 2 Patent Application Publication (KOKAI) 2003-220595
- Patent Literature 3 Patent Application Publication (KOKAI) 2001-352166
- FIG. 3 is an enlarged sectional view showing a behavior between the through hole 100 x in the core substrate 100 and the metal post 110 in FIG. 2B .
- a clearance G is ready to occur between the through hole 100 x and the metal post 110 . This is because it is difficult to reconcile an inner diameter of the through hole 100 x with an outer diameter of the metal post 110 perfectly and also the defects such that the metal post 110 is bent partially upon inserting the metal post 110 into the through hole 100 x , and the like are caused.
- the plating is not partially applied owing to the influence of the clearance G in forming the wiring patterns 114 on both surface side of the core substrate 100 , and thus there is such a possibility that the wiring patterns 114 are disconnected.
- the projected portions of the metal posts 110 must be removed by the polishing or the etching to get the flat surface.
- the metal posts 110 are not perfectly fixed to the through holes 100 x , sometimes the metal posts 110 drop out at the time of polishing, or the etchant sinks into the clearance to etch unnecessarily the metal posts 110 at the time of etching.
- the disadvantages such as the connection failure between the metal posts 110 and the wiring patterns 114 , and the like are ready to generate and thus it is extremely difficult to manufacture the highly-reliable wiring substrate at high yield.
- a method of manufacturing a wiring substrate of the present invention comprises the steps of preparing a substrate including a semi-cured resin layer or a thermo plastic resin layer; forming a through hole that passes through the substrate; inserting a conductive parts in the through hole; curing the semi-cured resin layer or the thermo plastic resin layer in a state that the resin layer is made to flow by applying a heat and a pressure to the substrate, and filling a clearance between the through hole and the conductive parts with the resin layer; and forming a wiring pattern, which is connected mutually via the conductive parts, on both surface sides of the substrate.
- the substrate including the semi-cured resin layer or the thermo plastic resin layer is prepared.
- the substrate in which the rigid substrate (the cured resin layer or the metal plate) is put between two semi-cured resin layers or two thermo plastic resin layer is employed preferably.
- the through holes passing through the substrate are formed and then the conductive parts (metal posts) are inserted thereinto.
- the semi-cured resin layers or the thermo plastic resin layers of the substrate are cured while causing to flow by applying the heat and the pressure, and thus the clearances between the through holes of the core substrate and the conductive parts are filled with the resin. Therefore, the conductive parts are fixed completely in the core substrate. Then, the wiring patterns connected mutually via the conductive parts are formed on both surface sides of the core substrate respectively.
- the clearances between the through holes of the substrate and the conductive parts are filled readily with the semi-cured resin layers that are caused to flow. Therefore, the wiring patterns can be connected electrically to the conductive parts with good reliability, and thus production yield and reliability of the wiring substrate can be improved.
- the resin layer is made to flow and is formed on the upper surfaces and the lower surfaces of the conductive parts, and the step of removing the resin layer on the upper surface and the lower surface of the conductive parts is further provided before the step of forming the wiring pattern.
- the step of removing the projected portions of the conductive parts projecting from the substrate to planarize is further provided after the step of filling the clearance between the through hole and the conductive parts with the resin layer (before the step of forming the wiring pattern).
- the coaxial type conductive parts having the structure in which the outer peripheral portion of the metal post is covered with the insulator may be employed as the conductive parts.
- the metal plate in addition to the cured resin layer, the metal plate may be employed as the rigid substrate constituting the substrate.
- the wiring patterns on both surface sides of the core substrate can be connected mutually via the conductive parts with good reliability without any disadvantage by inserting the conductive parts into the through holes in the core substrate.
- FIGS. 1A to 1 F are sectional views showing a method of manufacturing a wiring substrate in the prior art
- FIGS. 2A to 2 D are sectional views showing another method of manufacturing a wiring substrate in the prior art
- FIG. 3 is a fragmental enlarged sectional view showing a behavior between a through hole in a core substrate and a metal post in an enlarged fashion;
- FIGS. 4A to 4 H are sectional views showing a method of manufacturing a wiring substrate according to a first embodiment of the present invention
- FIG. 5 is a sectional view showing a wiring substrate according to a variation 1 of the first embodiment of the present invention.
- FIG. 6 is a sectional view showing a wiring substrate according to a variation 2 of the first embodiment of the present invention.
- FIGS. 7A to 7 H are sectional views showing a method of manufacturing a wiring substrate according to a second embodiment of the present invention.
- FIG. 8 is a sectional view showing a wiring substrate according to a variation 1 of the second embodiment of the present invention.
- FIG. 9 is a sectional view showing a wiring substrate according to a variation 2 of the second embodiment of the present invention.
- FIGS. 4A to 4 H are sectional views showing sequentially a method of manufacturing a wiring substrate according to a first embodiment of the present invention.
- a core substrate 10 such as shown in FIG. 4A is prepared.
- the core substrate 10 is composed to have a three-layered structure containing a semi-cured resin layer, and is composed of a cured resin layer 12 arranged in the middle portion, a first semi-cured resin layer 14 formed on an upper surface of the cured resin layer 12 , and a second semi-cured resin layer 16 formed on a lower surface of the cured resin layer 12 .
- a thickness of the core substrate 10 is 0.4 to 0.8 mm in total, for example.
- thermo plastic resin layers may be employed instead of the first semi-cured resin layer 14 and the second semi-cured resin layer 16 .
- the prepreg made of the carbon fiber, the glass fiber, the aramid fiber, or the like is impregnated with a thermosetting resin (epoxy resin, or the like) is preferably employed.
- the cured resin layer 12 is a rigid substrate whose resin has already been completely cured.
- the first and second semi-cured resin layers 14 , 16 are in a semi-cured condition (B-stage) in this step, and are completely cured by the annealing applied in the later steps.
- the resins containing various fibers are employed as the cured resin layer 12 and the first and second semi-cured resin layers 14 , 16 . But resins not containing the above fibers may be employed. Alternately, the semi-cured resin layers may be employed as the core substrate 10 as a whole.
- the metal plate made of copper (Cu), nickel (Ni), aluminum (Al), or the like may be employed to make the core substrate 10 have the rigidity.
- through holes 10 x passing through the core substrate 10 are formed by the punching.
- a diameter of the through hole is set to 0.15 to 0.35 mm and also a pitch between the through holes is set to 300 to 1250 ⁇ m, for example.
- conductive parts 20 inserted into the through holes 10 x of the core substrate 10 are prepared.
- a metal post obtained by cutting a metal wire made of copper (Cu), nickel (Ni), solder, or their alloy into a predetermined length is preferably employed.
- a coaxial type conductive parts made of the metal post whose outer peripheral portion is covered with an insulator is employed to prevent an electrical short-circuit.
- the conductive parts 20 are inserted into the through holes 10 x of the core substrate 10 .
- a length of the conductive parts 20 in the insertion direction is appropriately adjusted to meet a thickness of the core substrate 10 , and is set to 0.3 to 0.9 mm, for example.
- the length of the conductive parts 20 in the insertion direction is shorter than the thickness of the core substrate 10
- the conductive parts 20 are temporarily fixed to the through holes 10 x , nevertheless a clearance is produced between the through hole 10 ⁇ and the conductive parts 20 , as explained in FIG. 3 in the prior art.
- an upper surface and a lower surface of the conductive parts 20 are arranged in a state that these surfaces are positioned lower than an upper surface of the first semi-cured resin layer 14 and a lower surface of the second semi-cured resin layer 16 respectively.
- the method of inserting the conductive parts 20 into the through holes 10 x of the core substrate 10 is employed. Therefore, the desmear process or the plating process is not needed after the through holes 10 x are formed, and thus the wet processing step in which a burden is imposed on the process management can be reduced.
- the resultant structure in FIG. 4C is pressurized while heating (thermally pressed) in the vacuum atmosphere (or the low-pressure atmosphere).
- the first and second semi-cured resin layers 14 , 16 are completely cured.
- the thermal press conditions the conditions of a heating temperature: 200° C., a pushing force: 2.5 MPa, and a process time: 2 hour are preferably employed.
- the first and second semi-cured resin layers 14 , 16 are cured to flow to the through hole 10 x side respectively and then the clearances between the through holes 10 ⁇ and the conductive parts 20 are filled with the resin.
- the conductive parts 20 are fixed completely in the core substrate 10 .
- the resin is made to flow onto upper surfaces and lower surfaces of the conductive parts 20 , and then the conductive parts 20 are covered with the resin layer.
- core substrate 10 becomes the cured resin layer over the whole.
- thermo plastic resin layers are employed instead of the first and second semi-cured resin layers 14 , 16 , the thermo plastic resin layers are re-cured to flow and the clearances between the through holes 10 ⁇ and the conductive parts 20 are filled with the resin similarly.
- both surface sides of the core substrate 10 may be planarized completely by polishing both surface sides of the core substrate 10 until the upper surfaces and the lower surfaces of the conductive parts 20 are exposed.
- a seed layer 22 made of Cu, or the like is formed on both surfaces of the core substrate 10 , into which the conductive parts 20 are inserted, respectively.
- the seed layer 22 is formed of the electroless plating, the PVD method, or the CVD method.
- a metal layer 24 is formed on the seed layer 22 on both surface sides of the core substrate 10 by the electroplating utilizing the seed layer 22 as the plating-power feeding layer respectively.
- the metal layer 24 is made of Cu, or the like, and is formed with a film thickness of 10 to 25 ⁇ m by the electroless plating, a current density of which is set to about 1 A/dm 2 .
- the clearances between the through holes 10 ⁇ and the conductive parts 20 are buried with the first and second semi-cured resin layers 14 , 16 after the conductive parts 20 are inserted into the through holes 10 x of the core substrate 10 . Therefore, no area in which the seed layer 22 and the metal layer 24 are not formed is caused, and the seed layer 22 and the metal layer 24 are connected electrically to the conductive parts 20 with good reliability, and are formed.
- the metal layer 24 and the seed layer 22 on both surface sides of the core substrate 10 are patterned by the photolithography and the etching.
- wiring patterns 26 connected mutually via the conductive parts 20 are formed on both surfaces of the core substrate 10 respectively.
- the wiring patterns 26 may be formed by another method such as the semi-additive process, or the like.
- the wiring substrate according to the first embodiment of the present invention can be obtained.
- n-layered (n is an integer that is 1 or more) built-up wiring layer connected to the wiring patterns 26 is formed on one surface or both surfaces of the wiring substrate of the present embodiment.
- the electronic parts such as a semiconductor chip, or the like is mounted onto the connection portions of the uppermost wiring patterns on one surface side of the core substrate 10 , and then the connection portions of the uppermost wiring patterns on the other surface side of the core substrate 10 are connected electrically to the mother board.
- the core substrate 10 having the structure in which the cured resin layer 12 is put between the first semi-cured resin layer 14 and the second semi-cured resin layer 16 is prepared. Then, the through holes 10 x passing through the core substrate 10 are formed, and then the conductive parts 20 whose length is shorter than the thickness of the core substrate 10 are inserted into the through holes 10 x.
- the first and second semi-cured resin layers 14 , 16 of the core substrate 10 are cured while causing to flow by the thermal press.
- the clearances between the through holes 10 x of the core substrate 10 and the conductive parts 20 are filled with the resin, and thus the conductive parts 20 are fixed completely in the core substrate 10 .
- the resin layers that are made to flow on the upper surfaces and the lower surfaces of the conductive parts 20 are removed, and thus the upper surfaces and the lower surfaces of the conductive parts 20 are exposed.
- the wiring patterns 26 connected mutually via the conductive parts 20 are formed on both surface sides of the core substrate 10 respectively.
- the clearances between the through holes 10 ⁇ and the conductive parts 20 are filled readily with the first and second semi-cured resin layers 14 , 16 . Therefore, the wiring patterns 26 can be connected to the conductive parts 20 with good reliability, and thus production yield and reliability of the wiring substrate can be improved.
- a wiring substrate according to a variation 1 of the first embodiment is shown in FIG. 5 .
- a coaxial type conductive parts 30 composed of a metal post 30 a and an insulator 30 b coated on an outer peripheral portion of the metal post 30 a is employed.
- the insulator 30 b an epoxy resin, a polyimide resin, a polyamide resin, or the like is preferably employed.
- the overall core substrate 10 is formed of the cured resin layer finally by the thermal press, and the coaxial type conductive parts 30 are inserted into the through holes 10 x of the core substrate 10 .
- the core substrate having the above structure in which the cured resin layer 12 is put between the first semi-cured resin layer 14 and the second semi-cured resin layer 16 is employed as the core substrate 10 .
- the wiring substrate can be manufactured by the same manufacturing method as the first embodiment after the coaxial type conductive parts 30 are inserted into the through holes 10 x of the core substrate 10 .
- FIG. 6 A wiring substrate according to a variation 2 of the first embodiment is shown in FIG. 6 .
- the core substrate 10 has such a structure that a metal plate 13 is put between a first cured resin layer 14 a and a second cured resin layer 16 a finally by the thermal press, and the coaxial type conductive parts 30 are inserted into the through holes 10 x of the core substrate 10 .
- the core substrate having the structure in which the metal plate 13 is put between the first semi-cured resin layer 14 and the second semi-cured resin layer 16 as mentioned above is employed as the core substrate 10 .
- the wiring substrate can be manufactured by the same manufacturing method as the first embodiment after the coaxial type conductive parts 30 having the above structure are inserted into the through holes 10 x of the core substrate 10 .
- the metal plate 13 is present in the inside of the core substrate 10 , but the electrical short-circuit between the coaxial type conductive parts 30 can be prevented by the insulator 30 b coated on the outer peripheral portion of the coaxial type conductive parts 30 .
- FIGS. 7A to 7 H are sectional views showing a method of manufacturing a wiring substrate according to a second embodiment of the present invention sequentially.
- a difference of the second embodiment from the first embodiment resides in that the conductive parts whose length is longer than the thickness of the core substrate is employed.
- detailed explanation of the same steps as those in the first embodiment will be omitted herein.
- the through holes 10 x are formed in the core substrate 10 having the structure in which the cured resin layer 12 is put between the first semi-cured resin layer 14 and the second semi-cured resin layer 16 .
- the conductive parts 20 are inserted into the through holes 10 x of the core substrate 10 .
- the conductive parts whose length in the insertion direction is longer than the thickness of the core substrate 10 is employed as the conductive parts 20 , and also the conductive parts 20 are arranged to have a projected portion 20 a that is projected from exposed surfaces of the first semi-cured resin layer 14 and the second semi-cured resin layer 16 respectively.
- the clearance is produced between the through holes 10 x of the core substrate 10 and the conductive parts 20 in this step.
- the core substrate 10 is pressurized while heating (thermally pressed) in the vacuum atmosphere (or the low-pressure atmosphere).
- the first and second semi-cured resin layers 14 , 16 of the core substrate 10 are completely cured to flow to the through hole 10 x side respectively, and the clearances between the through holes 10 ⁇ and the conductive parts 20 are filled with the resin.
- the conductive parts 20 are fixed completely in the core substrate 10 .
- the core substrate 10 becomes the cured resin layer over the whole.
- the projected portions 20 a of the conductive parts 20 (e.g., Cu posts) projected from both surface sides of the core substrate 10 are removed by the polishing or the etching.
- the upper surfaces and the lower surfaces of the conductive parts 20 are planarized to constitute the almost coplanar surfaces with the upper surface and the lower surface of the core substrate 10 respectively.
- the buffing the tape polishing, or the CMP (Chemical Mechanical Polishing) is employed.
- CMP Chemical Mechanical Polishing
- iron (III) chloride aqueous solution copper (II) chloride aqueous solution, or ammonium peroxodisulfate aqueous solution is employed as the etchant.
- the conductive parts 20 are fixed completely to the core substrate 10 . Therefore, in polishing the projected portions 20 a of the conductive parts 20 , there is no possibility that the conductive parts 20 drop out from the core substrate 10 , and thus the projected portions 20 a of the conductive parts 20 can be polished stably. Also, since no clearance between the conductive parts 20 and the core substrate 10 is present, there is no possibility that the etchant sinks into the clearance and also unnecessary etching of the conductive parts 20 can be prevented even when the projected portions 20 a of the conductive parts 20 are removed by the etching.
- the seed layer 22 is formed on both surfaces of the core substrate 10 , into which the conductive parts 20 are inserted, respectively.
- the metal layer 24 is formed on the seed layer 22 on both surface sides of the core substrate 10 by the electroplating utilizing the seed layer 22 as the plating-power feeding layer respectively.
- the metal layer 24 and the seed layer 22 on both surface sides of the core substrate 10 are patterned.
- the wiring patterns 26 connected mutually via the conductive parts 20 are formed on both surfaces of the core substrate 10 respectively.
- the second embodiment can achieve the advantages similar to the first embodiment.
- both surfaces of the core substrate can be planarized without any disadvantage.
- the wiring patterns 26 connected mutually via the conductive parts 20 can be formed on both surfaces of the core substrate 10 with good reliability respectively.
- a wiring substrate according to a variation 1 of the second embodiment is shown in FIG. 8 .
- the overall core substrate 10 is formed of the cured resin layer finally by the thermal press, and the coaxial type conductive parts 30 are inserted into the through holes 10 x of the core substrate 10 .
- the core substrate having the above structure in which the cured resin layer 12 is put between the first semi-cured resin layer 14 and the second semi-cured resin layer 16 is employed as the core substrate 10 .
- the wiring substrate can be manufactured by the same manufacturing method as the second embodiment after the coaxial type conductive parts 30 similar to the variation of the first embodiment are inserted into the through holes 10 x of the core substrate 10 .
- the metal posts 30 a and the insulators 30 b are polished simultaneously and planarized.
- FIG. 9 A wiring substrate according to a variation 2 of the second embodiment is shown in FIG. 9 .
- the core substrate 10 has such a structure that the metal plate 13 is put between the first cured resin layer 14 a and the second cured resin layer 16 a finally by the thermal press, and the coaxial type conductive parts 30 are inserted into the through holes 10 x of the core substrate 10 .
- the core substrate having the structure in which the metal plate 13 is put between the first semi-cured resin layer 14 and the second semi-cured resin layer 16 as mentioned above is employed as the core substrate 10 .
- the wiring substrate can be manufactured by the same manufacturing method as the second embodiment after the coaxial type conductive parts 30 are inserted into the through holes 10 x of the core substrate 10 .
- the metal plate 13 is present in the inside of the core substrate 10 , but the electrical short-circuit between the coaxial type conductive parts 30 can be prevented by the insulator 30 b coated on the outer peripheral portion of the coaxial type conductive parts 30 .
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
- This application is based on and claims priority of Japanese Patent Application No. 2004-174969 filed on Jun. 14, 2004, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a method of manufacturing a wiring substrate and, more particularly, a method of manufacturing a wiring substrate having a structure that enable conduction of both surface sides of a core substrate via through holes provided in the core substrate.
- 2. Description of the Related Art
- In the prior art, there is the wiring substrate having the structure in which the wiring patterns formed on both surface sides of the core substrate are connected mutually via the conductors provided in the through holes in the core substrate.
- As the method of manufacturing such wiring substrate, as shown in
FIG. 1A , at first throughholes 100 x are formed in acore substrate 100 made of a glass epoxy resin, or the like, and then insides of the throughholes 100 x are cleaned by a desmear process using a permanganic acid, or the like. Then, as shown inFIG. 1B , a seed layer (not shown) is formed on both surfaces of thecore substrate 100 and side surfaces of the throughholes 100 x by the electroless plating, and then a metal layer (not shown) is formed on the seed layer by the electroless plating utilizing the seed layer as a plating-power feeding layer, and thus firstconductive layers 102 are obtained. Accordingly, both surface sides of thecore substrate 100 can be brought into a conductive condition via the firstconductive layer 102 provided in the throughholes 100 x. At this time, cavity is left in the throughholes 100 x in thecore substrate 100 respectively. - Then, as shown in
FIG. 1C , aninsulating resin body 104 is filled in the cavities of the throughholes 100 x. Then, as shown inFIG. 1D , projected portions of theinsulating resin bodies 104 projected from the firstconductive layer 102 are polished on both surface sides of thecore substrate 100 respectively. Thus, an upper surface and a lower surface of the insulatingresin body 104 are planarized to get substantially coplanar surfaces with exposed surfaces of the firstconductive layers 102 on the upper side and the lower side of thecore substrate 100 respectively. - Then, as shown in
FIG. 1E , a resultant structure inFIG. 1D is cleaned by applying the desmear process thereto, then a seed layer (not shown) is formed on the firstconductive layer 102 on both surface sides of thecore substrate 100 by the electroless plating respectively, and then a metal layer (not shown) is formed on the seed layer by the electroplating utilizing the seed layer as the plating-power feeding layer, and thus a secondconductive layer 106 is obtained on both surface sides respectively. - Then, as shown in
FIG. 1F ,wiring patterns 108 each composed of the first and second 102, 106 are formed on both surfaces by patterning the secondconductive layers conductive layer 106 and the firstconductive layer 102. In this manner, thewiring patterns 108 on both surface sides of thecore substrate 100 are connected mutually via the firstconductive layers 102 in the throughholes 100 x in thecore substrate 100. - In the above method of manufacturing the wiring substrate, the steps of the desmear process, the electroless plating, and the electroplating are required in the case of forming the first
conductive layers 102 for enabling conduction of both surface sides of the core substrate mutually, in the throughholes 100 x respectively. As a result, such problems exist that the manufacturing steps become complicated because many manufacturing steps are needed, and the heavy burden of the chemicals preparation and the liquid waste processing is imposed. - In order to overcome such problems, instead of the process of forming the conductive layer in the through holes of the core substrate by the plating, there is the manufacturing method of inserting the metal posts into the through holes.
- That is, as shown in
FIG. 2A andFIG. 2B , the throughholes 100 x are formed in thecore substrate 100, and thenmetal posts 110 are inserted into the throughholes 100 x. Then, as shown inFIG. 2C andFIG. 2D , aconductive layer 112 is formed on both surfaces of thecore substrate 100 by the electroless plating and the electroplating respectively, and thenwiring patterns 114 are formed by patterning theconductive layer 112 on both surfaces respectively. Accordingly, thewiring patterns 114 formed on both surfaces of thecore substrate 100 respectively are connected mutually via themetal posts 110 in the throughholes 100 x. - The wiring substrate having the structure in which the metal posts are inserted into the through holes provided in the core substrate is set forth in Patent Literature 1 (Patent Application Publication (KOKAI) 2002-289999), Patent Literature 2 (Patent Application Publication (KOKAI) 2003-220595), and Patent Literature 3 (Patent Application Publication (KOKAI) 2001-352166), for example.
-
FIG. 3 is an enlarged sectional view showing a behavior between thethrough hole 100 x in thecore substrate 100 and themetal post 110 inFIG. 2B . - As shown in
FIG. 3 , in the case of inserting themetal post 110 into thethrough hole 100 x in thecore substrate 100, a clearance G is ready to occur between the throughhole 100 x and themetal post 110. This is because it is difficult to reconcile an inner diameter of the throughhole 100 x with an outer diameter of themetal post 110 perfectly and also the defects such that themetal post 110 is bent partially upon inserting themetal post 110 into the throughhole 100 x, and the like are caused. - When the clearance occurs between the through
hole 100 x and themetal post 110, the plating is not partially applied owing to the influence of the clearance G in forming thewiring patterns 114 on both surface side of thecore substrate 100, and thus there is such a possibility that thewiring patterns 114 are disconnected. - Also, in case the top end portions of the
metal posts 110 are projected excessively from thecore substrate 100, the projected portions of themetal posts 110 must be removed by the polishing or the etching to get the flat surface. In the prior art, since themetal posts 110 are not perfectly fixed to the throughholes 100 x, sometimes themetal posts 110 drop out at the time of polishing, or the etchant sinks into the clearance to etch unnecessarily themetal posts 110 at the time of etching. - As described above, in the method of inserting the
metal posts 110 into the throughholes 100 x of thecore substrate 100 according to the prior art, the disadvantages such as the connection failure between themetal posts 110 and thewiring patterns 114, and the like are ready to generate and thus it is extremely difficult to manufacture the highly-reliable wiring substrate at high yield. - It is an object of the present invention to provide a method of manufacturing a wiring substrate, capable of connecting mutually wiring patterns on both surface sides of a core substrate with good reliability without any disadvantage by inserting conductive parts (metal posts) into through holes in the core substrate.
- A method of manufacturing a wiring substrate of the present invention, comprises the steps of preparing a substrate including a semi-cured resin layer or a thermo plastic resin layer; forming a through hole that passes through the substrate; inserting a conductive parts in the through hole; curing the semi-cured resin layer or the thermo plastic resin layer in a state that the resin layer is made to flow by applying a heat and a pressure to the substrate, and filling a clearance between the through hole and the conductive parts with the resin layer; and forming a wiring pattern, which is connected mutually via the conductive parts, on both surface sides of the substrate.
- In the present invention, first the substrate including the semi-cured resin layer or the thermo plastic resin layer is prepared. As such substrate, the substrate in which the rigid substrate (the cured resin layer or the metal plate) is put between two semi-cured resin layers or two thermo plastic resin layer is employed preferably. Then, the through holes passing through the substrate are formed and then the conductive parts (metal posts) are inserted thereinto.
- Then, the semi-cured resin layers or the thermo plastic resin layers of the substrate are cured while causing to flow by applying the heat and the pressure, and thus the clearances between the through holes of the core substrate and the conductive parts are filled with the resin. Therefore, the conductive parts are fixed completely in the core substrate. Then, the wiring patterns connected mutually via the conductive parts are formed on both surface sides of the core substrate respectively.
- In this manner, by employing the method of inserting the conductive parts to the through holes of the substrate, since manufacturing steps can be reduced rather than the case where the conductive layer is formed in the through holes of the core substrate by the plating, a reduction in production cost can be attained. Also, since the step of applying the chemicals can be reduced, a burden on the chemicals management can be reduced remarkably.
- Further, the clearances between the through holes of the substrate and the conductive parts are filled readily with the semi-cured resin layers that are caused to flow. Therefore, the wiring patterns can be connected electrically to the conductive parts with good reliability, and thus production yield and reliability of the wiring substrate can be improved.
- In the above invention, when a length of the conductive parts in an insertion direction is shorter than a thickness of the substrate, the resin layer is made to flow and is formed on the upper surfaces and the lower surfaces of the conductive parts, and the step of removing the resin layer on the upper surface and the lower surface of the conductive parts is further provided before the step of forming the wiring pattern.
- Also, in the above invention, when a length of the conductive parts in an insertion direction is longer than a thickness of the substrate, the step of removing the projected portions of the conductive parts projecting from the substrate to planarize is further provided after the step of filling the clearance between the through hole and the conductive parts with the resin layer (before the step of forming the wiring pattern).
- Also, in the above invention, the coaxial type conductive parts having the structure in which the outer peripheral portion of the metal post is covered with the insulator may be employed as the conductive parts. In this case, in addition to the cured resin layer, the metal plate may be employed as the rigid substrate constituting the substrate.
- As described above, according to the present invention, the wiring patterns on both surface sides of the core substrate can be connected mutually via the conductive parts with good reliability without any disadvantage by inserting the conductive parts into the through holes in the core substrate.
-
FIGS. 1A to 1F are sectional views showing a method of manufacturing a wiring substrate in the prior art; -
FIGS. 2A to 2D are sectional views showing another method of manufacturing a wiring substrate in the prior art; -
FIG. 3 is a fragmental enlarged sectional view showing a behavior between a through hole in a core substrate and a metal post in an enlarged fashion; -
FIGS. 4A to 4H are sectional views showing a method of manufacturing a wiring substrate according to a first embodiment of the present invention; -
FIG. 5 is a sectional view showing a wiring substrate according to a variation 1 of the first embodiment of the present invention; -
FIG. 6 is a sectional view showing a wiring substrate according to a variation 2 of the first embodiment of the present invention; -
FIGS. 7A to 7H are sectional views showing a method of manufacturing a wiring substrate according to a second embodiment of the present invention; -
FIG. 8 is a sectional view showing a wiring substrate according to a variation 1 of the second embodiment of the present invention; and -
FIG. 9 is a sectional view showing a wiring substrate according to a variation 2 of the second embodiment of the present invention. - Embodiments of the present invention will be explained with reference to the accompanying drawings hereinafter.
-
FIGS. 4A to 4H are sectional views showing sequentially a method of manufacturing a wiring substrate according to a first embodiment of the present invention. - In the method of manufacturing the wiring substrate according to the first embodiment of the present invention, first, a
core substrate 10 such as shown inFIG. 4A is prepared. Thecore substrate 10 is composed to have a three-layered structure containing a semi-cured resin layer, and is composed of a curedresin layer 12 arranged in the middle portion, a firstsemi-cured resin layer 14 formed on an upper surface of the curedresin layer 12, and a secondsemi-cured resin layer 16 formed on a lower surface of the curedresin layer 12. A thickness of thecore substrate 10 is 0.4 to 0.8 mm in total, for example. - In this case, thermo plastic resin layers may be employed instead of the first
semi-cured resin layer 14 and the secondsemi-cured resin layer 16. - As the material of respective layers constituting the
core substrate 10, the prepreg made of the carbon fiber, the glass fiber, the aramid fiber, or the like is impregnated with a thermosetting resin (epoxy resin, or the like) is preferably employed. The curedresin layer 12 is a rigid substrate whose resin has already been completely cured. The first and second semi-cured resin layers 14, 16 are in a semi-cured condition (B-stage) in this step, and are completely cured by the annealing applied in the later steps. - In the present embodiment, from a viewpoint of give rigidity to the
core substrate 10, the resins containing various fibers are employed as the curedresin layer 12 and the first and second semi-cured resin layers 14, 16. But resins not containing the above fibers may be employed. Alternately, the semi-cured resin layers may be employed as thecore substrate 10 as a whole. - In addition, instead of the cured
resin layer 12, the metal plate made of copper (Cu), nickel (Ni), aluminum (Al), or the like may be employed to make thecore substrate 10 have the rigidity. - Then, as shown in
FIG. 4B , throughholes 10 x passing through thecore substrate 10 are formed by the punching. A diameter of the through hole is set to 0.15 to 0.35 mm and also a pitch between the through holes is set to 300 to 1250 μm, for example. - Then, as shown in
FIG. 4C ,conductive parts 20 inserted into the throughholes 10 x of thecore substrate 10 are prepared. As theconductive parts 20, a metal post obtained by cutting a metal wire made of copper (Cu), nickel (Ni), solder, or their alloy into a predetermined length is preferably employed. As explained in variations described later, in case the metal plate is employed instead of the curedresin layer 12 of thecore substrate 10, a coaxial type conductive parts made of the metal post whose outer peripheral portion is covered with an insulator is employed to prevent an electrical short-circuit. - Then, the
conductive parts 20 are inserted into the throughholes 10 x of thecore substrate 10. A length of theconductive parts 20 in the insertion direction is appropriately adjusted to meet a thickness of thecore substrate 10, and is set to 0.3 to 0.9 mm, for example. - In the first embodiment, the case where the length of the
conductive parts 20 in the insertion direction is shorter than the thickness of thecore substrate 10 will be explained by way of example hereunder. At this time, theconductive parts 20 are temporarily fixed to the throughholes 10 x, nevertheless a clearance is produced between the throughhole 10× and theconductive parts 20, as explained inFIG. 3 in the prior art. In addition, an upper surface and a lower surface of theconductive parts 20 are arranged in a state that these surfaces are positioned lower than an upper surface of the firstsemi-cured resin layer 14 and a lower surface of the secondsemi-cured resin layer 16 respectively. - In the present embodiment, the method of inserting the
conductive parts 20 into the throughholes 10 x of thecore substrate 10 is employed. Therefore, the desmear process or the plating process is not needed after the throughholes 10 x are formed, and thus the wet processing step in which a burden is imposed on the process management can be reduced. - Then, as shown in
FIG. 4D , the resultant structure inFIG. 4C is pressurized while heating (thermally pressed) in the vacuum atmosphere (or the low-pressure atmosphere). Thus, the first and second semi-cured resin layers 14, 16 are completely cured. As an example of the thermal press conditions, the conditions of a heating temperature: 200° C., a pushing force: 2.5 MPa, and a process time: 2 hour are preferably employed. - At this time, as shown in
FIG. 4D andFIG. 4E , the first and second semi-cured resin layers 14, 16 are cured to flow to the throughhole 10 x side respectively and then the clearances between the throughholes 10× and theconductive parts 20 are filled with the resin. Thus, theconductive parts 20 are fixed completely in thecore substrate 10. Also, the resin is made to flow onto upper surfaces and lower surfaces of theconductive parts 20, and then theconductive parts 20 are covered with the resin layer. As a result,core substrate 10 becomes the cured resin layer over the whole. - In the case that the thermo plastic resin layers are employed instead of the first and second semi-cured resin layers 14, 16, the thermo plastic resin layers are re-cured to flow and the clearances between the through
holes 10× and theconductive parts 20 are filled with the resin similarly. - Then, as shown in
FIG. 4F , the resin layers on the upper surfaces and the lower surfaces of theconductive parts 20 are removed respectively, and thus the upper surfaces and the lower surfaces of theconductive parts 20 are exposed. In this event, the resin layers on the upper surfaces and the lower surfaces of theconductive parts 20 are removed by any one of the desmear process using a permanganic acid, or the like, the laser process, and the plasma desmear process using a CF4/O2 gas, or the like, or the process using these methods in combination. Otherwise, both surface sides of thecore substrate 10 may be planarized completely by polishing both surface sides of thecore substrate 10 until the upper surfaces and the lower surfaces of theconductive parts 20 are exposed. - Then, as shown in
FIG. 4G , aseed layer 22 made of Cu, or the like is formed on both surfaces of thecore substrate 10, into which theconductive parts 20 are inserted, respectively. Theseed layer 22 is formed of the electroless plating, the PVD method, or the CVD method. Then, ametal layer 24 is formed on theseed layer 22 on both surface sides of thecore substrate 10 by the electroplating utilizing theseed layer 22 as the plating-power feeding layer respectively. Themetal layer 24 is made of Cu, or the like, and is formed with a film thickness of 10 to 25 μm by the electroless plating, a current density of which is set to about 1 A/dm2. - In the present embodiment, the clearances between the through
holes 10× and theconductive parts 20 are buried with the first and second semi-cured resin layers 14, 16 after theconductive parts 20 are inserted into the throughholes 10 x of thecore substrate 10. Therefore, no area in which theseed layer 22 and themetal layer 24 are not formed is caused, and theseed layer 22 and themetal layer 24 are connected electrically to theconductive parts 20 with good reliability, and are formed. - Then, as shown in
FIG. 4H , themetal layer 24 and theseed layer 22 on both surface sides of thecore substrate 10 are patterned by the photolithography and the etching. Thus,wiring patterns 26 connected mutually via theconductive parts 20 are formed on both surfaces of thecore substrate 10 respectively. In this case, thewiring patterns 26 may be formed by another method such as the semi-additive process, or the like. - From the above, the wiring substrate according to the first embodiment of the present invention can be obtained. There may be employed such a mode that an n-layered (n is an integer that is 1 or more) built-up wiring layer connected to the
wiring patterns 26 is formed on one surface or both surfaces of the wiring substrate of the present embodiment. Then, for example, the electronic parts such as a semiconductor chip, or the like is mounted onto the connection portions of the uppermost wiring patterns on one surface side of thecore substrate 10, and then the connection portions of the uppermost wiring patterns on the other surface side of thecore substrate 10 are connected electrically to the mother board. - As described above, in the method of manufacturing the wiring substrate according to the first embodiment, first, the
core substrate 10 having the structure in which the curedresin layer 12 is put between the firstsemi-cured resin layer 14 and the secondsemi-cured resin layer 16 is prepared. Then, the throughholes 10 x passing through thecore substrate 10 are formed, and then theconductive parts 20 whose length is shorter than the thickness of thecore substrate 10 are inserted into the throughholes 10 x. - Then, the first and second semi-cured resin layers 14, 16 of the
core substrate 10 are cured while causing to flow by the thermal press. Thus, the clearances between the throughholes 10 x of thecore substrate 10 and theconductive parts 20 are filled with the resin, and thus theconductive parts 20 are fixed completely in thecore substrate 10. - Then, the resin layers that are made to flow on the upper surfaces and the lower surfaces of the
conductive parts 20 are removed, and thus the upper surfaces and the lower surfaces of theconductive parts 20 are exposed. Then, thewiring patterns 26 connected mutually via theconductive parts 20 are formed on both surface sides of thecore substrate 10 respectively. - In this manner, in the method of manufacturing the wiring substrate according to the present embodiment, since manufacturing steps can be reduced rather than the case where the conductive layer is formed in the through
holes 10 x of thecore substrate 10 by the plating, a reduction in production cost can be attained. Also, since the step of applying the chemicals can be reduced, a burden concerning the chemicals management can be reduced remarkably. - Besides, the clearances between the through
holes 10× and theconductive parts 20 are filled readily with the first and second semi-cured resin layers 14, 16. Therefore, thewiring patterns 26 can be connected to theconductive parts 20 with good reliability, and thus production yield and reliability of the wiring substrate can be improved. - Next, variations of the first embodiment will be explained hereunder.
- A wiring substrate according to a variation 1 of the first embodiment is shown in
FIG. 5 . As shown inFIG. 5 , in the variation 1, instead of theconductive parts 20 formed of the metal post, a coaxial typeconductive parts 30 composed of ametal post 30 a and aninsulator 30 b coated on an outer peripheral portion of themetal post 30 a is employed. As theinsulator 30 b, an epoxy resin, a polyimide resin, a polyamide resin, or the like is preferably employed. - In the variation 1, the
overall core substrate 10 is formed of the cured resin layer finally by the thermal press, and the coaxial typeconductive parts 30 are inserted into the throughholes 10 x of thecore substrate 10. In the variation 1, the core substrate having the above structure in which the curedresin layer 12 is put between the firstsemi-cured resin layer 14 and the secondsemi-cured resin layer 16 is employed as thecore substrate 10. Then, the wiring substrate can be manufactured by the same manufacturing method as the first embodiment after the coaxial typeconductive parts 30 are inserted into the throughholes 10 x of thecore substrate 10. - A wiring substrate according to a variation 2 of the first embodiment is shown in
FIG. 6 . As shown inFIG. 6 , in the variation 2, thecore substrate 10 has such a structure that ametal plate 13 is put between a first curedresin layer 14 a and a second curedresin layer 16 a finally by the thermal press, and the coaxial typeconductive parts 30 are inserted into the throughholes 10 x of thecore substrate 10. In the variation 2, first, the core substrate having the structure in which themetal plate 13 is put between the firstsemi-cured resin layer 14 and the secondsemi-cured resin layer 16 as mentioned above is employed as thecore substrate 10. Then, the wiring substrate can be manufactured by the same manufacturing method as the first embodiment after the coaxial typeconductive parts 30 having the above structure are inserted into the throughholes 10 x of thecore substrate 10. - In the variation 2, the
metal plate 13 is present in the inside of thecore substrate 10, but the electrical short-circuit between the coaxial typeconductive parts 30 can be prevented by theinsulator 30 b coated on the outer peripheral portion of the coaxial typeconductive parts 30. -
FIGS. 7A to 7H are sectional views showing a method of manufacturing a wiring substrate according to a second embodiment of the present invention sequentially. - A difference of the second embodiment from the first embodiment resides in that the conductive parts whose length is longer than the thickness of the core substrate is employed. In the second embodiment, detailed explanation of the same steps as those in the first embodiment will be omitted herein.
- In the method of manufacturing the wiring substrate according to the second embodiment of the present invention, as shown in
FIG. 7A andFIG. 7B , like the first embodiment, the throughholes 10 x are formed in thecore substrate 10 having the structure in which the curedresin layer 12 is put between the firstsemi-cured resin layer 14 and the secondsemi-cured resin layer 16. - Then, as shown in
FIG. 7C , theconductive parts 20 are inserted into the throughholes 10 x of thecore substrate 10. In the second embodiment, the conductive parts whose length in the insertion direction is longer than the thickness of thecore substrate 10 is employed as theconductive parts 20, and also theconductive parts 20 are arranged to have a projectedportion 20 a that is projected from exposed surfaces of the firstsemi-cured resin layer 14 and the secondsemi-cured resin layer 16 respectively. Also, like the first embodiment, the clearance is produced between the throughholes 10 x of thecore substrate 10 and theconductive parts 20 in this step. - Then, as shown in
FIG. 7D , like the first embodiment, thecore substrate 10 is pressurized while heating (thermally pressed) in the vacuum atmosphere (or the low-pressure atmosphere). Thus, as shown inFIG. 7D andFIG. 7E , the first and second semi-cured resin layers 14, 16 of thecore substrate 10 are completely cured to flow to the throughhole 10 x side respectively, and the clearances between the throughholes 10× and theconductive parts 20 are filled with the resin. Thus, theconductive parts 20 are fixed completely in thecore substrate 10. As a result, thecore substrate 10 becomes the cured resin layer over the whole. - Then, as shown in
FIG. 7F , the projectedportions 20 a of the conductive parts 20 (e.g., Cu posts) projected from both surface sides of thecore substrate 10 are removed by the polishing or the etching. Thus, the upper surfaces and the lower surfaces of theconductive parts 20 are planarized to constitute the almost coplanar surfaces with the upper surface and the lower surface of thecore substrate 10 respectively. - When the polishing is employed, the buffing, the tape polishing, or the CMP (Chemical Mechanical Polishing) is employed. When the etching is employed, iron (III) chloride aqueous solution, copper (II) chloride aqueous solution, or ammonium peroxodisulfate aqueous solution is employed as the etchant.
- At this time, the
conductive parts 20 are fixed completely to thecore substrate 10. Therefore, in polishing the projectedportions 20 a of theconductive parts 20, there is no possibility that theconductive parts 20 drop out from thecore substrate 10, and thus the projectedportions 20 a of theconductive parts 20 can be polished stably. Also, since no clearance between theconductive parts 20 and thecore substrate 10 is present, there is no possibility that the etchant sinks into the clearance and also unnecessary etching of theconductive parts 20 can be prevented even when the projectedportions 20 a of theconductive parts 20 are removed by the etching. - Then, as shown in
FIG. 7G , like the first embodiment, theseed layer 22 is formed on both surfaces of thecore substrate 10, into which theconductive parts 20 are inserted, respectively. Then, themetal layer 24 is formed on theseed layer 22 on both surface sides of thecore substrate 10 by the electroplating utilizing theseed layer 22 as the plating-power feeding layer respectively. - Then, as shown in
FIG. 7H , like the first embodiment, themetal layer 24 and theseed layer 22 on both surface sides of thecore substrate 10 are patterned. Thus, thewiring patterns 26 connected mutually via theconductive parts 20 are formed on both surfaces of thecore substrate 10 respectively. - With the above the wiring substrate according to the first embodiment of the present invention can be obtained.
- The second embodiment can achieve the advantages similar to the first embodiment. In addition to this, even though the conductive parts whose length is longer than the thickness of the
core substrate 10 are employed as theconductive parts 20, both surfaces of the core substrate can be planarized without any disadvantage. Thus, thewiring patterns 26 connected mutually via theconductive parts 20 can be formed on both surfaces of thecore substrate 10 with good reliability respectively. - Next, variations of the second embodiment will be explained hereunder.
- A wiring substrate according to a variation 1 of the second embodiment is shown in
FIG. 8 . As shown inFIG. 8 , in the variation 1, theoverall core substrate 10 is formed of the cured resin layer finally by the thermal press, and the coaxial typeconductive parts 30 are inserted into the throughholes 10 x of thecore substrate 10. In the variation 1, the core substrate having the above structure in which the curedresin layer 12 is put between the firstsemi-cured resin layer 14 and the secondsemi-cured resin layer 16 is employed as thecore substrate 10. Then, the wiring substrate can be manufactured by the same manufacturing method as the second embodiment after the coaxial typeconductive parts 30 similar to the variation of the first embodiment are inserted into the throughholes 10 x of thecore substrate 10. - In the step of removing the projected portions of the coaxial type
conductive parts 30, the metal posts 30 a and theinsulators 30 b are polished simultaneously and planarized. - A wiring substrate according to a variation 2 of the second embodiment is shown in
FIG. 9 . As shown inFIG. 9 , in the variation 2, thecore substrate 10 has such a structure that themetal plate 13 is put between the first curedresin layer 14 a and the second curedresin layer 16 a finally by the thermal press, and the coaxial typeconductive parts 30 are inserted into the throughholes 10 x of thecore substrate 10. In the variation 2, first, the core substrate having the structure in which themetal plate 13 is put between the firstsemi-cured resin layer 14 and the secondsemi-cured resin layer 16 as mentioned above is employed as thecore substrate 10. Then, the wiring substrate can be manufactured by the same manufacturing method as the second embodiment after the coaxial typeconductive parts 30 are inserted into the throughholes 10 x of thecore substrate 10. - In the variation 2, like the variation 2 of the first embodiment, the
metal plate 13 is present in the inside of thecore substrate 10, but the electrical short-circuit between the coaxial typeconductive parts 30 can be prevented by theinsulator 30 b coated on the outer peripheral portion of the coaxial typeconductive parts 30.
Claims (10)
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| JP2004-174969 | 2004-06-14 | ||
| JP2004174969A JP4551135B2 (en) | 2004-06-14 | 2004-06-14 | Wiring board manufacturing method |
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| US20050277282A1 true US20050277282A1 (en) | 2005-12-15 |
| US7276438B2 US7276438B2 (en) | 2007-10-02 |
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| US11/135,350 Expired - Lifetime US7276438B2 (en) | 2004-06-14 | 2005-05-24 | Method of manufacturing wiring substrate |
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| US (1) | US7276438B2 (en) |
| JP (1) | JP4551135B2 (en) |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060012967A1 (en) * | 2002-04-01 | 2006-01-19 | Ibiden Co., Ltd. | Ic chip mounting substrate, ic chip mounting substrate manufacturing method, optical communication device, and optical communication device manufacturing method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5158673A (en) * | 1974-11-20 | 1976-05-22 | Fujitsu Ltd | Purintohaisenbanno seizohoho |
| JPS5742186A (en) * | 1980-08-28 | 1982-03-09 | Tokyo Shibaura Electric Co | Both-side metal core through hole printed circuit board |
| JPH03229488A (en) * | 1990-02-02 | 1991-10-11 | Sharp Corp | Manufacture of printed wiring board |
| JP4390368B2 (en) * | 2000-06-08 | 2009-12-24 | 新光電気工業株式会社 | Wiring board manufacturing method |
| JP3851513B2 (en) | 2001-03-27 | 2006-11-29 | 株式会社鈴木 | Wiring board manufacturing method |
| JP2003220595A (en) | 2002-01-29 | 2003-08-05 | Suzuki Co Ltd | Method for punching resin substrate and method for manufacturing wiring substrate |
| JP2004066763A (en) * | 2002-08-09 | 2004-03-04 | Nitto Denko Corp | Metal foil laminate and manufacturing method thereof |
-
2004
- 2004-06-14 JP JP2004174969A patent/JP4551135B2/en not_active Expired - Fee Related
-
2005
- 2005-05-24 US US11/135,350 patent/US7276438B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060012967A1 (en) * | 2002-04-01 | 2006-01-19 | Ibiden Co., Ltd. | Ic chip mounting substrate, ic chip mounting substrate manufacturing method, optical communication device, and optical communication device manufacturing method |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2005353932A (en) | 2005-12-22 |
| US7276438B2 (en) | 2007-10-02 |
| JP4551135B2 (en) | 2010-09-22 |
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