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US20040155693A1 - Level shifter having automatic delay adjusting function - Google Patents

Level shifter having automatic delay adjusting function Download PDF

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Publication number
US20040155693A1
US20040155693A1 US10/762,336 US76233604A US2004155693A1 US 20040155693 A1 US20040155693 A1 US 20040155693A1 US 76233604 A US76233604 A US 76233604A US 2004155693 A1 US2004155693 A1 US 2004155693A1
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United States
Prior art keywords
type transistor
voltage
drain
delay adjusting
supplied
Prior art date
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Abandoned
Application number
US10/762,336
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English (en)
Inventor
Miwa Ito
Kazuyuki Nakanishi
Akio Hirata
Hiroo Yamamoto
Tsuguyasu Hatsuda
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HATSUDA, TSUGUYASU, HIRATA, AKIO, ITO, MIWA, NAKANISHI, KAZUYUKI, YAMAMOTO, HIROO
Publication of US20040155693A1 publication Critical patent/US20040155693A1/en
Priority to US11/191,009 priority Critical patent/US7148735B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature

Definitions

  • the present invention relates to a level shifter disposed between two logic circuits respectively driven by different power voltages for shifting the voltage level of an output signal of one of the logic circuits to supply the shifted voltage to the other logic circuit.
  • FIG. 15 is a diagram for showing the configuration of the level shifter and FIG. 16 is a diagram for showing its input waveform and output waveform.
  • the internal voltage level VDD 1 of the input signal V(in) is transferred to an inverter I 1 .
  • the inverter I 1 outputs a signal at L (0 V) level
  • an inverter I 2 outputs a signal at the internal voltage level VDD 1 .
  • An input voltage to the gate of an NMOS transistor N 1 becomes the internal voltage level VDD 1 , and therefore, the NMOS transistor N 1 is turned on, and an input voltage to the gate of another NMOS transistor N 2 becomes 0 V, and hence, the NMOS transistor N 2 is turned off.
  • an input voltage to the gate of a PMOS transistor P 2 and an inverter I 3 changes from the external voltage level VDD 2 to 0 V, and hence, the output voltage of the inverter I 3 is changed from 0 V to the external voltage level VDD 2 .
  • the PMOS transistor P 2 since the PMOS transistor P 2 is gradually turned on, the input voltage to the gate of a PMOS transistor P 1 is changed from 0 V to the external voltage level VDD 2 , and hence the PMOS transistor P 1 is turned off.
  • the inverter I 1 outputs a signal at the internal voltage level VDD 1 and the inverter I 2 outputs a voltage of 0 V
  • the input voltage to the gate of the NMOS transistor N 1 becomes 0 V, and hence the NMOS transistor N 1 is turned off, and the input voltage to the gate of the NMOS transistor N 2 becomes the internal voltage level VDD 1 , and hence the NMOS transistor N 2 is turned on.
  • the input voltage to the gate of the PMOS transistor P 1 is changed from the external voltage level VDD 2 to 0 V
  • the PMOS transistor P 1 is gradually turned on, and therefore, the input voltage to the gate of the PMOS transistor P 2 and the inverter I 3 is changed from 0 V to the external voltage level VDD 2 , and the PMOS transistor P 2 is turned off.
  • the output voltage of the inverter I 3 namely, the output signal from the output terminal out, is changed from the external voltage level VDD 2 to 0 V.
  • FIG. 17 shows the characteristics of the rise delay time tpLH and the fall delay time tpHL of the output signal obtained when the internal power voltage level VDD 1 and the external power voltage level VDD 2 are changed.
  • An object of the invention is, in a level shifter, automatically adjusting balance between rise and fall delay times of an output signal without externally inputting a control signal even when one or both of a power voltage on the input side and a power voltage on the output side are changed.
  • the balance between the delay times is corrected by automatically compensating the quantity of a current supplied as the output signal to be increased so as to reduce the rise delay time, or by automatically increasing the fall delay time of the output signal.
  • the level shifter having an automatic delay adjusting function of this invention includes an input terminal to which an input signal having a first amplitude voltage corresponding to potential difference between a first power voltage and a given voltage is input; a level shifting unit for level-shifting the first amplitude voltage of the input signal input to the input terminal into a second amplitude voltage corresponding to potential difference between a second power voltage and the given voltage; an output terminal for outputting an output signal resulting from shift performed by the level shifting unit; and an automatic delay adjusting circuit for automatically correcting balance between a rise delay time and a fall delay time of the output signal that results from the shift by the level shifting unit and is output from the output terminal in accordance with change of a voltage value of at least one of the first power voltage and the second power voltage.
  • the automatic delay adjusting circuit compensatively increases the quantity of a current flowing to the output terminal when the rise delay time of the output signal output from the output terminal is longer than the fall delay time.
  • the automatic delay adjusting circuit includes an N-type transistor, and the second power voltage is supplied to one end of the N-type transistor, the other end thereof is connected to the output terminal and a gate thereof is connected to the input terminal.
  • the automatic delay adjusting circuit further includes a P-type transistor, and a drain of the P-type transistor is connected to a source of the N-type transistor, the first power voltage is supplied to a source thereof and the second power voltage is supplied to a gate thereof.
  • the automatic delay adjusting circuit includes a current mirror circuit, the current mirror circuit includes a first N-type transistor and first and second P-type transistors, the given voltage is supplied to a source of the first N-type transistor, a drain thereof is connected to gates of the first and second P-type transistors and a gate thereof is connected to the input terminal, a drain of the first P-type transistor is connected to the drain of the first N-type transistor and the second power voltage is supplied to a source thereof, and a drain of the second P-type transistor is connected to the output terminal and the second power voltage is supplied to a source thereof.
  • the level shifter having an automatic delay adjusting function further includes an inverter for inverting the signal resulting from the shift performed by the level shifting unit and for outputting an inverted signal to the output terminal
  • the current mirror circuit further includes a second N-type transistor, and a source of the second N-type transistor is connected to the drain of the first N-type transistor, a drain thereof is connected to the drain of the first P-type transistor and a gate thereof is connected between the inverter and the output terminal.
  • the automatic delay adjusting circuit compensatively reduces lowering of a voltage on the side of the input terminal of the level shifting unit or a voltage on the side of the output terminal of the level shifting unit when the rise delay time of the output signal output from the output terminal is longer than the fall delay time.
  • the automatic delay adjusting circuit includes serially connected first and second N-type transistors, a gate of the first N-type transistor is connected to the input terminal and a drain thereof is connected to a signal input side of the level shifting unit, and the given voltage is supplied to a source of the second N-type transistor, a drain thereof is connected to a source of the first N-type transistor and the second power voltage is supplied to a gate thereof.
  • the automatic delay adjusting circuit includes serially connected first and second N-type transistors, a gate of the first N-type transistor is connected to a signal output side of the level shifting unit and a drain thereof is connected to the output terminal, and a drain of the second N-type transistor is connected to a source of the first N-type transistor, the given voltage is supplied to a source thereof and the first power voltage is supplied to a gate thereof.
  • the level shifting unit is a cross latch type shifter including first and second P-type transistors and third and fourth N-type transistors, a drain of one of the first and second P-type transistors is connected to a drain of the other P-type transistor and a drain of the second P-type transistor is connected to the output terminal, a gate of the third N-type transistor is connected to the input terminal and the given voltage is supplied to a source thereof, and a gate of the fourth N-type transistor is connected to the input terminal through an inverter and the given voltage is supplied to a source thereof, the automatic delay adjusting circuit includes a fifth N-type transistor, and a drain of the fifth N-type transistor is connected to the source of the fourth N-type transistor, the given voltage is supplied to a source thereof and the second power voltage is supplied to a gate thereof.
  • the automatic delay adjusting circuit further includes a sixth N-type transistor, and a drain of the sixth N-type transistor is connected to the source of the third N-type transistor, the given voltage is supplied to a source thereof and the first power voltage is supplied to a gate thereof.
  • the level shifting unit is a cross latch type shifter including first and second P-type transistors and first and second N-type transistors, a drain of one of the first and second P-type transistors is connected to a gate of the other P-type transistor and a drain of the second P-type transistor is connected to the output terminal, and a gate of the first N-type transistor is connected to the input terminal and the given voltage is supplied to a source thereof, and a gate of the second N-type transistor is connected to the input terminal through an inverter and the given voltage is supplied to a source thereof.
  • the rise delay time and the fall delay time of an output signal from an output terminal are set to be substantially the same time when a voltage level is shifted to be higher, if the voltage level is shifted to be lower due to change of first and second power voltages, the rise delay time becomes longer than the fall delay time.
  • the automatic delay adjusting circuit automatically corrects imbalance between the delay times even in such a case, so that an input signal can be level-shifted always with appropriate delay characteristics regardless of the values of the power voltages attained before and after the level shift.
  • the automatic delay adjusting circuit makes a large current flow to the output terminal so as to compensate the voltage increase of the output signal, and hence, the rise delay time is reduced to be balanced with the fall delay time.
  • the P-type transistor when it is necessary to compensate the delay times because the imbalance between the rise and fall delay times is large, namely, merely when the second power voltage is lower than the first power voltage, the P-type transistor is turned on so as to allow a large current to flow to the output terminal.
  • a large current is allowed to flow to the output terminal by using the current mirror circuit, the rise delay time can be effectively reduced.
  • the second N-type transistor is turned off when the output signal from the output terminal has undergone a transition to H level, and therefore, a steady state current flowing from the current mirror circuit can be cut so as to reduce the power consumption.
  • the rise delay time of the output signal becomes longer than the fall delay time
  • the fall of the input signal to the level shifting unit is slowed so as to increase the fall delay time of the output signal, or the rise of the output signal from the level shifting unit is shortened so as to reduce the rise delay time of the output signal.
  • the balance between the rise delay time and the fall delay time can be satisfactorily kept.
  • FIG. 1 is a block diagram of a system using a level shifter having an automatic delay adjusting function according to Embodiment 1 of the invention
  • FIG. 2 is a circuit diagram for showing the internal configuration of the level shifter having the automatic delay adjusting function of Embodiment 1;
  • FIG. 3 is a diagram for showing the delay time characteristics of the level shifter of FIG. 2;
  • FIG. 4 is a circuit diagram for showing the internal configuration of a level shifter having an automatic delay adjusting function according to Embodiment 2 of the invention.
  • FIG. 5 is a diagram for showing the delay time characteristics of the level shifter of FIG. 4;
  • FIG. 6 is a circuit diagram for showing the internal configuration of a level shifter having an automatic delay adjusting function according to Embodiment 3 of the invention.
  • FIG. 7 is a circuit diagram for showing the internal configuration of a level shifter having an automatic delay adjusting function according to Embodiment 4 of the invention.
  • FIG. 8 is a circuit diagram for showing the internal configuration of a level shifter having an automatic delay adjusting function according to Embodiment 5 of the invention.
  • FIG. 9 is a diagram for showing the delay time characteristics of the level shifter of FIG. 8;
  • FIG. 10 is a circuit diagram for showing the internal configuration of a level shifter having an automatic delay adjusting function according to Embodiment 6 of the invention.
  • FIG. 11 is a circuit diagram for showing the internal configuration of a level shifter having an automatic delay adjusting function according to Embodiment 7 of the invention.
  • FIG. 12 is a circuit diagram for showing the internal configuration of a level shifter having an automatic delay adjusting function according to Embodiment 8 of the invention.
  • FIG. 13 is a circuit diagram for showing the internal configuration of a level shifter having a delay adjusting function according to first related art of the invention
  • FIG. 14 is a circuit diagram for showing the internal configuration of a level shifter having a delay adjusting function according to second related art of the invention.
  • FIG. 15 is a circuit diagram for showing the configuration of a conventional level shifter
  • FIG. 16 is a diagram for explaining a rise delay time and a fall delay time of an output signal in the conventional level shifter.
  • FIG. 17 is a diagram for showing a rise delay time characteristic and a fall delay time characteristic of the output signal obtained when a first power voltage and a second power voltage are changed in the conventional level shifter.
  • FIG. 1 is a block diagram of a system using a level shifter having an automatic delay adjusting function according to Embodiment 1 of the invention.
  • a reference numeral 1 denotes a first logic circuit
  • a reference numeral 2 denotes a first power supply for supplying a first power voltage VDDL
  • a reference numeral 3 denotes a second logic circuit
  • a reference numeral 4 denotes a second power supply for supplying a second power voltage VDDH
  • a reference numeral 5 denotes a level shifter having an automatic delay adjusting function disposed between the first logic circuit 1 and the second logic circuit 3
  • a reference numeral 6 denotes a control unit for changing the first and second power voltages VDDL and VDDH of the first and second power supplies 2 and 4 .
  • the first power voltage VDDL is supplied to the first logic circuit 1 by the first power supply 2
  • the second power voltage VDDH is supplied to the second logic circuit 3 by the second power supply 4 . Signals are transferred between the first logic circuit 1 and the second logic circuit 3 .
  • the first power voltage VDDL is set to a high voltage
  • the first power voltage VDDL is set to a low voltage.
  • the second power voltage VDDH is set to a high voltage
  • the second power voltage VDDH is set to a low voltage
  • the first power voltage VDDL and the second power voltage VDDH can be independently changed respectively in accordance with control signals cnt 1 and cnt 2 supplied by the control unit 6 .
  • the amplitude voltage of an output signal from the first logic circuit 1 corresponds to a potential difference between the first power voltage VDDL and a ground voltage (a given voltage), namely, the first power voltage VDDL.
  • the level shifter 5 level-shifts the signal level (the amplitude voltage) of the output signal from the first logic circuit 1 into the second power voltage VDDH corresponding to the signal level (the amplitude voltage) of a signal in the second logic circuit 3 (i.e., the amplitude voltage corresponding to a potential difference between the second power voltage VDDH and the ground voltage).
  • a signal that has been level-shifted by the level shifter 5 is input to the second logic circuit 3 .
  • the delay time characteristics can be improved in accordance with the voltage levels of an input signal and an output signal, and furthermore, imbalance between the delay time characteristics and increase of a delay time derived from the changes of the voltage levels of the input signal and the output signal can be avoided.
  • FIG. 2 is a circuit diagram for showing the internal configuration of the level shifter 5 having the automatic delay adjusting function.
  • in indicates an input terminal
  • out indicates an output terminal
  • L indicates a level shifting unit disposed between the terminals in and out.
  • the output signal from the first logic circuit 1 is input to the input terminal in.
  • the input signal entering the input terminal in is input to an input node n 1 of the level shifting unit L through a first inverter I 1 .
  • the first inverter I 1 to which the first power voltage VDDL is supplied, inverts the level of the input signal so that the inverted signal can be at a level of the ground voltage when the input signal is the first power voltage VDDL and that the inverted signal can be at a level of the first power voltage VDDL when the input signal is the ground voltage.
  • the level shifting unit L is a cross latch type shifter having the internal configuration including first and second P-type MOS transistors P 1 and P 2 , first and second N-type MOS transistors N 1 and N 2 and a second inverter I 2 .
  • the transistors used in this embodiment are not limited to MOS (Metal Oxide Semiconductor) type transistors but may be MIS (Metal Insulator Semiconductor) type transistors. This also applies to each embodiment described below.
  • the first and second P-type MOS transistors P 1 and P 2 to the sources of which the second power voltage VDDH is supplied, are in a cross coupled configuration in which the drain of one MOS transistor is connected to the gate of the other.
  • the drain of the second P-type MOS transistor P 2 is connected, as an output node n 3 , to the output terminal out through a third inverter I 3 as described later.
  • the gate of the first N-type MOS transistor N 1 works as the input node n 1 of the level shifting unit L, and an inverted input signal entering the input terminal in is input to this gate (i.e., the input node n 1 ) through the first inverter I 1 .
  • a ground voltage (a given voltage) VSS is supplied to the source of the first N-type MOS transistor N 1 , whose drain is connected to the drain of the first P-type MOS transistor P 1 , and the connecting point between these transistors corresponds to a node n 2 .
  • the gate thereof is connected to the input node n 1 of the level shifting unit L through the second inverter I 2 for receiving the input signal entering the input terminal in, the ground voltage VSS is supplied to the source thereof, the drain thereof is connected to the drain of the second P-type MOS transistor P 2 , and the connection point between these transistors corresponds to the output node n 3 of the level shifting unit L.
  • the second inverter I 2 accepts the first power voltage VDDL and performs a signal inverting operation similar to that of the first inverter I 1 .
  • the level shifting unit L shifts the level of a signal entering the input node n 1 (namely, the level of the inverted input signal from the input terminal in) and increases the amplitude voltage of the signal (corresponding to the first power voltage VDDL) to a larger amplitude voltage (corresponding to the second power voltage VDDH). Specifically, when the signal at the input node n 1 is at the level of the first power voltage VDDL, the signal level is shifted into the second power voltage VDDH, and when the signal at the input node n 1 is at the level of the ground voltage VSS, the signal level is shifted into the ground voltage VSS.
  • the output node n 3 of the level shifting unit L is connected to the output terminal out through the third inverter I 3 .
  • the inverter I 3 accepts the second power voltage VDDH, and shifts, without changing the amplitude voltage, the level of the signal at the output node n 3 of the level shifting unit L into the second power voltage VDDH when the signal is at the level of the ground voltage VSS and into the ground voltage VSS when the signal is at the level of the second power voltage VDDH.
  • the output node n 3 of the level inverting unit L is connected to an automatic delay adjusting circuit 10 A.
  • This automatic delay adjusting circuit 10 A automatically adjusts the balance between a rise delay time and a fall delay time of an output signal that results from the level shift performed by the level shifting unit L and is output from the output terminal out even when at least one of the first and second power voltages VDDL and VDDH is changed.
  • the automatic delay adjusting circuit 10 A is composed of an N-type MOS transistor N 3 .
  • the second power voltage VDDH is supplied to the source of the MOS transistor N 3 , the drain thereof is connected to the output node n 3 of the level shifting unit L and the gate thereof is connected to the input node n 1 of the level shifting unit L.
  • the first and third inverters II and I 3 are respectively disposed before and after the input node n 1 and the output node n 3 of the level shifting unit L in this embodiment, these inverters I 1 and 13 are not always necessary. In a basic configuration not using these inverters, the rises and the falls of the input signal and the output signal are reversed in the following description.
  • the gate-source voltage Vgs of the P-type MOS transistor P 2 is small and the gate-source voltage Vgs of the N-type MOS transistor N 2 is large. Accordingly, the driving ability of the P-type MOS transistor P 2 is lower as compared with that of the N-type MOS transistor N 2 , and hence, a fall delay time from the input signal in to the output signal out is increased as compared with a rise delay time so as to largely spoil the balance between these delay times.
  • the N-type MOS transistor N 3 of the automatic delay adjusting circuit 10 A when the input signal in falls, the N-type MOS transistor N 3 of the automatic delay adjusting circuit 10 A is turned on, so as to apply the second power voltage VDDH to the output node n 3 of the level shifting unit L, and hence, a current on the basis of the second power voltage VDDH flows to the output node n 3 . Accordingly, even when the driving ability of the P-type MOS transistor P 2 of the level shifting unit L is lowered, the quantity of a current flowing to the output node n 3 is increased because the current flowing from the N-type MOS transistor N 3 of the automatic delay adjusting circuit 10 A is added to a current flowing to the output node n 3 through the P-type MOS transistor P 2 . As a result, the fall delay time of the output signal from the output terminal out is reduced to be substantially equivalent to the rise delay time. Thus, the balance between the delay times can be satisfactorily compensated.
  • FIG. 3 shows the change characteristics of the rise delay time tpLH and the fall delay time tpHL of the output signal obtained when the first and second power voltages VDDL and VDDH are changed in this embodiment.
  • Data shown in FIG. 3 are calculated under the same conditions as those employed for obtaining the characteristic diagram of the conventional level shifter shown in FIG. 17.
  • the imbalance between the delay times can be suppressed even when the power voltages are changed as shown in FIG. 3.
  • the fall delay time tpHL of the output signal can be adjusted to be substantially as short as the rise delay time tpLH, so that the characteristics of these delay times can be well balanced.
  • a level shifter having an automatic delay adjusting function according to Embodiment 2 of the invention will now be described with reference to the accompanying drawings.
  • FIG. 4 is a circuit diagram of the level shifter having the automatic delay adjusting function of this embodiment.
  • the level shifter of FIG. 4 has a basic configuration substantially the same as that of the level shifter of FIG. 2 but is different in an automatic delay adjusting circuit 10 B including a P-type MOS transistor P 3 in addition to the N-type MOS transistor N 3 .
  • the source of the N-type MOS transistor N 3 is connected to the output terminal out and the gate thereof is connected to the input node n 1 of the level shifting unit L. Furthermore, in the P-type MOS transistor P 3 , the drain thereof is connected to the drain of the N-type MOS transistor N 3 , the first power voltage VDDL is supplied to the source thereof and the second power voltage VDDH is supplied to the gate thereof.
  • the fall delay time tpHL of the output signal is increased as compared with the rise delay time tpLH, so as to largely spoil the balance between these delay times.
  • the driving ability of the P-type MOS transistor P 3 is changed in accordance with a potential difference between the first power voltage VDDL and the second power voltage VDDH, so that the driving ability of the P-type MOS transistor P 3 can be higher as the first power voltage VDDL is higher and the second power voltage VDDH is lower. Accordingly, when these power voltages are under conditions for more largely spoiling the balance between the rise delay time and the fall delay time, the quantity of the current flowing to the output node n 3 on the basis of the second power voltage VDDH is larger, and hence, the compensating effect can be advantageously larger.
  • the P-type MOS transistor P 3 is turned off, so as to automatically stop compensating the rise of the signal at the output node n 3 of the level shifting unit L. Accordingly, in the whole level shifter, useless transition of the transistors can be avoided, so as to advantageously reduce the power consumption.
  • the balance between the rise and fall delay times of the output signal can be automatically kept, and in addition, the automatic delay adjusting circuit 10 B can be automatically stopped when there is no need to adjust the delay times.
  • a level shifter having an automatic delay adjusting function according to Embodiment 3 of the invention will now be described with reference to the accompanying drawing.
  • FIG. 6 is a circuit diagram of the level shifter having the automatic delay adjusting function of this embodiment.
  • the level shifter of FIG. 6 includes a current mirror circuit 15 as an automatic delay adjusting circuit 10 C.
  • the current mirror circuit 15 includes a first N-type MOS transistor N 3 and first and second P-type MOS transistors P 3 and P 4 .
  • the N-type MOS transistor N 3 the ground voltage VSS is supplied to the source thereof, the drain thereof is connected to the gates of the first and second P-type MOS transistors P 3 and P 4 and the gate thereof is connected to the input node n 1 of the level shifting unit L.
  • the drain thereof is connected to the drain of the first N-type MOS transistor N 3 and the second power voltage VDDH is supplied to the source thereof.
  • the second P-type MOS transistor P 4 the drain thereof is connected to the output node n 3 of the level shifting unit L and the second power voltage VDDH is supplied to the source thereof.
  • the fall delay time tpHL is increased as compared with the rise delay time tpLH of the output signal, so as to largely spoil the balance between these delay times as described above.
  • the N-type MOS transistor N 3 is turned on in the current mirror circuit 15 , and hence the P-type MOS transistors P 3 and P 4 are also turned on.
  • a current on the basis of the second power voltage VDDH flows to the output node n 3 of the level shifting unit L through the P-type MOS transistor P 4 , so as to compensate the rise of the signal at the output node n 3 .
  • the increase of the fall delay time tpHL of the output signal from the output terminal out can be effectively suppressed, so as to satisfactorily keep the balance between the rise delay time tpLH and the fall delay time tpHL.
  • a level shifter having an automatic delay adjusting function according to Embodiment 4 of the invention will now be described with reference to the accompanying drawing.
  • FIG. 7 is a circuit diagram of the level shifter having the automatic delay adjusting function of this embodiment.
  • a current mirror circuit 15 ′ obtained by additionally providing a second N-type MOS transistor N 4 to the current mirror circuit 15 working as the automatic delay adjusting circuit 10 C shown in FIG. 6 is provided as an automatic delay adjusting circuit 10 D.
  • the second N-type MOS transistor N 4 is disposed between the first N-type MOS transistor N 3 and the first P-type MOS transistor P 3 , and the source thereof is connected to the drain of the first N-type MOS transistor N 3 , the drain thereof is connected to the drain of the first P-type MOS transistor P 3 and the gate thereof is connected between the third inverter I 3 and the output terminal out.
  • the second N-type MOS transistor N 4 of the current mirror circuit 15 ′ is in an ON state because the output signal from the output terminal out is at the level of the second power voltage VDDH.
  • the first N-type MOS transistor N 3 and the first and second P-type MOS transistors P 3 and P 4 are turned on in the current mirror circuit 15 ′, and hence, a current on the basis of the second power voltage VDDH is supplied through the P-type MOS transistor P 4 to the output node n 3 of the level shifting unit L, so as to compensate the rise of the signal at the output node n 3 (namely, the fall of the output signal).
  • the N-type MOS transistor N 4 of the current mirror circuit 15 ′ is turned off, and therefore, a potential at the node n 4 is immediately increased owing to the drive of the P-type MOS transistor P 3 in the current mirror circuit 15 ′, so as to turn off the P-type MOS transistor P 4 .
  • the current supply for the compensation to the output node n 3 of the level shifting unit L by the current mirror circuit 15 ′ is stopped.
  • the level shifter of this embodiment includes a feedback circuit for automatically controlling the operation and the non-operation of the automatic delay adjusting circuit 10 D even when the first and second power voltages are changed. Accordingly, not only the balance in the delay characteristics between the rise delay time and the fall delay time of the output signal is satisfactorily kept but also efficient balance adjustment can be realized.
  • a level shifter having an automatic delay adjusting function according to Embodiment 5 of the invention will now be described with reference to the accompanying drawings.
  • FIG. 8 is a circuit diagram of the level shifter having the automatic delay adjusting function of this embodiment.
  • an automatic delay adjusting circuit 10 E is disposed on the side of the input node n 1 of the level shifting unit L.
  • the automatic delay adjusting circuit 10 E includes an N-type MOS transistor N 5 , which is serially connected to a P-type MOS transistor P 5 so as to together construct a first inverter I 1 , and a second N-type MOS transistor N 4 serially connected to the first N-type MOS transistor (first N-type transistor) N 5 .
  • the gate of the first N-type MOS transistor N 5 is connected to the input terminal in and the drain thereof is connected to the input node n 1 of the level shifting unit L.
  • the ground voltage VSS is supplied to the source thereof, the drain thereof is connected to the source of the first N-type MOS transistor N 5 and the second power voltage VDDH is supplied to the gate thereof.
  • the fall delay time tpHL of the output signal becomes longer than the rise delay time tpLH so that the time difference therebetween is increased as is understood from FIG. 3.
  • the second power voltage VDDH is set to a lower voltage, the driving ability of the N-type MOS transistor N 4 of the automatic delay adjusting circuit 10 E is further lower.
  • a level shifter having an automatic delay adjusting function according to Embodiment 6 of the invention will now be described with reference to FIG. 10.
  • the level shifter of this embodiment is obtained by combining Embodiment 1 shown in FIG. 2 and Embodiment 5 shown in FIG. 8.
  • the level shifter of FIG. 10 includes two automatic delay adjusting circuits 10 A and 10 E.
  • One automatic delay adjusting circuit 10 A includes the N-type MOS transistor N 3 connected to the output node n 3 of the level shifting unit L and operated in accordance with potential at the input node n 1 of the level shifting unit L.
  • the other automatic delay adjusting circuit 10 E includes the second N-type MOS transistor N 4 serially connected to the N-type MOS transistor (first transistor) N 5 of the first inverter I 1 .
  • Embodiment 1 an effect resulting from the combination of Embodiment 1 and Embodiment 5 can be attained.
  • the fall delay time tpHL of the output signal is adjusted to be shorter by the automatic delay adjusting circuit 10 A, and the rise delay time tpLH of the output signal is adjusted to be longer by the automatic delay adjusting circuit 10 E, so that the balance between these delay times tpHL and tpLH can be kept at the substantially intermediate delay time.
  • a level shifter having an automatic delay adjusting function according to Embodiment 7 of the invention will now be described with reference to FIG. 11.
  • the level shifter of FIG. 11 is obtained by changing the position of the automatic delay adjusting circuit 10 E of Embodiment 5 shown in FIG. 8.
  • an automatic delay adjusting circuit 10 F is disposed on the side of the output node n 3 of the level shifting unit L.
  • the automatic delay adjusting circuit 10 F includes serially connected first and second N-type MOS transistors N 6 and N 4 similarly to the automatic delay adjusting circuit 10 E of FIG. 8, and the first N-type MOS transistor N 6 also works as the N-type MOS transistor N 6 serially connected to a P-type MOS transistor P 6 so as to together construct a third inverter I 3 .
  • the gate of the first N-type MOS transistor N 6 is connected to the output node n 3 of the level shifting unit L, the drain thereof is connected to the output terminal out and the source thereof is connected to the drain of the second N-type MOS transistor N 4 . Also, the first power voltage VDDL is supplied to the gate of the second N-type MOS transistor N 4 .
  • the fall delay time tpHL of the output signal is longer than the rise delay time tpLH so that the time difference therebetween is increased as is understood from FIG. 3.
  • the driving ability of the N-type MOS transistor N 4 of the automatic delay adjusting circuit 10 F becomes higher.
  • the fall delay time tpHL of the signal from the output terminal out is reduced.
  • the rise delay time tpLH is short
  • the fall delay time tpHL is adjusted to be short, so as to satisfactorily compensate the balance between these delay times tpLH and tpHL.
  • a level shifter having an automatic delay adjusting function according to Embodiment 8 of the invention will now be described with reference to the accompanying drawing.
  • FIG. 12 is a circuit diagram of the level shifter having the automatic delay adjusting function of this embodiment.
  • a level shifting unit L is a cross latch type shifter including first and second P-type MOS transistors P 1 and P 2 , third and fourth N-type MOS transistors N 1 and N 2 and a second inverter I 2
  • an automatic delay adjusting circuit 10 G includes a fifth N-type MOS transistor N 4 and a sixth N-type MOS transistor N 3 .
  • the fifth N-type MOS transistor N 4 is serially connected to the fourth N-type MOS transistor N 2 of the level shifting unit L, the drain thereof is connected to the source of the fourth N-type MOS transistor N 2 , the ground voltage VSS is supplied to the source thereof and the second power voltage VDDH is supplied to the gate thereof.
  • the sixth N-type MOS transistor N 3 is serially connected to the third N-type MOS transistor N 1 of the level shifting unit L, the drain thereof is connected to the source of the third N-type MOS transistor N 1 , the ground voltage VSS is supplied to the source thereof and the first power voltage VDDL is supplied to the gate thereof.
  • the driving ability of the P-type MOS transistor P 2 is lower as compared with that of the N-type MOS transistor N 2 of the level shifting unit L, and hence, the rise delay time of the signal at the output node n 3 becomes longer than the fall delay time.
  • the driving ability of the fifth N-type MOS transistor N 4 is suppressed as compared with that of the sixth N-type MOS transistor N 3 . Therefore, the fall delay time at the output node n 3 of the level shifting unit L becomes longer than the rise delay time.
  • the lowering of the driving ability of the P-type MOS transistor P 2 of the level shifting unit L and the forced suppression of the driving ability of the fifth N-type MOS transistor N 4 can be compared favorably with each other.
  • the rise delay time tpLH of the output signal from the output terminal out tends to be substantially equal to the fall delay time tpHL, so that the rise and fall delay times can be well balanced.
  • FIG. 13 is a circuit diagram of a level shifter of the related art.
  • the gate of the N-type MOS transistor N 4 which is serially connected between the drain of the P-type MOS transistor P 3 and the drain of the N-type MOS transistor N 3 in the current mirror circuit 15 ′ of the level shifter shown in FIG. 7, is connected not to the output terminal out but to a control terminal cnt, so that the N-type MOS transistor N 4 can be controlled by externally supplying a control signal through the control terminal cnt.
  • the driving ability of the P-type MOS transistor P 2 is lower as compared with that of the N-type MOS transistor N 2 in the level shifting unit L, and hence, the fall delay time of the output signal is increased as compared with the rise delay time, so as to largely spoil the balance between these delay times.
  • a control signal at H (high) level is applied to the control terminal cnt so as to place the N-type MOS transistor N 4 always in an ON state, and the N-type MOS transistor N 3 is turned on at the fall of the input signal.
  • the rise of the signal at the output node n 3 of the level shifting unit L is compensated so as to suppress the increase of the fall delay time of the output signal.
  • a control signal at L level is applied to the control terminal cnt so as to place the N-type MOS transistor N 4 always in an OFF state.
  • the delay adjusting function is performed not automatically but can be selected to perform or not by inputting a control signal from the control terminal cnt.
  • the delay adjusting function is performed not automatically but can be selected to perform or not by inputting a control signal from the control terminal cnt.
  • FIG. 14 is a circuit diagram of the level shifter according to the related art.
  • the gate of the P-type MOS transistor P 3 of the automatic delay adjusting circuit 10 B which accepts the second power voltage VDDH in the level shifter of Embodiment 2 shown in FIG. 4, is connected to a control terminal cnt instead of supplying the second power voltage VDDH, so that the P-type MOS transistor P 3 can be controlled by externally supplying a control signal through the control terminal cnt.
  • the fall delay time of the output signal is increased as compared with the rise delay time, so as to largely spoil the balance between these delay times as described above.
  • a control signal at L level is applied to the control terminal cnt so as place the P-type MOS transistor P 3 always in an ON state, and the N-type MOS transistor N 3 is turned on at the fall of the input signal.
  • the rise of the signal at the output node n 3 of the level shifting unit L is compensated so as to suppress the increase of the fall delay time of the output signal.
  • the function to adjust the delay times can be disabled, and hence, useless transition of the transistors can be avoided in the whole level shifter, resulting in advantageously reducing the power consumption.
  • the function to adjust the delay times can be selectively employed in accordance with the control signal supplied through the control terminal even if the power voltages are changed. In this manner, the delay characteristics of the rise delay time and the fall delay time of the output signal can be well balanced and efficient balance adjustment can be realized.

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US20050258887A1 (en) 2005-11-24
CN1520037A (zh) 2004-08-11
US7148735B2 (en) 2006-12-12

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