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US20040103385A1 - Method of ITO layout to make IC bear the high-volt electrostatic discharge - Google Patents

Method of ITO layout to make IC bear the high-volt electrostatic discharge Download PDF

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Publication number
US20040103385A1
US20040103385A1 US10/304,736 US30473602A US2004103385A1 US 20040103385 A1 US20040103385 A1 US 20040103385A1 US 30473602 A US30473602 A US 30473602A US 2004103385 A1 US2004103385 A1 US 2004103385A1
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US
United States
Prior art keywords
layout
ito
static discharge
electro static
bear
Prior art date
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Granted
Application number
US10/304,736
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US6981234B2 (en
Inventor
Hsing-Fa Wang
Ming-Chuan Lin
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Wintek Corp
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Wintek Corp
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Priority to JP2002328786A priority Critical patent/JP2004165385A/en
Application filed by Wintek Corp filed Critical Wintek Corp
Priority to US10/304,736 priority patent/US6981234B2/en
Assigned to WINTEK CORPORATION reassignment WINTEK CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, MING-CHUAN, WANG, HSING-FA
Publication of US20040103385A1 publication Critical patent/US20040103385A1/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Definitions

  • the present invention relates to a method of ITO layout to make IC bear the high-volt electro static discharge.
  • the first of all developments in the relative industries is how to improve the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client and designing the circuits which make LCD Driver IC be able to resist the high-volt static voltage in accordance with the property of the electronic component.
  • ESD Electro Static Discharge
  • the object of the present invention is to provide a method of ITO layout to make IC bear the high-volt electro static discharge.
  • the major steps of a method of ITO layout to make IC bear the high-volt electro static discharge include: designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module (COG type) in accordance with the function and use of each pin; improving the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client.
  • COG type Driver IC bonding and Interface on LCD Module
  • the major steps of a method of ITO layout to make IC bear the high-volt electro static discharge include: designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module (COG type) in accordance with the function and use of each pin; improving the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client; wherein: connecting the pins of all VDD or VSS at the bottom of the IC and the width of ITO layout spreading over the bottom of IC after connecting VSS or VDD without influencing the layout of other pins.
  • COG type Driver IC bonding and Interface on LCD Module
  • FIG. 1 is the schematic diagram of ITO layout of DRIVER IC in LCD MODULE in the present invention
  • FIG. 2 is the schematic diagram of ITO layout in the conventional way, which is the regular width of the interface pin.
  • FIG. 3 is the schematic diagram of ITO layout in the present invention, and the different ITO circuit impendence and layout are designed in accordance with the function and use of each interface pin.
  • VOUT I/O The most negative voltage supply pin of the chip. 14 VSS Low Ground. A reference for the logic pins. 15 VDD High Chip's Power Supply pin. 16 D7 H/L Data bus to be connected to the MCU. 17 D6 H/L Data bus to be connected to the MCU. 18 D5 H/L Data bus to be connected to the MCU. 19 D4 H/L Data bus to be connected to the MCU. 20 D3 H/L Data bus to be connected to the MCU. 21 D2 H/L Data bus to be connected to the MCU. 22 D1 H/L Data bus to be connected to the MCU. 23 D0 H/L Data bus to be connected to the MCU. 24 /RD,E I/O The MCU interface input. 25 /WR,R/W I/O The MCU interface input. 26 A0 Input Data/Command control pin. 27 /RES Input Reset signal input. 28 /CS1 Input The chip select input.
  • the present invention discharges the static electricity which enters IC by means of ITO layout's spreading over the bottom of IC according to the special area-distribution function and cooperating the design of the impedance in the special exit-pin, and dissipate the static electricity effectively or isolate part of the static electricity at the position of Module Interface by means of the special design of ITO layout.
  • the present invention improves the protection ability of IC for the electro static discharge and doesn't add the additional capacitor or the antistatic element to reduce the cost effectively.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Elimination Of Static Electricity (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention provides a method of ITO layout to make IC bear the high-volt electro static discharge, wherein the major steps include: designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module(COG type) in accordance with the function and use of each pin; improving the protection function of ESD(Electro Static Discharge) in increasing the LCD Module assembly on the product of the client; wherein: connecting the pins of all VDD or VSS together at the bottom of the IC and the width of ITO layout spreading over the bottom of IC without influencing the layout of other pins after connecting VSS or VDD. Discharge the static electricity that enters the position of Module Interface and dissipate the electro static discharge by means of the ITO layout design of the big area to improve the protection ability of IC for the electro static discharge. Serial connect an extremely high impedance(3K˜50KΩ) in the Reset Pin. Increase the value (100˜1000 Ω) of ITO circuit impedance of Date bus, such as CS1.D/C,WR,RD,D0˜D7,C86 etc.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field Of The Technique [0001]
  • The present invention relates to a method of ITO layout to make IC bear the high-volt electro static discharge. [0002]
  • 2. Description of the Prior Art [0003]
  • It is believed that how to use the most simple way to take the shortest time to deliver all kinds of information to the consumers in the era full of information will be paid attention by the consumers, such as the quotation on the stock market or the newest information of consumption available at any time and in any place etc., and the mobile phones, the electronic mechanisms having display screen, are the best medium for the industrial and commercial world to make use in the situation that the utility rates of the mobile phones almost reach the level of everyone having a mobile phone; however, those who are skilled in this art know that the major reason why the display screen of the mobile phone can show all kinds of information is the combination of an IC connecting with its display screen and the circuit constituted by ITO layout and the relative micro-electronics elements. [0004]
  • The application of the conventional ITO circuit to the mobile phone is favorable for the industrial and commercial world to deliver large complicated informations by means of the mobile phones because the conventional ITO circuit has good electric conductivity and is advantageous to be processed on the glass. But, due to the conventional design of ITO layout in LCD MODULE, it is necessary to greatly improve LCD MODULE(COG type) for the high-volt electro static discharge, which is on account of the drawback that LCD MODULE's unable to bear the high-volt electro static discharge causes the action of the screen on the mobile phone extraordinary. Although one of the solutions is to add capacitors or antistatic elements on the glass, in addition to the limited applicable space, the fairly complicated process and the high cost are also the drawbacks. The first of all developments in the relative industries is how to improve the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client and designing the circuits which make LCD Driver IC be able to resist the high-volt static voltage in accordance with the property of the electronic component. [0005]
  • The inventor of the present application longed for improving and innovating in view of every drawback derived from the above conventional electronic circuit, made extraordinarily painstaking efforts to devote himself to the study of science many years, and achieved this method of ITO Layout to make IC bear the high-volt electro static discharge finally. [0006]
    • SUMMARY OF THE INVENTION
  • The object of the present invention is to provide a method of ITO layout to make IC bear the high-volt electro static discharge. The major steps of a method of ITO layout to make IC bear the high-volt electro static discharge which is provided by the present invention, include: designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module (COG type) in accordance with the function and use of each pin; improving the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client. [0007]
  • The major steps of a method of ITO layout to make IC bear the high-volt electro static discharge, which can reach the above objects of the invention, include: designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module (COG type) in accordance with the function and use of each pin; improving the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client; wherein: connecting the pins of all VDD or VSS at the bottom of the IC and the width of ITO layout spreading over the bottom of IC after connecting VSS or VDD without influencing the layout of other pins. Discharge the static electricity that enters the position of Module Interface and dissipate the static electricity by means of the ITO layout design of the big area to improve the protection ability of IC for the electro static discharge. Serial connect an extremely high impedance (3K˜50KΩ) in the Reset Pin. Increase the impedance (100˜1000 Ω) of ITO circuit of Date bus, such as CS1.D/C,WR,RD,D0˜D7,C86 etc.[0008]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Please refer to the detail description and the drawings thereinafter with regard to a preferred embodiment of the present invention and the technique content, the object and the function of the present invention will be further understood. [0009]
  • FIG. 1 is the schematic diagram of ITO layout of DRIVER IC in LCD MODULE in the present invention; [0010]
  • FIG. 2 is the schematic diagram of ITO layout in the conventional way, which is the regular width of the interface pin; and [0011]
  • FIG. 3 is the schematic diagram of ITO layout in the present invention, and the different ITO circuit impendence and layout are designed in accordance with the function and use of each interface pin.[0012]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Please refer to FIG. 3. The major steps of a method of ITO layout to make IC bear the high-volt electro static discharge which is provided by the present invention, include: [0013]
  • 1. designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module (COG type) in accordance with the function and use of each pin; improving the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client; wherein: [0014]
  • 2. connecting the pins of all VDD or VSS together at the bottom of the IC and the width of ITO layout spreading over the bottom of IC after connecting VSS or VDD without influencing the layout of other pins; [0015]
  • Discharging the static electricity that enters the position of Module Interface and dissipating the static electricity by means of the ITO layout design of the big area to improve the protection ability of IC for the electro static discharge; [0016]
  • 3. serial connecting an extremely high impedance(3K˜50KΩ) in the Reset Pin; [0017]
  • 4. increasing the impedance value (100˜1000 Ω) of ITO circuit of Date bus, such as CS1.D/C,WR,RD,D0˜D7,C86 etc. [0018]
  • The potential and function of every symbol in the drawing is such as that shown in Table 1: [0019]
    NO SYMBOL LEVEL FUNCTION
    1 C86 Input MCU parallel interface selection input
    2 VSS Low Ground. A reference for the logic pins
    3 V5 Supply The most negative LCD
    4 V4 Supply The LCD driving voltage levels.
    5 V3 Supply The LCD driving voltage levels.
    6 V2 Supply The LCD driving voltage levels.
    7 V1 Supply The LCD driving voltage levels.
    8 CAP2+ Output When internal DC-DC voltage converter is
    used.
    9 CAP2− Output When internal DC-DC voltage converter is
    used.
    10 CAP1− Output When internal DC-DC voltage converter is
    used.
    11 CAP1+ Output When internal DC-DC voltage converter is
    used.
    12 CAP3− Output When internal DC-DC voltage converter is
    used.
    13 VOUT I/O The most negative voltage supply pin of the
    chip.
    14 VSS Low Ground. A reference for the logic pins.
    15 VDD High Chip's Power Supply pin.
    16 D7 H/L Data bus to be connected to the MCU.
    17 D6 H/L Data bus to be connected to the MCU.
    18 D5 H/L Data bus to be connected to the MCU.
    19 D4 H/L Data bus to be connected to the MCU.
    20 D3 H/L Data bus to be connected to the MCU.
    21 D2 H/L Data bus to be connected to the MCU.
    22 D1 H/L Data bus to be connected to the MCU.
    23 D0 H/L Data bus to be connected to the MCU.
    24 /RD,E I/O The MCU interface input.
    25 /WR,R/W I/O The MCU interface input.
    26 A0 Input Data/Command control pin.
    27 /RES Input Reset signal input.
    28 /CS1 Input The chip select input.
  • Comparing a method of ITO layout making IC bear the high-volt electro static discharge, which is provided by the present invention, with the other conventional art, the present invention discharges the static electricity which enters IC by means of ITO layout's spreading over the bottom of IC according to the special area-distribution function and cooperating the design of the impedance in the special exit-pin, and dissipate the static electricity effectively or isolate part of the static electricity at the position of Module Interface by means of the special design of ITO layout. The present invention improves the protection ability of IC for the electro static discharge and doesn't add the additional capacitor or the antistatic element to reduce the cost effectively. It also improves the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client. Many changes and modifications in the above described embodiment of the invention can, of course, be carried out without departing from the scope thereof. Accordingly, to promote the progress in science and the useful arts, the invention is disclosed and is intended to be limited only by the scope of the appended claims. [0020]

Claims (4)

What is claimed is:
1. A method of ITO Layout to make IC bear the high-volt electro static discharge, the major steps including: designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module (COG type) in accordance with the function and use of each pin; improving the protection function of ESD (Electro Static Discharge) in increasing the LCD Module assembly on the product of the client.
2. The method of ITO Layout to make IC bear the high-volt electro static discharge according to claim 1, wherein connecting the pins of all VDD or VSS together at the bottom of the IC and the width of ITO layout spreading over the bottom of IC after connecting VSS or VDD without influencing the layout of other pins; discharging the static electricity entering the position of Module Interface and dissipating the electro static discharge by means of the ITO layout design of the big area to improve the protection ability of IC for the electro static discharge.
3. The method of ITO Layout to make IC bear the high-volt electro static discharge according to claim 1, wherein serial connecting an extremely high impedance(3K˜50K Ω) in the Reset Pin.
4. The method of ITO Layout to make IC bear the high-volt electro static discharge according to claim 1, wherein increasing the impedance value (100˜1000 Ω) of ITO circuit of Date bus, such as CS1.D/C,WR,RD,D0˜D7,C86 etc.
US10/304,736 2002-11-12 2002-11-27 Method of ITO layout to make IC bear the high-volt electrostatic discharge Expired - Fee Related US6981234B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002328786A JP2004165385A (en) 2002-11-12 2002-11-12 ITO lead wiring method capable of suppressing high volt static voltage discharge in IC
US10/304,736 US6981234B2 (en) 2002-11-12 2002-11-27 Method of ITO layout to make IC bear the high-volt electrostatic discharge

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002328786A JP2004165385A (en) 2002-11-12 2002-11-12 ITO lead wiring method capable of suppressing high volt static voltage discharge in IC
US10/304,736 US6981234B2 (en) 2002-11-12 2002-11-27 Method of ITO layout to make IC bear the high-volt electrostatic discharge

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100733509B1 (en) * 2002-12-04 2007-06-28 윈테크 코포레이션 Improved Antistatic Method Using ITIO Line Design

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160055368A (en) 2014-11-07 2016-05-18 삼성디스플레이 주식회사 Display apparatus and method of driving the same

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559614A (en) * 1995-05-01 1996-09-24 Motorola, Inc. Liquid crystal display with integral heater and method of fabricating same
US5949502A (en) * 1995-08-07 1999-09-07 Hitachi, Ltd. Liquid crystal device having resistor elements
US6040812A (en) * 1996-06-19 2000-03-21 Xerox Corporation Active matrix display with integrated drive circuitry
US20020044329A1 (en) * 2000-08-10 2002-04-18 Hitoshi Shoji Electrooptical unit and electronic apparatus
US20020047982A1 (en) * 2000-09-12 2002-04-25 Hitachi, Ltd. Liquid crystal display
US6437764B1 (en) * 1998-06-29 2002-08-20 Hitachi, Ltd. Liquid crystal display device
US6525342B2 (en) * 2001-05-23 2003-02-25 International Business Machines Corporation Low resistance wiring in the periphery region of displays
US20030107696A1 (en) * 2001-12-07 2003-06-12 Samsung Electronics Co., Ltd. Liquid crystal display
US20030107565A1 (en) * 2001-11-20 2003-06-12 International Business Machines Corporation Active matrix oled voltage drive pixel circuit
US6680761B1 (en) * 2000-01-24 2004-01-20 Rainbow Displays, Inc. Tiled flat-panel display having visually imperceptible seams, optimized for HDTV applications
US20040055785A1 (en) * 2000-12-29 2004-03-25 Amir Ben-Shalom Fat conductor

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559614A (en) * 1995-05-01 1996-09-24 Motorola, Inc. Liquid crystal display with integral heater and method of fabricating same
US5949502A (en) * 1995-08-07 1999-09-07 Hitachi, Ltd. Liquid crystal device having resistor elements
US6040812A (en) * 1996-06-19 2000-03-21 Xerox Corporation Active matrix display with integrated drive circuitry
US6437764B1 (en) * 1998-06-29 2002-08-20 Hitachi, Ltd. Liquid crystal display device
US6680761B1 (en) * 2000-01-24 2004-01-20 Rainbow Displays, Inc. Tiled flat-panel display having visually imperceptible seams, optimized for HDTV applications
US20020044329A1 (en) * 2000-08-10 2002-04-18 Hitoshi Shoji Electrooptical unit and electronic apparatus
US20020047982A1 (en) * 2000-09-12 2002-04-25 Hitachi, Ltd. Liquid crystal display
US20040055785A1 (en) * 2000-12-29 2004-03-25 Amir Ben-Shalom Fat conductor
US6525342B2 (en) * 2001-05-23 2003-02-25 International Business Machines Corporation Low resistance wiring in the periphery region of displays
US20030107565A1 (en) * 2001-11-20 2003-06-12 International Business Machines Corporation Active matrix oled voltage drive pixel circuit
US20030107696A1 (en) * 2001-12-07 2003-06-12 Samsung Electronics Co., Ltd. Liquid crystal display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100733509B1 (en) * 2002-12-04 2007-06-28 윈테크 코포레이션 Improved Antistatic Method Using ITIO Line Design

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US6981234B2 (en) 2005-12-27

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