[go: up one dir, main page]

US20040014292A1 - Sub-micron MOS transistor - Google Patents

Sub-micron MOS transistor Download PDF

Info

Publication number
US20040014292A1
US20040014292A1 US10/621,852 US62185203A US2004014292A1 US 20040014292 A1 US20040014292 A1 US 20040014292A1 US 62185203 A US62185203 A US 62185203A US 2004014292 A1 US2004014292 A1 US 2004014292A1
Authority
US
United States
Prior art keywords
depositing
layer
region
selective etchable
selective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/621,852
Inventor
Yanjun Ma
David Evans
Yoshi Ono
Sheng Hsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/621,852 priority Critical patent/US20040014292A1/en
Publication of US20040014292A1 publication Critical patent/US20040014292A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D64/01318—
    • H10D64/0132—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0179—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10W20/0698—
    • H10W20/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H10W20/069—

Definitions

  • This invention relates to MOS Transistor and IC fabrication method, and specifically to the use of a nitride undercut to form a sub-micron MOS.
  • LDD Lightly doped
  • a method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure.
  • a sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.
  • An object of the invention is to provide a method of fabrication for sub-micron transistors.
  • Another object of the invention is to provide a simplified LDD process.
  • FIGS. 1 - 4 depicts steps in the method of the invention.
  • FIG. 5 depicts a sub-micron MOS transistor constructed according to the method of the invention.
  • n-channel MOS transistor is used as an example to describe the method of the invention, however, the structure and fabrication process is also applicable to p-channel MOS transistors and CMOS integration.
  • a structure 10 constructed according to the method of the invention is fabricated using state-of-the-art processes on a p-type substrate 12 to form an n-well, a p-well, to adjust the voltage threshold in an active region 14 , and to provide device isolation, as by oxide regions 16 .
  • a gate oxide layer 18 is formed, and a layer of silicon nitride (Si 3 N 4 ), or polysilicon, 20 , also referred to herein as a first selective etchable layer is deposited to a thickness of between about 200 nm to 500 nm.
  • a thin layer of oxide 22 also referred to herein as a second selective etchable layer, is deposited over the nitride layer to a thickness of between about 20 nm to 100 nm.
  • oxide layer 22 and silicon nitride, or polysilicon, layer 20 , or polysilicon are followed by photo lithography and anisotropic plasma etching of oxide layer 22 and silicon nitride, or polysilicon, layer 20 , or polysilicon, wherein the etching stops at the level of gate oxide 18 .
  • Gate oxide layer 18 may be partially etched, or may be completely removed during this etching process.
  • the remaining silicon nitride, or polysilicon, layer forms a replacement cast for a gate electrode, which will be formed in a subsequent step. Any remaining photoresist is then removed, resulting in the structure shown generally at 10 in FIG. 2.
  • nitride layer 20 is partially etched using phosphoric acid, which has a high selectivity over oxide, i.e., the phosphoric acid will remove silicon nitride considerably faster than it will remove silicon oxide, resulting in the structure of FIG. 3.
  • the gate length is shortened by two-times the thickness of the nitride etched, resulting in a device having a shorter channel, for instance, a gate length of 100 nm results from an initial nitride deposition having a length of 200 nm, of which 50 nm is removed by etching.
  • the gate oxide In the case where polysilicon is used as a replacement cast, the gate oxide must not be completely removed during the gate etching process. Polysilicon may be selectively etched by using diluted HNO 3 /HF solution. Additionally, the oxide layer 22 may be replaced with silicon nitride to achieve higher etching selectivity. In this case, silicon nitride is deposited to a thickness of between about 20 nm to 100 nm.
  • a source region 24 and a drain region 26 is formed in active region 16 by ion implantation adjacent a gate region 27 .
  • Arsenic ions are implanted at a dose of between about 1-10 15 cm ⁇ 2 to 5-10 15 cm ⁇ 2 , and an energy level of between about 30 keV to 70 keV. Because of overhanging oxide 22 , the implantation depth and dose is reduced in the region under the overhanging oxide, which results in an LDD source region 24 a and an LDD drain region 26 a adjacent gate region 27 , without an additional implantation step.
  • the implanted profile in this region is a function of implant energy, dose, and the thickness of the oxide.
  • the ion concentration in the source region 24 and drain region 26 is between about 1-10 20 cm ⁇ 3 to 1-10 21 cm ⁇ 3
  • the ion concentration in LDD source region 24 a and LDD drain region 26 a is between about 5-10 18 cm ⁇ 3 to 5-10 9 cm ⁇ 3
  • the gate may be heavily doped polysilicon or metal.
  • the next step is to CVD an oxide layer 28 to a thickness of between about 1.5 times to two times the thickness of silicon nitride layer 20 .
  • the structure is planarized by CMP, stopping at the level of silicon nitride layer 20 .
  • a high selectivity slurry is desirable for this process.
  • Nitride layer 90 is etched to remove it, and doped polysilicon or metal 30 is deposited and CMP planarized to form a gate electrode.
  • An oxide layer 32 is deposited by CVD, and a source electrode 34 and a drain electrode is formed, resulting in the structure shown generally at 38 in FIG. 5.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of application Ser. No. 09/783,760, filed Feb. 14, 2001, entitled “Structure and Method of Making a Sub-Micron MOS Transistor,” invented by Ma et al, which is a continuation-in-part of application Ser. No. 09/004,991, filed Jan. 9, 1998, now issued as U.S. Letters Pat. No. 6,274,421 entitled “Method of Making Metal Gate Sub-Micron MOS Transistor,” invented by Hsu et al.[0001]
    • FIELD OF THE INVENTION
  • This invention relates to MOS Transistor and IC fabrication method, and specifically to the use of a nitride undercut to form a sub-micron MOS. [0002]
    • BACKGROUND OF THE INVENTION
  • The use of chemical etching to provide a controllable undercut has been used to produce conventional MOS transistors, which is known as a “T-gate” structure. A nitride undercut, using phosphoric acid, has been used specifically in the fabrication of triple implanted bipolar transistors, however, this process is not widely used now because of controllability issues required to manufacture ICs using current technology. The nitride undercutting process may remain a useful process in a certain application, such as in the manufacture of sub-micron MOS transistors. [0003]
  • Lightly doped (LDD) structures are widely used in state-of-the-art IC fabrication. The usual LDD process requires two implantation steps, however, one of the implantation steps is eliminated using the LDD method of the invention. [0004]
    • SUMMARY OF THE INVENTION
  • A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. [0005]
  • A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region. [0006]
  • An object of the invention is to provide a method of fabrication for sub-micron transistors. [0007]
  • Another object of the invention is to provide a simplified LDD process. [0008]
  • This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.[0009]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. [0010] 1-4 depicts steps in the method of the invention.
  • FIG. 5 depicts a sub-micron MOS transistor constructed according to the method of the invention.[0011]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • An n-channel MOS transistor is used as an example to describe the method of the invention, however, the structure and fabrication process is also applicable to p-channel MOS transistors and CMOS integration. [0012]
  • Referring to FIG. 1, a [0013] structure 10 constructed according to the method of the invention is fabricated using state-of-the-art processes on a p-type substrate 12 to form an n-well, a p-well, to adjust the voltage threshold in an active region 14, and to provide device isolation, as by oxide regions 16.
  • Turning to FIG. 2, a [0014] gate oxide layer 18 is formed, and a layer of silicon nitride (Si3N4), or polysilicon, 20, also referred to herein as a first selective etchable layer is deposited to a thickness of between about 200 nm to 500 nm. A thin layer of oxide 22, also referred to herein as a second selective etchable layer, is deposited over the nitride layer to a thickness of between about 20 nm to 100 nm.
  • This is followed by photo lithography and anisotropic plasma etching of [0015] oxide layer 22 and silicon nitride, or polysilicon, layer 20, or polysilicon, wherein the etching stops at the level of gate oxide 18. Gate oxide layer 18 may be partially etched, or may be completely removed during this etching process. The remaining silicon nitride, or polysilicon, layer forms a replacement cast for a gate electrode, which will be formed in a subsequent step. Any remaining photoresist is then removed, resulting in the structure shown generally at 10 in FIG. 2.
  • Referring now to FIG. 3, [0016] nitride layer 20 is partially etched using phosphoric acid, which has a high selectivity over oxide, i.e., the phosphoric acid will remove silicon nitride considerably faster than it will remove silicon oxide, resulting in the structure of FIG. 3. The gate length is shortened by two-times the thickness of the nitride etched, resulting in a device having a shorter channel, for instance, a gate length of 100 nm results from an initial nitride deposition having a length of 200 nm, of which 50 nm is removed by etching.
  • In the case where polysilicon is used as a replacement cast, the gate oxide must not be completely removed during the gate etching process. Polysilicon may be selectively etched by using diluted HNO[0017] 3/HF solution. Additionally, the oxide layer 22 may be replaced with silicon nitride to achieve higher etching selectivity. In this case, silicon nitride is deposited to a thickness of between about 20 nm to 100 nm.
  • A [0018] source region 24 and a drain region 26 is formed in active region 16 by ion implantation adjacent a gate region 27. In the preferred embodiment, Arsenic ions are implanted at a dose of between about 1-1015 cm−2 to 5-1015 cm−2, and an energy level of between about 30 keV to 70 keV. Because of overhanging oxide 22, the implantation depth and dose is reduced in the region under the overhanging oxide, which results in an LDD source region 24 a and an LDD drain region 26 a adjacent gate region 27, without an additional implantation step. The implanted profile in this region is a function of implant energy, dose, and the thickness of the oxide. For instance, the ion concentration in the source region 24 and drain region 26 is between about 1-1020 cm−3 to 1-1021 cm−3, while the ion concentration in LDD source region 24 a and LDD drain region 26 a is between about 5-1018 cm−3 to 5-109 cm−3. The gate may be heavily doped polysilicon or metal.
  • The next step is to CVD an [0019] oxide layer 28 to a thickness of between about 1.5 times to two times the thickness of silicon nitride layer 20. The structure is planarized by CMP, stopping at the level of silicon nitride layer 20. A high selectivity slurry is desirable for this process. Nitride layer 90 is etched to remove it, and doped polysilicon or metal 30 is deposited and CMP planarized to form a gate electrode. An oxide layer 32 is deposited by CVD, and a source electrode 34 and a drain electrode is formed, resulting in the structure shown generally at 38 in FIG. 5.
  • The remainder of the process proceeds as described in an earlier patent disclosure by Hsu and Evans describing the nitride replacement or “cast” process. For conventional polysilicon gate fabrication, standard processing, which is well known to those of ordinary skill in the art, is performed. [0020]
  • Thus, a structure and a method for fabricating a sub-micron MOS transistor using, a silicon nitride or polysilicon undercut process has been disclosed. It will be appreciated that farther variations and modifications thereof may be made within the scope of the invention as defined in the appended claims. [0021]

Claims (17)

We claim:
1. A method of fabricating a sub-micron MOS transistor comprising:
preparing a substrate, including isolating an active region therein;
depositing a gate oxide layer;
depositing a first selective etchable layer over the gate oxide layer;
depositing a second selective etchable layer over the first selective etchable layer;
etching the structure to undercut the first selective etchable layer;
implanting ions in the active region to form a source region and a drain region;
removing the remaining first selective etchable layer and the second selective etchable layer;
depositing a gate electrode; and
depositing oxide and metallizing the structure.
2. The method of claim 1 wherein said depositing, a first selective etchable layer includes depositing a layer of silicon nitride, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon oxide.
3. The method of claim 1 wherein said depositing a first selective etchable layer includes depositing a layer of polysilicon, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon nitride.
4. The method of claim 1 wherein said depositing a first selective etchable layer includes depositing a layer of polysilicon, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon oxide.
5. The method of claim 1 wherein said depositing a gate electrode includes depositing a layer of material taken from the group of materials consisting of doped polysilicon and metal.
6. The method of claim 1 wherein said implanting includes implanting Arsenic ions at a dose of between about 1-1015 cm−2 to 5-1015 cm−2, and an energy level of between about 30 keV to 70 keV.
7. The method of claim 6 wherein said implanting includes forming a LDD source region and an LDD drain region adjacent the gate region.
8. The method of claim 7 wherein said implanting includes implanting ions to provide an ion concentration in the source region and in the drain region of between about 1-1020 cm−3 to 1-1021 cm−3, and wherein the ion concentration the LDD source region and in the LDD drain re(ion is between about 5-10 18 cm−3 to 5-1018 cm−3.
9. A method of fabricating a sub-micron MOS transistor comprising:
preparing a substrate, including isolating an active region therein;
depositing a (rate oxide layer;
depositing a first selective etchable layer over the gate oxide layer;
depositing a second selective etchable layer over the first selective etchable layer;
etching the structure to undercut the first selective etchable layer;
implanting ions in the active region to form a source region and a drain region, including forming a LDD source region and an LDD drain region adjacent the gate region;
removing, the remaining first selective etchable layer and the second selective etchable layer;
depositing a gate electrode; and
depositing oxide and metallizing the structure.
10. The method of claim 9 wherein said depositing a first selective etchable layer includes depositing a layer of silicon nitride to a thickness of between about 200 nm to 500 nm, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon oxide to a thickness of between about 20 nm to 100 nm.
11. The method of claim 9 wherein said depositing a first selective etchable layer includes depositing a layer of polysilicon, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon nitride, wherein the thickness of both layers is between about 200 nm and 500 nm.
12. The method of claim 9 wherein said depositing a first selective etchable layer includes depositing a layer of polysilicon to a thickness of between about 200 nm to 500 nm, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon oxide to a thickness of between about 20 nm to 100 nm.
13. The method of claim 9 wherein said depositing a gate electrode includes depositing a layer of material taken from the group of materials consisting of doped polysilicon and metal.
14. The method of claim 9 wherein said implanting includes implanting, Arsenic ions at a dose of between about 1-1015 cm−2 to 5-1015 cm−2, and an energy level of between about 30 keV to 70 keV.
15. The method of claim 9 wherein said implanting includes implanting ions to provide an ion concentration in the source region and in the drain region of between about 1-1020 cm−3 to 1-1021 cm−3, and wherein the ion concentration the LDD source region and in the LDD drain region is between about 5-1018 cm−3 to 5-1019 cm−3.
16. A sub-micron MOS transistor comprising:
a substrate; and
an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region; wherein the ion concentration in said source region and in said drain region is between about 1-1020 cm−3 to 1-1021 cm−3, and wherein the ion concentration in said LDD source region and in said LDD drain region is between about 5-1018 cm−3 to 5-1019 cm−3.
17. The MOS transistor of claim 16 which further includes an insulating oxide layer thereover and a source electrode, a gate electrode and a drain electrode.
US10/621,852 1998-01-09 2003-07-16 Sub-micron MOS transistor Abandoned US20040014292A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/621,852 US20040014292A1 (en) 1998-01-09 2003-07-16 Sub-micron MOS transistor

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/004,991 US6274421B1 (en) 1998-01-09 1998-01-09 Method of making metal gate sub-micron MOS transistor
US09/783,760 US6632731B2 (en) 1998-01-09 2001-02-14 Structure and method of making a sub-micron MOS transistor
US10/621,852 US20040014292A1 (en) 1998-01-09 2003-07-16 Sub-micron MOS transistor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/783,760 Division US6632731B2 (en) 1998-01-09 2001-02-14 Structure and method of making a sub-micron MOS transistor

Publications (1)

Publication Number Publication Date
US20040014292A1 true US20040014292A1 (en) 2004-01-22

Family

ID=21713564

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/004,991 Expired - Fee Related US6274421B1 (en) 1998-01-09 1998-01-09 Method of making metal gate sub-micron MOS transistor
US09/783,760 Expired - Fee Related US6632731B2 (en) 1998-01-09 2001-02-14 Structure and method of making a sub-micron MOS transistor
US10/621,852 Abandoned US20040014292A1 (en) 1998-01-09 2003-07-16 Sub-micron MOS transistor

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US09/004,991 Expired - Fee Related US6274421B1 (en) 1998-01-09 1998-01-09 Method of making metal gate sub-micron MOS transistor
US09/783,760 Expired - Fee Related US6632731B2 (en) 1998-01-09 2001-02-14 Structure and method of making a sub-micron MOS transistor

Country Status (5)

Country Link
US (3) US6274421B1 (en)
EP (1) EP0929105A3 (en)
JP (1) JPH11224949A (en)
KR (1) KR100352715B1 (en)
TW (1) TW434901B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432258B2 (en) 2006-07-20 2008-10-07 Smithkline Beecham Corporation Morpholinyl and pyrrolidinyl analogs

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100624961B1 (en) * 1999-10-20 2006-09-19 주식회사 하이닉스반도체 Transistor manufacturing method employing metal gate
TW514992B (en) 1999-12-17 2002-12-21 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
US6607950B2 (en) 2000-03-30 2003-08-19 Interuniversitair Microelektronic Centrum (Imec) MIS transistors with a metal gate and high-k dielectric and method of forming
US7008832B1 (en) 2000-07-20 2006-03-07 Advanced Micro Devices, Inc. Damascene process for a T-shaped gate electrode
US6417084B1 (en) * 2000-07-20 2002-07-09 Advanced Micro Devices, Inc. T-gate formation using a modified conventional poly process
US6509282B1 (en) 2001-11-26 2003-01-21 Advanced Micro Devices, Inc. Silicon-starved PECVD method for metal gate electrode dielectric spacer
WO2004012256A1 (en) * 2002-07-31 2004-02-05 Advanced Micro Devices, Inc. Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith
JP2004152790A (en) * 2002-10-28 2004-05-27 Toshiba Corp Semiconductor device and method of manufacturing semiconductor device
US7388259B2 (en) * 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US7078298B2 (en) * 2003-05-20 2006-07-18 Sharp Laboratories Of America, Inc. Silicon-on-nothing fabrication process
US6887798B2 (en) * 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
KR100481185B1 (en) 2003-07-10 2005-04-07 삼성전자주식회사 Method of fabricating a MOS transistor using a total gate silicidation process
US7410846B2 (en) * 2003-09-09 2008-08-12 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate
US6890808B2 (en) * 2003-09-10 2005-05-10 International Business Machines Corporation Method and structure for improved MOSFETs using poly/silicide gate height control
US6887751B2 (en) * 2003-09-12 2005-05-03 International Business Machines Corporation MOSFET performance improvement using deformation in SOI structure
US7170126B2 (en) 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US7144767B2 (en) * 2003-09-23 2006-12-05 International Business Machines Corporation NFETs using gate induced stress modulation
US7119403B2 (en) 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US7037770B2 (en) * 2003-10-20 2006-05-02 International Business Machines Corporation Method of manufacturing strained dislocation-free channels for CMOS
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7129126B2 (en) * 2003-11-05 2006-10-31 International Business Machines Corporation Method and structure for forming strained Si for CMOS devices
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7029964B2 (en) * 2003-11-13 2006-04-18 International Business Machines Corporation Method of manufacturing a strained silicon on a SiGe on SOI substrate
US7122849B2 (en) 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7247534B2 (en) * 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7198995B2 (en) 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7202132B2 (en) 2004-01-16 2007-04-10 International Business Machines Corporation Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs
US7381609B2 (en) 2004-01-16 2008-06-03 International Business Machines Corporation Method and structure for controlling stress in a transistor channel
US7118999B2 (en) * 2004-01-16 2006-10-10 International Business Machines Corporation Method and apparatus to increase strain effect in a transistor channel
US7923782B2 (en) 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
US7205206B2 (en) * 2004-03-03 2007-04-17 International Business Machines Corporation Method of fabricating mobility enhanced CMOS devices
US7504693B2 (en) * 2004-04-23 2009-03-17 International Business Machines Corporation Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering
US7223994B2 (en) * 2004-06-03 2007-05-29 International Business Machines Corporation Strained Si on multiple materials for bulk or SOI substrates
US7037794B2 (en) 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
US7227205B2 (en) 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
TWI463526B (en) 2004-06-24 2014-12-01 萬國商業機器公司 Method for improving stress-induced CMOS components and components prepared by the method
US7288443B2 (en) * 2004-06-29 2007-10-30 International Business Machines Corporation Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension
US7217949B2 (en) 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7384829B2 (en) 2004-07-23 2008-06-10 International Business Machines Corporation Patterned strained semiconductor substrate and device
CN100539035C (en) * 2004-09-10 2009-09-09 中芯国际集成电路制造(上海)有限公司 The new caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer
US7338907B2 (en) * 2004-10-04 2008-03-04 Sharp Laboratories Of America, Inc. Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications
US7238565B2 (en) 2004-12-08 2007-07-03 International Business Machines Corporation Methodology for recovery of hot carrier induced degradation in bipolar devices
US7262087B2 (en) * 2004-12-14 2007-08-28 International Business Machines Corporation Dual stressed SOI substrates
US7173312B2 (en) * 2004-12-15 2007-02-06 International Business Machines Corporation Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
US7274084B2 (en) * 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US20060160317A1 (en) * 2005-01-18 2006-07-20 International Business Machines Corporation Structure and method to enhance stress in a channel of cmos devices using a thin gate
US7432553B2 (en) * 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7220626B2 (en) * 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7256081B2 (en) * 2005-02-01 2007-08-14 International Business Machines Corporation Structure and method to induce strain in a semiconductor device channel with stressed film under the gate
US7224033B2 (en) 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
US7545004B2 (en) * 2005-04-12 2009-06-09 International Business Machines Corporation Method and structure for forming strained devices
US7544577B2 (en) * 2005-08-26 2009-06-09 International Business Machines Corporation Mobility enhancement in SiGe heterojunction bipolar transistors
US7202513B1 (en) 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US20070096170A1 (en) * 2005-11-02 2007-05-03 International Business Machines Corporation Low modulus spacers for channel stress enhancement
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7785950B2 (en) * 2005-11-10 2010-08-31 International Business Machines Corporation Dual stress memory technique method and related structure
US7709317B2 (en) 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
US7348638B2 (en) * 2005-11-14 2008-03-25 International Business Machines Corporation Rotational shear stress for charge carrier mobility modification
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7776695B2 (en) * 2006-01-09 2010-08-17 International Business Machines Corporation Semiconductor device structure having low and high performance devices of same conductive type on same substrate
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
US7635620B2 (en) 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US20070158743A1 (en) * 2006-01-11 2007-07-12 International Business Machines Corporation Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
US7691698B2 (en) * 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US8461009B2 (en) * 2006-02-28 2013-06-11 International Business Machines Corporation Spacer and process to enhance the strain in the channel with stress liner
US7608489B2 (en) * 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7615418B2 (en) * 2006-04-28 2009-11-10 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7521307B2 (en) * 2006-04-28 2009-04-21 International Business Machines Corporation CMOS structures and methods using self-aligned dual stressed layers
US8853746B2 (en) 2006-06-29 2014-10-07 International Business Machines Corporation CMOS devices with stressed channel regions, and methods for fabricating the same
US7790540B2 (en) 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
US8754446B2 (en) 2006-08-30 2014-06-17 International Business Machines Corporation Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material
US7462522B2 (en) * 2006-08-30 2008-12-09 International Business Machines Corporation Method and structure for improving device performance variation in dual stress liner technology
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
KR100927398B1 (en) * 2007-06-26 2009-11-19 주식회사 하이닉스반도체 Method for forming fine pattern of semiconductor device
US8115254B2 (en) 2007-09-25 2012-02-14 International Business Machines Corporation Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
US8492846B2 (en) * 2007-11-15 2013-07-23 International Business Machines Corporation Stress-generating shallow trench isolation structure having dual composition
CN102157437B (en) * 2010-02-11 2013-12-25 中国科学院微电子研究所 Method for forming semiconductor structure
US8598006B2 (en) * 2010-03-16 2013-12-03 International Business Machines Corporation Strain preserving ion implantation methods
KR102044667B1 (en) * 2013-05-28 2019-11-14 엘지디스플레이 주식회사 Flat panel display device having oxide thin film transistor and method for fabricating thereof
KR20150091895A (en) * 2014-02-04 2015-08-12 에스케이하이닉스 주식회사 Semiconductor device and method of operating the same
WO2021035420A1 (en) 2019-08-23 2021-03-04 京东方科技集团股份有限公司 Display panel and manufacturing method therefor, and display device
CN105185816A (en) * 2015-10-15 2015-12-23 京东方科技集团股份有限公司 Array substrate, manufacturing method, and display device
US11600234B2 (en) 2015-10-15 2023-03-07 Ordos Yuansheng Optoelectronics Co., Ltd. Display substrate and driving method thereof
WO2021035414A1 (en) 2019-08-23 2021-03-04 京东方科技集团股份有限公司 Pixel circuit and driving method therefor, and display substrate and driving method therefor, and display device
WO2021035415A1 (en) 2019-08-23 2021-03-04 京东方科技集团股份有限公司 Display device and manufacturing method therefor
WO2021035529A1 (en) 2019-08-27 2021-03-04 京东方科技集团股份有限公司 Electronic device substrate and method for manufacture and electronic device thereof
CN109979984B (en) * 2017-12-27 2023-08-29 深圳尚阳通科技股份有限公司 Superjunction device and method of manufacturing the same
CN114864647B (en) 2019-08-23 2025-03-28 京东方科技集团股份有限公司 Display device and method for manufacturing the same
US12120914B2 (en) 2019-08-23 2024-10-15 Boe Technology Group Co., Ltd. Display device and manufacturing method thereof
US12266303B2 (en) 2019-08-23 2025-04-01 Boe Technology Group Co., Ltd. Display device and manufacturing method thereof
KR20220049031A (en) 2019-08-23 2022-04-20 보에 테크놀로지 그룹 컴퍼니 리미티드 Display device, manufacturing method thereof, and driving board

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146291A (en) * 1988-08-31 1992-09-08 Mitsubishi Denki Kabushiki Kaisha MIS device having lightly doped drain structure
US5159417A (en) * 1990-04-16 1992-10-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having short channel field effect transistor with extended gate electrode structure and manufacturing method thereof
US5212102A (en) * 1990-08-22 1993-05-18 National Semiconductor Corporation Method of making polysilicon Schottky clamped transistor and vertical fuse devices
US5219770A (en) * 1983-11-30 1993-06-15 Fujitsu Limited Method for fabricating a MISFET including a common contact window
US6010929A (en) * 1996-12-11 2000-01-04 Texas Instruments Incorporated Method for forming high voltage and low voltage transistors on the same substrate
US6235564B1 (en) * 1999-07-27 2001-05-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing MISFET
US20020045307A1 (en) * 1997-07-03 2002-04-18 Jorge Kittl Method of forming a silicide layer using metallic impurities and pre-amorphization

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617824A (en) * 1965-07-12 1971-11-02 Nippon Electric Co Mos device with a metal-silicide gate
US4337476A (en) * 1980-08-18 1982-06-29 Bell Telephone Laboratories, Incorporated Silicon rich refractory silicides as gate metal
US4702792A (en) 1985-10-28 1987-10-27 International Business Machines Corporation Method of forming fine conductive lines, patterns and connectors
US4944836A (en) 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US4694565A (en) * 1986-04-28 1987-09-22 Rockwell International Corporation Method of making hardened CMOS sub-micron field effect transistors
DE3685495D1 (en) * 1986-07-11 1992-07-02 Ibm METHOD FOR PRODUCING A UNDERLYED MASK CONTOUR.
US4849376A (en) * 1987-01-12 1989-07-18 Itt A Division Of Itt Corporation Gallium Arsenide Technology Center Self-aligned refractory gate process with self-limiting undercut of an implant mask
JP2807226B2 (en) * 1987-09-12 1998-10-08 ソニー株式会社 Method for manufacturing semiconductor device
US4914500A (en) * 1987-12-04 1990-04-03 At&T Bell Laboratories Method for fabricating semiconductor devices which include sources and drains having metal-containing material regions, and the resulting devices
US4954142A (en) 1989-03-07 1990-09-04 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US4956311A (en) * 1989-06-27 1990-09-11 National Semiconductor Corporation Double-diffused drain CMOS process using a counterdoping technique
US5281769A (en) 1990-11-05 1994-01-25 Nippon Telegraph And Telephone Corporation Dewall plating technique
KR100274555B1 (en) * 1991-06-26 2000-12-15 윌리엄 비. 켐플러 Insulated gate field effect transistor and manufacturing the same
JP3023933B2 (en) * 1991-06-28 2000-03-21 株式会社村田製作所 Method for manufacturing semiconductor device
US5196357A (en) * 1991-11-18 1993-03-23 Vlsi Technology, Inc. Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor
US5334545A (en) * 1993-02-01 1994-08-02 Allied Signal Inc. Process for forming self-aligning cobalt silicide T-gates of silicon MOS devices
US5451546A (en) 1994-03-10 1995-09-19 National Semiconductor Corporation Masking method used in salicide process for improved yield by preventing damage to oxide spacers
KR0148296B1 (en) 1994-07-28 1998-12-01 문정환 Isolation Method of Semiconductor Devices
US5656519A (en) 1995-02-14 1997-08-12 Nec Corporation Method for manufacturing salicide semiconductor device
JP2663905B2 (en) * 1995-03-30 1997-10-15 日本電気株式会社 Method for manufacturing semiconductor device
JP3093620B2 (en) * 1995-10-19 2000-10-03 日本電気株式会社 Method for manufacturing semiconductor device
US5767004A (en) * 1996-04-22 1998-06-16 Chartered Semiconductor Manufacturing, Ltd. Method for forming a low impurity diffusion polysilicon layer
US5858843A (en) 1996-09-27 1999-01-12 Intel Corporation Low temperature method of forming gate electrode and gate dielectric
TW358989B (en) 1997-04-08 1999-05-21 United Microelectronics Corp Method of forming gold-oxygen semiconductor cells
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
TW423080B (en) * 1997-11-08 2001-02-21 Winbond Electronics Corp Semiconductor device and its manufacturing method
US5966597A (en) * 1998-01-06 1999-10-12 Altera Corporation Method of forming low resistance gate electrodes
US6069387A (en) * 1998-04-06 2000-05-30 Advanced Micro Devices, Inc. Lightly doped drain formation integrated with source/drain formation for high-performance transistor formation
JP2000091350A (en) * 1998-09-11 2000-03-31 Japan Radio Co Ltd Method for manufacturing semiconductor field effect transistor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5219770A (en) * 1983-11-30 1993-06-15 Fujitsu Limited Method for fabricating a MISFET including a common contact window
US5146291A (en) * 1988-08-31 1992-09-08 Mitsubishi Denki Kabushiki Kaisha MIS device having lightly doped drain structure
US5159417A (en) * 1990-04-16 1992-10-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having short channel field effect transistor with extended gate electrode structure and manufacturing method thereof
US5212102A (en) * 1990-08-22 1993-05-18 National Semiconductor Corporation Method of making polysilicon Schottky clamped transistor and vertical fuse devices
US6010929A (en) * 1996-12-11 2000-01-04 Texas Instruments Incorporated Method for forming high voltage and low voltage transistors on the same substrate
US20020045307A1 (en) * 1997-07-03 2002-04-18 Jorge Kittl Method of forming a silicide layer using metallic impurities and pre-amorphization
US6235564B1 (en) * 1999-07-27 2001-05-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing MISFET

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432258B2 (en) 2006-07-20 2008-10-07 Smithkline Beecham Corporation Morpholinyl and pyrrolidinyl analogs

Also Published As

Publication number Publication date
US20010009784A1 (en) 2001-07-26
EP0929105A2 (en) 1999-07-14
EP0929105A3 (en) 1999-12-22
JPH11224949A (en) 1999-08-17
KR100352715B1 (en) 2003-03-26
US6274421B1 (en) 2001-08-14
TW434901B (en) 2001-05-16
US6632731B2 (en) 2003-10-14
KR19990066850A (en) 1999-08-16

Similar Documents

Publication Publication Date Title
US6632731B2 (en) Structure and method of making a sub-micron MOS transistor
US6573134B2 (en) Dual metal gate CMOS devices and method for making the same
US6153455A (en) Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer
US4760033A (en) Method for the manufacture of complementary MOS field effect transistors in VLSI technology
US5610088A (en) Method of fabricating field effect transistors having lightly doped drain regions
JP2663402B2 (en) Method for manufacturing CMOS integrated circuit device
US6514810B1 (en) Buried channel PMOS transistor in dual gate CMOS with reduced masking steps
EP0715344A2 (en) Process for forming gate oxides possessing different thicknesses on a semiconductor substrate
EP0749165A2 (en) Thin film transistor in insulated semiconductor substrate and manufacturing method thereof
US6033958A (en) Method of fabricating dual voltage MOS transistors
JPH08250715A (en) Method for manufacturing semiconductor device
US6261888B1 (en) Method of forming CMOS integrated circuitry
US4509991A (en) Single mask process for fabricating CMOS structure
US6630716B1 (en) Disposable spacer
US7276407B2 (en) Method for fabricating semiconductor device
JPH09181158A (en) Method for manufacturing semiconductor device
US5994743A (en) Semiconductor device having different sidewall widths and different source/drain depths for NMOS & PMOS structures
US20030203550A1 (en) Method of angle implant to improve transistor reverse narrow width effect
US20040137688A1 (en) Semiconductor device with tapered gate and process for fabricating the device
US5821146A (en) Method of fabricating FET or CMOS transistors using MeV implantation
JP3200231B2 (en) Method for manufacturing semiconductor device
EP0527372A1 (en) Manufacturing method for a bipolar transistor
JPH05267331A (en) Manufacture of mos semiconductor device
US20020061617A1 (en) Fabrication method of a dual-gate cmosfet
US6110788A (en) Surface channel MOS transistors, methods for making the same, and semiconductor devices containing the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION