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US20030030051A1 - Superjunction device with improved avalanche capability and breakdown voltage - Google Patents

Superjunction device with improved avalanche capability and breakdown voltage Download PDF

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Publication number
US20030030051A1
US20030030051A1 US09/927,027 US92702701A US2003030051A1 US 20030030051 A1 US20030030051 A1 US 20030030051A1 US 92702701 A US92702701 A US 92702701A US 2003030051 A1 US2003030051 A1 US 2003030051A1
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Prior art keywords
columns
dose
column
silicon
die
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/927,027
Inventor
Ming Zhou
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Priority to US09/927,027 priority Critical patent/US20030030051A1/en
Assigned to INTERNATIONAL RECTIFIER CORPORATION reassignment INTERNATIONAL RECTIFIER CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZHOU MING
Priority to AU2002367714A priority patent/AU2002367714A1/en
Priority to PCT/US2002/022171 priority patent/WO2003088312A2/en
Publication of US20030030051A1 publication Critical patent/US20030030051A1/en
Priority to US10/383,434 priority patent/US6768170B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • This invention relates to semiconductor devices and more specifically relates to a superjunction type power MOSFET with increased avalanche energy.
  • the avalanche capability is determined mainly by the means of preventing the turn on of the inherent parasitic bipolar transistor in a DMOS type MOSgated device.
  • the concentration of the P type columns is chosen to maintain charge balance in the active area of the epitaxial silicon body material. This requirement lowers the avalanche capability of the device because the high field locates in the N type region of the epitaxial silicon layer, resulting in a higher base resistance R b 1 in the avalanche current path through the N type region and to the N+ source.
  • avalanche energy that is, the amount of energy which is produced in avalanche without failure, has been as low as 50 millijoules. Attempts to increase this energy results in a reduction of the device breakdown voltage.
  • the P column dose in a superjunction device is increased to a value intentionally higher than that required for charge balance in apparent disregard of the accepted theory and design rules for superjunction devices.
  • the high field location moves from the N region to the P column, and, therefore, a lower R b 1 or lateral base resistance is experienced by the avalanche current through the P column to the source.
  • the avalanche capability of the device is significantly improved (by a factor greater than 10) without degrading breakdown voltage.
  • the P column dose was increased to 1.1E13 and avalanche energy was increased from 50 millijoules to 2500 millijoules.
  • the P column dose to be used is dependent on die size and it was found that a higher dose can be used on smaller area die.
  • a P column dose of 1.2E13 was used for a die of size 110 ⁇ 140 mils; while a dose of 1.1E13 was used on larger die of 257 ⁇ 330 mils and 315 ⁇ 450 mils.
  • a dose of 1.1E13 to 1.3E13 can be used to improve avalanche capability without adversely affecting breakdown voltage.
  • FIG. 1 is a cross-section of a small area of a superjunction die and is a cross-section of a portion of FIG. 2 taken across section line 2 - 2 in FIG. 1.
  • FIG. 2 is a view of the top of the silicon in FIG. 1, take across section line 1 - 1 in FIG. 2 to show the topology of the P type pedestals or channels.
  • FIGS. 1 and 2 there is shown a silicon die having an N + body 10 which has an epitaxially deposited N ⁇ top layer 11 formed thereon.
  • epitaxial layer means a layer of silicon which was grown by an epitaxial process.
  • Layer 10 is about 500 microns thick and layer 11 is about 17 microns thick for a 500 volt device.
  • the N ⁇ concentration is typically about 1.26 atoms/cm 3 (or about 3.5 ohm cm).
  • a plurality of spaced P columns 12 are formed in layer 11 as shown.
  • P columns may have a depth of about 6.4 microns and a center-to-center spacing of about 15 microns.
  • the P columns are shown as hexagonal in section, but they can have any other shape and; if desired, may be rectangular, square, or even have a parallel elongated stripe form.
  • hexagonal columns When hexagonal as shown, the hexagonal columns may be 6.4 microns wide when measured perpendicular to parallel sides, and may be spaced by about 8.6 microns from all adjacent columns.
  • the P columns may be fabricated by sequentially growing N ⁇ epitaxial layers about 6.4 microns thick and diffusing the hexagonal P layers which are aligned with one another to build the full P column.
  • the P columns 10 are formed by implants of boron at 80 KeV and at a dose of 1.1E13 or greater, but in accordance with the invention, will have a value which is greater than that need for charge balance between the N ⁇ epitaxial silicon 11 and the P columns 12 .
  • a gate oxide and a conductive polysilicon lattice 13 (atop the gate oxide) is formed in the lattice space between columns 12 .
  • a shallow N + source 14 is then formed into the top of each column 12 as by implantation and diffusion, to define channel regions under the gate 13 .
  • a thin P + contact layer 15 is formed beneath each source layer 14 .
  • the top of polysilicon gates 13 are capped by an interlayer oxide 16 and a shallow trench is formed through sources 14 and into P + regions 15 .
  • An aluminum source electrode 17 is then formed atop the upper surface of the die, making contact with source regions 14 and P + regions 15 .
  • the top of source 17 is covered by a suitable passivation layer 18 .
  • a drain electrode 20 is formed on the bottom of die 10 .
  • the concentration in the P column is greater that needed for charge balance to the surrounding N ⁇ epitaxial silicon.
  • a P concentration defined by an implant dose of 1.0 ⁇ 10 13 atoms/cm 2 would be used in the prior art.
  • the dose of 1.1E13 for columns 12 increased avalanche energy over 10 fold.
  • a dose of 1.2 ⁇ 10 13 atoms/cm 2 can be used with the same benefit.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Light Receiving Elements (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A superjunction device has a plurality of equally spaced P columns in an N− epitaxial layer. The concentration of the P type columns is made greater than that needed for maintaining charge balance in the N− epi region and the P columns thereby to increase avalanche energy. An implant dose of 1.1E13 or greater is used to form the P columns.

Description

    FIELD OF THE INVENTION
  • This invention relates to semiconductor devices and more specifically relates to a superjunction type power MOSFET with increased avalanche energy. [0001]
    • BACKGROUND OF THE INVENTION
  • Superjunction power MOSFETs are well known. The static and dynamic characteristics of such devices are also described in “Analysis of the Effect of Charge Imbalance on the Static and dynamic Characteristics of the Superjunction MOSFET by Proveen M. Shenoy, Anup Bhalla and Gray M. Dolay, Proceeding of the ISPSD '99, pp. 99-102, June 1999. [0002]
  • In such devices, the avalanche capability, sometimes called “ruggedness” is determined mainly by the means of preventing the turn on of the inherent parasitic bipolar transistor in a DMOS type MOSgated device. However, in the superjunction device, the concentration of the P type columns is chosen to maintain charge balance in the active area of the epitaxial silicon body material. This requirement lowers the avalanche capability of the device because the high field locates in the N type region of the epitaxial silicon layer, resulting in a higher base resistance R[0003] b 1 in the avalanche current path through the N type region and to the N+ source. Thus, in some designs, avalanche energy, that is, the amount of energy which is produced in avalanche without failure, has been as low as 50 millijoules. Attempts to increase this energy results in a reduction of the device breakdown voltage.
  • It would be desirable to increase the avalanche energy of a superjunction device without degrading the breakdown voltage. [0004]
    • BRIEF DESCRIPTION OF THE INVENTION
  • In accordance with the invention, the P column dose in a superjunction device is increased to a value intentionally higher than that required for charge balance in apparent disregard of the accepted theory and design rules for superjunction devices. By doing so, the high field location moves from the N region to the P column, and, therefore, a lower R[0005] b 1 or lateral base resistance is experienced by the avalanche current through the P column to the source. Thus, the avalanche capability of the device is significantly improved (by a factor greater than 10) without degrading breakdown voltage.
  • For example, in a prior design using an N epi layer concentration of 1.26E15 and a P column dose of about 1E13, the P column dose was increased to 1.1E13 and avalanche energy was increased from 50 millijoules to 2500 millijoules. The P column dose to be used is dependent on die size and it was found that a higher dose can be used on smaller area die. Thus, a P column dose of 1.2E13 was used for a die of size 110×140 mils; while a dose of 1.1E13 was used on larger die of 257×330 mils and 315×450 mils. In all cases, a dose of 1.1E13 to 1.3E13 can be used to improve avalanche capability without adversely affecting breakdown voltage.[0006]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-section of a small area of a superjunction die and is a cross-section of a portion of FIG. 2 taken across section line [0007] 2-2 in FIG. 1.
  • FIG. 2 is a view of the top of the silicon in FIG. 1, take across section line [0008] 1-1 in FIG. 2 to show the topology of the P type pedestals or channels.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Referring to FIGS. 1 and 2, there is shown a silicon die having an N[0009] + body 10 which has an epitaxially deposited N− top layer 11 formed thereon. Note that the term epitaxial layer means a layer of silicon which was grown by an epitaxial process. Layer 10 is about 500 microns thick and layer 11 is about 17 microns thick for a 500 volt device. The N− concentration is typically about 1.26 atoms/cm3 (or about 3.5 ohm cm).
  • A plurality of spaced [0010] P columns 12 are formed in layer 11 as shown. P columns may have a depth of about 6.4 microns and a center-to-center spacing of about 15 microns. The P columns are shown as hexagonal in section, but they can have any other shape and; if desired, may be rectangular, square, or even have a parallel elongated stripe form. When hexagonal as shown, the hexagonal columns may be 6.4 microns wide when measured perpendicular to parallel sides, and may be spaced by about 8.6 microns from all adjacent columns.
  • The P columns may be fabricated by sequentially growing N[0011] − epitaxial layers about 6.4 microns thick and diffusing the hexagonal P layers which are aligned with one another to build the full P column. As well be later emphasized, the P columns 10 are formed by implants of boron at 80 KeV and at a dose of 1.1E13 or greater, but in accordance with the invention, will have a value which is greater than that need for charge balance between the N− epitaxial silicon 11 and the P columns 12.
  • After forming the [0012] P columns 12, a gate oxide and a conductive polysilicon lattice 13 (atop the gate oxide) is formed in the lattice space between columns 12. A shallow N+ source 14 is then formed into the top of each column 12 as by implantation and diffusion, to define channel regions under the gate 13. A thin P+ contact layer 15 is formed beneath each source layer 14. The top of polysilicon gates 13 are capped by an interlayer oxide 16 and a shallow trench is formed through sources 14 and into P+ regions 15. An aluminum source electrode 17 is then formed atop the upper surface of the die, making contact with source regions 14 and P+ regions 15. The top of source 17 is covered by a suitable passivation layer 18. A drain electrode 20 is formed on the bottom of die 10.
  • In accordance with the invention the concentration in the P column is greater that needed for charge balance to the surrounding N[0013] − epitaxial silicon. In particular and with an N− region resistivity of 3.5 ohm cm and the dimensions given, a P concentration defined by an implant dose of 1.0×1013 atoms/cm2 would be used in the prior art. In accordance with the invention however, and for a die of 315×450 mils, the dose of 1.1E13 for columns 12 increased avalanche energy over 10 fold. For a smaller die of 110×140 mils, a dose of 1.2×1013 atoms/cm2 can be used with the same benefit.
  • Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein. [0014]

Claims (6)

What is claimed is:
1. A super unction device comprising a flat thin monocrystalline silicon die having an N+ body and a junction-receiving epitaxially grown N− layer on top of said N+ body; a plurality of equally spaced P type columns of similar cross-section extending into said epitaxial layer for a substantial portion of the thickness of said epitaxial layer and perpendicularly to the top and bottom surfaces of said die; said P type columns having a P type concentration which is intentionally greater than that needed for change balance between said P columns and the surrounding N− epitaxial silicon.
2. The device of claim 1, which further includes a MOSgate structure formed on the top surface of said N− epitaxial layer of silicon.
3. The device of claim 2, wherein said MOSgate structure includes a source region in the top of each of said P columns and defining invertible channel regions in said P columns and a gate structure spanning across said invertible channel regions and said N− epitaxial silicon.
4. The device of claim 1, wherein said P column is formed from boron implants having a dose of greater than about 1.1E13.
5. The device of claim 2, wherein said P column is formed from boron implants having a dose of greater than about 1.1E13.
6. The device of claim 3, wherein said P column is formed from boron implants having a dose of greater than about 1.1E13.
US09/927,027 2001-08-09 2001-08-09 Superjunction device with improved avalanche capability and breakdown voltage Abandoned US20030030051A1 (en)

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US09/927,027 US20030030051A1 (en) 2001-08-09 2001-08-09 Superjunction device with improved avalanche capability and breakdown voltage
AU2002367714A AU2002367714A1 (en) 2001-08-09 2002-07-11 Superjunction device with improved avalanche capability and breakdown voltage
PCT/US2002/022171 WO2003088312A2 (en) 2001-08-09 2002-07-11 Superjunction device with improved avalanche capability and breakdown voltage
US10/383,434 US6768170B2 (en) 2001-08-09 2003-03-06 Superjunction device with improved avalanche capability and breakdown voltage

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* Cited by examiner, † Cited by third party
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US20080299726A1 (en) * 2007-05-29 2008-12-04 Nec Electronics Corporation Semiconductor apparatus and method of manufacturing semiconductor apparatus
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
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EP1487021A1 (en) * 2002-01-28 2004-12-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
DE10346838A1 (en) * 2002-10-08 2004-05-13 International Rectifier Corp., El Segundo Superjunction semiconductor device using spaced pylons provided with increased charge concentration at their top ends
US7166890B2 (en) * 2003-10-21 2007-01-23 Srikant Sridevan Superjunction device with improved ruggedness
US7268395B2 (en) * 2004-06-04 2007-09-11 International Rectifier Corporation Deep trench super switch device
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US7812441B2 (en) 2004-10-21 2010-10-12 Siliconix Technology C.V. Schottky diode with improved surge capability
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US7834376B2 (en) * 2005-03-04 2010-11-16 Siliconix Technology C. V. Power semiconductor switch
US9419092B2 (en) * 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
US8368165B2 (en) * 2005-10-20 2013-02-05 Siliconix Technology C. V. Silicon carbide Schottky diode
US7659588B2 (en) * 2006-01-26 2010-02-09 Siliconix Technology C. V. Termination for a superjunction device
US9627552B2 (en) * 2006-07-31 2017-04-18 Vishay-Siliconix Molybdenum barrier metal for SiC Schottky diode and process of manufacture
JP5132123B2 (en) 2006-11-01 2013-01-30 株式会社東芝 Power semiconductor device
US8274128B2 (en) * 2007-03-23 2012-09-25 Siliconix Technology C. V. Ir Semiconductor device with buffer layer
KR101614565B1 (en) 2008-09-01 2016-04-21 로무 가부시키가이샤 Semiconductor device and manufacturing method thereof
US9722041B2 (en) 2012-09-19 2017-08-01 Vishay-Siliconix Breakdown voltage blocking device
US9287371B2 (en) 2012-10-05 2016-03-15 Semiconductor Components Industries, Llc Semiconductor device having localized charge balance structure and method
US9219138B2 (en) 2012-10-05 2015-12-22 Semiconductor Components Industries, Llc Semiconductor device having localized charge balance structure and method
CN104779295B (en) * 2015-04-24 2018-11-06 无锡同方微电子有限公司 Half super node MOSFET structure of one kind and preparation method thereof
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Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4284997A (en) * 1977-07-07 1981-08-18 Zaidan Hojin Handotai Kenkyu Shinkokai Static induction transistor and its applied devices
US4375124A (en) 1981-11-12 1983-03-01 Gte Laboratories Incorporated Power static induction transistor fabrication
US4587712A (en) 1981-11-23 1986-05-13 General Electric Company Method for making vertical channel field controlled device employing a recessed gate structure
US5766966A (en) * 1996-02-09 1998-06-16 International Rectifier Corporation Power transistor device having ultra deep increased concentration region
EP0689239B1 (en) 1994-06-23 2007-03-07 STMicroelectronics S.r.l. Manufacturing process for MOS-technology power devices
JP3938964B2 (en) 1997-02-10 2007-06-27 三菱電機株式会社 High voltage semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080299726A1 (en) * 2007-05-29 2008-12-04 Nec Electronics Corporation Semiconductor apparatus and method of manufacturing semiconductor apparatus
US7829417B2 (en) * 2007-05-29 2010-11-09 Nec Electronics Corporation Semiconductor apparatus and method of manufacturing semiconductor apparatus
CN114759081A (en) * 2022-06-14 2022-07-15 绍兴中芯集成电路制造股份有限公司 Semiconductor structure and preparation method thereof

Also Published As

Publication number Publication date
WO2003088312A2 (en) 2003-10-23
US6768170B2 (en) 2004-07-27
US20030151045A1 (en) 2003-08-14
AU2002367714A1 (en) 2003-10-27
WO2003088312A3 (en) 2004-02-12
AU2002367714A8 (en) 2003-10-27

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