US20020100959A1

US20020100959A1 - Capacitor for semiconductor memory device and method of manufacturing the same

Info

Publication number: US20020100959A1
Application number: US10/086,551
Authority: US
Inventors: Kwang Chul Joo; Kee Jeung Lee; Il Keoun Han
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1999-07-02
Filing date: 2002-03-04
Publication date: 2002-08-01
Also published as: GB2358284B; DE10032213B8; US6376299B1; TW449912B; CN100383971C; CN1280392A; JP2001053253A; DE10032213B4; GB2358284A; GB0015991D0; DE10032213A1

Abstract

Disclosed are a capacitor for a semiconductor memory device and a method of manufacturing the same. According to the present invention, the method includes the steps of: forming a lower electrode on a semiconductor substrate; nitride-treating the surface of the lower electrode so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta₂O₅layer as a dielectric layer on the upper part of the lower electrode; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta₂O₅layer; and forming an upper electrode on the upper part of the conductive barrier.

Description

FIELD OF THE INVENTION

The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor for semiconductor memory device including a conductive barrier having an excellent step coverage, between a dielectric layer and an upper electrode and a method of manufacturing the same.

BACKGROUND OF THE INVENTION

As the number of memory cells composing DRAM semiconductor device has been recently increased, occupancy area of each memory cell is gradually decreased. Meanwhile, capacitors formed in the respective memory cells require a sufficient capacitance for precise reading out of storage data. Accordingly, the current DRAM semiconductor device requires memory cells in which capacitors having larger capacitance as well as occupying small area are formed. The capacitance of a capacitor can be increased by using an insulator having high dielectric constant as a dielectric layer, or by enlarging the surface area of a lower electrode. In a highly integrated DRAM semiconductor device, a Ta ₂O₅layer having a higher dielectric constant than that of the nitride-oxide(NO) is now used as a dielectric, thereby forming a lower electrode of a 3-Dimentional structure.

FIG. 1 is a cross-sectional view showing a capacitor for a conventional semiconductor memory device. Referring to FIG. 1, a

gate electrode

13 including a gate insulating layer 12 at a lower portion thereof is formed according to a known technique on the upper part of a semiconductor substrate 10 which a field oxide layer 11 is formed at a selected portion thereof. A junction region 14 is formed on the semiconductor substrate 10 at both sides of the gate electrode 13, thereby forming an MOS transistor. A first interlayer insulating layer 16 and a second interlayer insulating layer 18 are formed on the upper part of the semiconductor substrate 10 which the MOS transistor is formed therein. A storage node contact hole h is formed inside the first and the second

interlayer insulating layers

16,18 so that the junction region 14 is exposed. A cylinder type lower electrode 20 is formed according to a known method, inside the storage node contact hole h so as to be in contact with the exposed junction region 14. A HSG(hemi-spherical grain) layer 21 is formed on a surface of a lower electrode 20 to increase the surface area of the lower electrode 20 more. A Ta₂O₅layer 22 is deposited on the upper part of the lower electrode 20 which the HSG layer 21 is formed thereon. The Ta₂O₅layer 22 can be formed according to PECVD(plasma enhanced chemical vapor deposition) method or LPCVD(low pressure chemical vapor deposition) method. At this time, the Ta₂O₅formed according to the PECVD method has an advantage of excellent layer quality, but a disadvantage of poor step coverage property. Therefore, the conventional Ta₂O₅layer 22 has been formed according to the LPCVD method having an excellent step coverage property. Afterwards, Ta₂O₅layer 22 is crystallized after a selected thermal process. A titanium nitride layer(TiN) 23 serving as the conductive barrier is formed on the upper part of the Ta₂O₅layer 22. The TiN layer 22 is formed according to the LPCVD method or a sputtering method. An upper electrode 24 made of a doped polysilicon layer is formed on the upper part of the TiN layer.

However, the capacitor using the Ta ₂O₅layer as a dielectric has the following problems.

First, a difference in the composition rate of Ta and O is generated since the Ta ₂O₅layer 23 generally has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms are generated in a thin film. Since those vacancy atoms are oxygen vacancies, leakage current is generated. The amount of vacancy atoms can be controlled depending on the contents and the bonding strength of components in the Ta₂O₅layer; however, it is difficult to eliminate them completely. To stabilize the unstable stoichiometry of the Ta₂O₅layer, the Ta₂O₅layer is oxidized so as to remove the substitutional Ta atoms therein. However, when the Ta₂O₅layer is oxidized to prevent leakage current, the following problem is generated. That is, the Ta₂O₅layer has a large reaction with the lower electrode formed of a polysilicon layer. Therefore, in a oxidizing process of the substitutional Ta atoms, a natural oxide layer having low dielectric constant between the Ta₂O₅layer and the lower electrode. Oxygen moves to an interface between the Ta₂O₅layer and the lower electrode, thereby deteriorating the homogeneity of the interface.

Moreover, impurities such as carbon atoms (C), carbon compounds (CH ₄, C₂H₄), and H₂O are generated inside the Ta₂O₅layer by a reaction of organic substances of Ta(OC₂H₅)₅used as a precursor and O₂(or N₂O) gas. These impurities increase leakage current of a capacitor and deteriorate a dielectric property inside the Ta₂O₅layer. Therefore, a great capacitor is difficult to obtain.

Meanwhile, the

TiN layer

23 also serving as the conductive barrier between the upper electrode 24 and the Ta₂O₅layer 22 has the following problems.

First, in case the

TiN layer

23 serving as the conductive barrier is formed according to the LPCVD method, the problem is described. TiCl₄gas and NH₃gas are generally used for source gas of the TiN layer formed according to the LPCVD method. At this time, TiCl₄gas has a property of being dissociated at a high temperature of more than 600° C. Therefore, the TiN layer is actually formed at much higher temperature than 600° C. to control easily Cl density therein. However, when forming the TiN layer, a high temperature process is accompanied, thereby generating mutual diffusion between atoms composing the Ta₂O₅layer 22 and the lower electrode 20. And, a gas phase reaction is active in a chamber by NH₄gas having a high reaction, thereby generating a large amount of particles inside the Ta₂O₅layer or on the surface thereof. As a result, the homogeneity of the dielectric layer is deteriorated.

Furthermore, when the TiN layer is formed, the amount of Cl inside the TiN layer is difficult to be controlled. As a result, a large amount of Cl inside the TiN layer remain. The TiN layer which a large amount of Cl remained therein is difficult to serve as the conductive barrier, thereby generating leakage current inside the capacitor.

And, since the

TiN layer

23 formed of according to the sputtering method has a poor step coverage property, the TiN layer is difficult to be deposited on the upper part of the Ta₂O₅layer 22 to the thickness of 200 to 400 Å. As a result, voids are formed between the grains of the HSG layer 21, thereby deteriorating a capacitor property.

In addition, the

TiN layer

23 and Ta₂O₅layer 22 react at a temperature of 687K(414° C.) as follows.

5TiN+2Ta₂O₅→5TiO₂+4TaN+{fraction (1/2)}N₂

That is, in a range of 687K temperature, the

TiN layer

23 and the Ta₂O₅layer 24 react, thereby generating undesired TiO₂dielectric substances(not shown) on the interface between the TiN layer 23 and Ta₂O₅layer 22. The TiO₂dielectric substances increase the thickness of the dielectric layer, thereby deteriorating capacitance. In addition, TiO₂itself has a high leakage property, thereby increasing leakage current of the dielectric layer.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to improve the uniformity of the dielectric layer by preventing a natural oxide layer from generating between a lower electrode and a Ta ₂O₅layer.

And, it is another object of the present invention to ensure high capacitance as well as low leakage current.

It is the other object to form a conductive barrier having a good step coverage property.

To achieve the objects according to one aspect of the present invention, a capacitor for a semiconductor memory device includes: a lower electrode; a silicon nitride layer for restraint of a natural oxide layer formed on the lower electrode surface; a dielectric layer formed on the upper part of the silicon nitride layer; and an upper electrode formed on the upper part of the dielectric layer, wherein the dielectric layer is a Ta ₂O₅layer.

And, according to another embodiment, a capacitor for a semiconductor memory device includes: a lower electrode; a silicon nitride layer for restraint of a natural oxide layer formed on the lower electrode surface; a dielectric layer formed on the upper part of the silicon nitride layer; a conductive barrier made of the silicon nitride layer formed on the dielectric layer surface; and an upper electrode formed on the upper part of the conductive barrier, wherein the dielectric layer is a Ta ₂O₅layer.

Further, according to the other aspect a method for forming a capacitor for a semiconductor device includes the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode; depositing the Ta ₂O₅layer as the dielectric layer on the upper part of the surface nitride-treated lower electrode; and forming an upper electrode on the upper part of the dielectric layer.

Moreover, according to another embodiment of the present invention the method of forming a capacitor for a semiconductor device including the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta ₂O₅layer as a dielectric layer on the upper part of the lower electrode; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta₂O₅layer; and forming an upper electrode on the upper part of the conductive barrier.

And, according to the other embodiment a method of forming a capacitor for a semiconductor device includes the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode inside a chamber maintaining NH ₃or N₂/H₂plasma gas and a temperature of 200 to 700° C. so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta₂O₅layer as a dielectric layer on the upper part of the lower electrode; crystallizing the Ta₂O₅layer after thermal-treatment thereof; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta₂O₅layer in a chamber maintaining plasma gas containing nitrogen and a temperature of 200 to 400° C.; and forming an upper electrode on the upper part of the conductive barrier, wherein the surface nitride treatment step of the lower electrode, the formation step of the Ta₂O₅layer, the thermal-treating and then crystallizing step of the Ta₂O₅layer and the formation step of the conductive barrier are performed in situ in the same chamber.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a conventional capacitor for a semiconductor memory device. [0021]
FIGS. 2A to [0022] 2D are cross-sectional views for describing a method of manufacturing a capacitor for a semiconductor device according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of a capacitor for a semiconductor memory device for describing a second embodiment of the present invention. [0023]
FIGS. 4A and 4B are cross-sectional views of a capacitor for a semiconductor memory device for describing a third embodiment of the present invention.[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[Embodiment 1][0025]
Referring to FIG. 2A, a [0026] field oxide layer 31 is formed according to a known method at a selected portion of a semiconductor substrate 30 having a selected conductivity. A gate electrode 33 having a gate insulating layer 32 at a lower portion thereof is formed at a selected portion on the upper part of the semiconductor substrate 30, and a spacer 34 is formed according to a known method at both side-walls of the gate electrode 33. A junction region 35 is formed on the semiconductor substrate 30 at both sides of the gate electrode 33, thereby forming an MOS transistor. A first interlayer insulating layer 36 and a second interlayer insulating layer 38 are formed on the semiconductor substrate 30 which the MOS transistor is formed therein. Afterward, the second and the first interlayer insulating layers 38,36 are patterned so that a portion of the junction region 35 is exposed, thereby forming a storage node contact hole H. A lower electrode 40 of cylinder type is formed to be in contact with the exposed junction region 35. A HSG layer 41 for enlarging the surface area of the lower electrode 40 is formed according to a known method on the surface of the lower electrode 40.
Afterward, to restrain the generation of a low dielectric natural oxide layer at an interface between the [0027] lower electrode 40 having the HSG layer 41 and a dielectric layer to be formed later(not shown), the surfaces of the lower electrode 40 having the HSG layer 41 and the second interlayer insulating layer 38 are nitride-treated. The surface nitride-treatment is performed in an LPCVD chamber maintaining an NH₃gas or N₂/H₂gas plasma state at a temperature of 200 to 700° C., more preferably 300 to 500° C.
Referring to FIG. 2B, as a dielectric, a Ta[0028] ₂O₅layer 43 is formed on the surface of a first silicon nitride layer 42. The Ta₂O₅layer 43 of the present invention is formed by a chemical gas phase deposition method, e.g. an LPCVD method and an organic material such as Ta(OC₂H₅)₅(tantalum ethylate) is used as a precursor. Herein, the organic substance such as Ta(OC₂H₅)₅, as known, is in liquid state, and therefore is supplied into the LPCVD chamber after converting into a vapor state. That is, the precursor in liquid state is quantified using a flow controller such as an MFC(Mass Flow Controller) and then evaporated in an evaporizer including an orifice or a nozzle, or a conduit coupled to the chamber, thereby becoming Ta chemical vapor. Afterwards, Ta chemical vapor is preferably supplied into the LPCVD chamber by flux of 80 to 100 mg/min. At this time, the temperature of the evaporizer and a conduit coupled to the chamber which is a flow path of Ta vapor, is preferably maintained at 150 to 200° C. so as to prevent condensation of Ta chemical vapor. Ta chemical vapor supplied into the LPCVD chamber according to this method, and excess O₂gas, reaction gas, are reacted together, thereby forming an amorphous Ta₂O₅layer 43 to the thickness of approximately 100 to 150 Å. At this time, to minimize particle generation, Ta chemical vapor and O₂gas are controlled to inhibit the gas phase reaction inside the chamber so that the gases react with each other only on the wafer surface. Herein, the gas phase reaction can be controlled by the flow rates of the reaction gases and the pressure within the chamber. And, according to the present embodiment, O₂gas, reaction gas, is supplied into the LPCVD chamber by flux of 10 to 500 sccm or so and the temperature within the chamber is preferably maintained at 300 to 500° C. so as to restrain the gas phase reaction. At this time, the formation process of the Ta₂O₅layer and the surface nitride-treatment process of the lower electrode are both performed in situ without interrupting the vacuum state within the LPCVD chamber. Consequently, an additional natural oxide and particle are not generated.
Afterwards, to remove chronic remaining substitutional Ta atoms within the Ta[0029] ₂OS layer 43 and disconnected carbon components, the Ta₂O₅layer 43 is first annealed under an atmosphere of O₃or UV-O₃at a temperature of 300 to 500° C. And then, to crystallize the Ta₂O₅layer 43 and simultaneously remove carbon compounds remaining by a low temperature annealing process, a high annealing process is performed under an atmosphere of N₂O gas, O₂gas or N₂gas at a temperature of 700 to 950° C. for 5 to 30 minutes. At this time, the annealing process with the surface nitride-treatment of the lower electrode and the formation process of the Ta₂O₅layer is also performed in situ.
Afterwards, as shown in FIG. 2C, a second [0030] silicon nitride layer 44 as a conductive barrier is deposited on the upper part of the Ta₂O₅layer 43. The second silicon nitride layer 44 is formed by a nitride-treatment using plasma, nitride-treatment using a furnace or an RTN method according to in-situ or cluster method. First, the nitride-treatment using plasma is performed under an atmosphere of NH₃gas, N₂/O₂gas, or N₂O gas including containing nitrogen at a temperature of 200 to 400° C. Meanwhile, the nitride-treatment using the furnace and the RTN process are performed under an atmosphere of NH₃gas, N₂/O₂gas, or N₂O gas at a temperature of 750 to 950° C. Herein, when the second silicon nitride layer 44 as a conductive barrier is formed by the nitride-treatment using plasma, it is performed in situ with the surface nitride-treatment process of the lower electrode, the formation process of the Ta₂O₅layer and the annealing process of the Ta₂O₅layer.
Next, referring to FIG. 2D, an [0031] upper electrode 45 is on the upper part of the second silicon nitride layer 44. The upper electrode 45 can be formed of a doped polysilicon layer and a metal layer such as TiN, TaN, W, WN, WSi, Ru, RuO₂, Ir, IrO₂or Pt. When the doped polysilicon layer is used as the upper electrode 45, it is preferably deposited to the thickness of 1000 to 1500 Å. And, the metal layer is used as the upper electrode 45, it is preferably formed to the thickness of 100 to 600 Å. In addition, the polysilicon layer can be formed by a CVD method, the metal layer can be formed by one among LPCVD, PECVD, RF magnetic sputtering method.
According to the present embodiment, the Ta[0032] ₂O₅layer 43 is nitride-treated in situ before the formation thereof. As a result, in an oxidizing process for removing substitutional Ta atoms and impurities, oxide reaction of the lower electrode 40 and the Ta₂O₅layer 43 is restrained, thereby reducing the movement of oxygen. Consequently, the equivalent thickness of the dielectric layer can be thinned, and the interface homogeneity between the lower electrode 40 and the Ta₂O₅layer 43 can be ensured.
Moreover, the surface nitride-treatment process of the lower electrode, the formation process of the Ta[0033] ₂O₅layer, the thermal process of the Ta₂O₅layer and the formation process of the silicon nitride layer for the conductive barrier are performed in situ, thereby preventing the generation of an additional natural oxidation and particles.
Further, the [0034] silicon nitride layer 44 as the conductive barrier is formed by plasma treatment under NH₃, gas, N₂/O₂gas or N₂O gas atmosphere, the nitride-treatment by the furnace, or the RTN process, and therefore can be homogeneously deposited to the thickness of 10 to 20 Å on the upper part of the Ta₂O₅layer. Accordingly, the step coverage property of the conductive barrier is improved.
And, TiCl[0035] ₄source gas for the formation of a TiN layer is not required, and therefore the contamination within the chamber and the Ta₂O₅layer 43 by Cl ion is prevented, thereby preventing leakage current. In addition, since the conductive barrier made of the silicon nitride layer is reacted with the Ta₂O₅layer at a selected temperature, the generation of leakage current due to reaction byproducts and the problem of the increase in the effective thickness are not generated.
Furthermore, the Ta[0036] ₂O₅layer having high dielectric constant is used as the dielectric layer, thereby obtaining a capacitor having a high capacitance.
[EMBODIMENT 2][0037]
Each part of the present embodiment may be largely equal to that of the first embodiment while only the structure of the lower electrode is different. [0038]
As shown in FIG. 3, according to the present embodiment, a [0039] lower electrode 400 is formed in a stack structure. Although the surface area of the stack structure lower electrode 400 is narrower than that of the cylinder structure lower electrode, the Ta₂O₅layer having a good dielectric constant is used as the dielectric layer, thereby obtaining a desired capacitor.
[EMBODIMENT 3][0040]
The present embodiment can be equal to the first and the second embodiments and only the manufacturing method thereof is different. And, all processes until the first [0041] silicon nitride layer 42 is formed, are equal to those of the first and the second embodiments, and therefore in the present embodiment, only the manufacturing method is described.
Referring FIG. 4A, a first Ta[0042] ₂O₅layer 43-1 is formed on the upper part of the first silicon oxide layer 42 to the thickness of 53 to 57 Å at a temperature of 400 to 450° C. Afterwards, the first Ta₂O₅layer 43-1 is annealed in situ in an N₂O or O₂plasma state to remove substitutional Ta molecules and carbon components therein. Or, substitutional Ta molecules and carbon components inside the first Ta₂O₅layer 43-1 can be removed ex situ using UV-O₃. Afterwards, a second Ta₂O₅layer 43-2 is formed on the surface of the first annealed Ta₂O₅layer 43-1 by the same methods as those of the formation of the first Ta₂O₅layer 43-1.
Next, as shown in FIG. 4B, the second Ta[0043] ₂O₅layer 43-2 and the first Ta₂O₅layer 43-1 are annealed again so as to remove the substitutional Ta molecules and carbon components inside them. As a result, the first Ta₂O₅layer 43-1 and the second Ta₂O₅layer become single layers respectively due to this plasma annealing process.
As described above in detail, the followings are the effects of the present invention. [0044]
First, the Ta[0045] ₂O₅layer 43 is nitride-treated in situ before the formation thereof. Therefore, in an oxidizing process for removing substitutional Ta atoms and impurities. The oxide reaction of the lower electrode 40 and the Ta₂O₅layer 43 is restrained and the movement of oxygen is reduced. Consequently, the equivalent thickness of the dielectric layer can be thinned, thereby ensuring the interface homogeneity between the lower electrode 40 and the Ta₂O₅layer 43.
Moreover, those processes of the surface nitride-treatment of the lower electrode, the formation process of the Ta[0046] ₂O₅layer, the thermal process of the Ta₂O₅layer and the formation process of the silicon nitride layer for the conductive barrier can be performed in situ, thereby preventing additional generation of natural oxidation and particles.
And, since the silicon nitride layer as a conductive barrier is formed by the plasma treatment or the RTN process under NH[0047] ₃, N₂/O₂or N₂O gas atmosphere, the silicon nitride layer can be homogeneously deposited to the thickness of 10 to 20 Å although there is formed step difference on the upper part of the Ta₂O₅layer. Accordingly, the step coverage property of the conductive barrier is improved.
Furthermore, since TiCl[0048] ₄source gas for forming of the TiN layer is not required, the contamination inside the chamber owing to the Cl ion is prevented, thereby preventing leakage current. In addition, since reaction between the conductive barrier made of the silicon nitride layer and the Ta₂O₅layer is not generated at a selected temperature, leakage current by reaction byproducts and reaction byproducts are not generated. As a result, the effective thickness of the Ta₂O₅layer is not increased.
And, the Ta[0049] ₂O₅layer is crystallized simultaneously with the formation of the conductive barrier, thereby reducing the manufacturing processes.
In addition, the Ta[0050] ₂O₅layer having a high dielectric constant is used as the dielectric layer, thereby obtaining a capacitor having a high capacitance.
Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of the present invention. [0051]

Claims

What is claim is:

1. A capacitor for a semiconductor memory device comprising:

a lower electrode;

a silicon nitride layer for restraint of a natural oxide layer formed on the lower electrode surface;

a dielectric layer formed on the upper part of the silicon nitride layer; and

an upper electrode formed on the upper part of the dielectric layer,

wherein the dielectric layer is a Ta₂O₅layer.

2. The capacitor according to claim 1, comprising a conductive barrier made of the silicon nitride layer between the dielectric layer and the upper electrode.

3. The capacitor according to claim 2, wherein the thickness of the conductive barrier is 10 to 20Å.

4. The capacitor according to claim 1, wherein the lower electrode has cylinder or stack structure which an HSG layer is formed on the surface thereof.

5. The capacitor according to claim 1, wherein the thickness of the Ta₂O₅layer is 100 to 150Å.

6. The capacitor according to claim 1, wherein the upper electrode is formed of a doped polysilicon layer.

7. The capacitor according to claim 1, wherein the upper electrode is formed of a metal layer.

8. The capacitor according to claim 6, wherein the metal layer is one among TiN, TaN, W, WN, WSi, Ru, RuO₂, Ir, IrO₂and Pt.

9. A capacitor for a semiconductor memory device comprising:

a lower electrode;

a dielectric layer formed on the upper part of the silicon nitride layer;

a conductive barrier made of the silicon nitride layer formed on the dielectric layer surface; and

an upper electrode formed on the upper part of the conductive barrier,

wherein the dielectric layer is a Ta₂O₅layer.

10. The capacitor according to claim 9, wherein the thickness of the conductive barrier is 10 to 20Å.

11. The capacitor according to claim 9, wherein the lower electrode is cylinder or stack structure which an HSG layer is formed on the surface thereof.

12. The capacitor according to claim 9, wherein the thickness of the Ta₂O₅layer is 100 to 150Å.

13. The capacitor according to claim 9, wherein the upper electrode is formed of a doped polysilicon layer.

14. The capacitor according to claim 9, wherein the upper electrode is formed of a metal layer.

15. The capacitor according to claim 14, wherein the metal layer is one among TiN, TaN, W, WN, Wsi, Ru, RuO₂, Ir, IrO₂, and Pt.