US20020004285A1

US20020004285A1 - Stress-free shallow trench isolation

Info

Publication number: US20020004285A1
Application number: US09/123,746
Authority: US
Inventors: Shye-Lin Wu
Original assignee: Individual
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; TSMC Acer Semiconductor Manufacturing Inc
Priority date: 1998-07-27
Filing date: 1998-07-27
Publication date: 2002-01-10
Anticipated expiration: 2018-07-27
Also published as: US6355540B2

Abstract

The present invention proposes a shallow trench isolation region in a semiconductor substrate for ULSI devices. The trench region includes a thermal oxide film formed on the bottom and the sidewall, a CVD dielectric film formed on the bottom of the thermal oxide film, and a channel stop region formed beneath the bottom of the thermal oxide film. The processes described as follows. Forming a pad oxide/silicon nitride layer on the substrate, the trench region and active area are defined. After silicon spacers are formed, the silicon substrate is recessed to form trench region by using the silicon nitride layer and silicon spacers as etching mask. A channel stopping implantation is performed. Then a thermal oxide film is regrown on the trench surface. After removing the silicon nitride layer, a thick CVD dielectric layer is deposited on the substrate. The dielectric film outside the trench region is removed by a CMP process, and thus the present invention complete.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more especially, to a method for fabricating shallow trench isolation.

2. Description of the Prior Art

For building an integrated circuit operating with desired action, it is necessary to fabricate many active devices on a single semiconductor substrate. Various kinds of devices with different functions, such as transistors, resistors and capacitors, are formed together. Each of the devices on the substrate must be electrically isolated from the others to ensure their individual function. The art of isolating semiconductor devices becomes one important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power. Improper isolation will result in circuit latch-up, which can destroy the circuit temporarily or even permanently. In addition, improper isolation can cause degradation in circuit noise margin, voltage shift and crosstalk.

Local oxidation of silicon (LOCOS) is one of the most well known techniques for isolation. LOCOS provides the isolation by oxidizing the silicon substrate to create silicon dioxide regions among active devices or functional regions. Because it is easy for the silicon substrate to be oxidized into silicon dioxide, LOCOS has the benefits of its process simplicity and low cost, and it becomes the most widely used isolation technique in very large scale integrated (VLSI) circuit. However, with the tendency for the manufacture of semiconductor integral circuit to high package density, LOCOS meets the limitation in its scalability.

The trench isolation, which is usually referred as shallow trench isolation (STI), is another isolation technique developed especially for semiconductor chip with high integration. The trench regions are formed in the semiconductor substrate by recessing the substrate deep enough for isolation and refilling with insulating material to provide the isolation among active devices or different well regions. In general, trench isolation has a better scalability in comparison with LOCOS isolation.

In the paper “Characteristics of CMOS Device Isolation for the ULSI Age” in IEDM Tech. Dig., p. 671, 1994, by A. Bryant, et al., the two different isolation techniques of LOCOS and STI are investigated. The paper reviews how LOCOS and STI isolations are being improved to meet the scaling requirements for abrupt active-isolation transitions, isolation depth, and isolation planarity. For deep sub-micron CMOS generation, the conventional LOCOS isolation suffers from several drawbacks such as large lateral extend of bird's beak, non-planarity, local field oxide thinning effect, and stressinduced silicon defects. The key challenges to LOCOS scaling are insulator thinning at narrow dimension, bird's beak formation, and field-implant encroachment. For future CMOS technology, an effective device isolation method that provides abrupt transitions to active device regions with minimum impact on device characteristics or topography will be required. They come to the conclusions that, at the cost of a trench-fill and planarization, STI is a more direct method of meeting these requirements while benefiting from a significant advantage in planarity.

Trench isolation is developed to be a better isolation technique in deep sub-micron CMOS generation due to the advantages in its scalability, planarity, and isolation depth. But it still encounters several problems such as silicon damage induced by etching and the corner effects. In the paper entitled “Correlation between Gate Oxide Reliability and the Profile of the Trench Top Corner in Shallow Trench Isolation (STI)”, IEDM Tech. Dig., p.747, 1996, T. Park, et al., illustrated three schematic profiles of oxide etch-back trench corners. The gate conductor could wrap around the trench corner when a conventional oxide etch-back process is performed. They propose for above situation a two-step trench etching with a sidewall around. With this two-step trench etching process, the corner parasitic leakage and the gate wrap-around could be solved.

In 1997, T. Park, et al., proposed another method named “very simple trench isolation technology” in their paper “A Very Simple Trench Isolation (VSTI) Technology with Chemo-Mechanically Polished (CMP) Substrate Si” Symposium On VLSI Tech. Dig., p. 121. Based on the idea that the Si wafer is finalized with CMP step, this method provides a simple process to fabricate the isolated trench regions with smaller number of steps compared to the conventional trench isolation technique or even the LOCOS isolation. By this method, low junction leakage current, high breakdown voltage and flat surface can be reached, but the double hump associated with sharp top corner of the active to field boundary could not be completely avoided at a large reverse biased condition.

SUMMARY OF THE INVENTION

A method for fabricating shallow trench regions in a semiconductor substrate is disclosed. Silicon sidewall spacers and a thick thermal oxide film are created at and near the trench corners to prevent the corner effect such as the gate wrap-around and corner parasitic leakage. According to the processes, the trench region is formed with a thermal oxide film on the bottom and the sidewall, a CVD dielectric film on the bottom of the thermal oxide film, and a channel stop region beneath the bottom of the thermal oxide film.

Forming a pad oxide and a silicon nitride layer on a semiconductor substrate, the trench region and active area are defined by a photoresist photolithography followed by an anisotropic nitride etching. After silicon spacers are formed, the semiconductor substrate is recessed to form trench region by another dry etching using the silicon nitride layer and silicon spacers as etching hard mask. A channel stopping implantation is performed. Then a thermal oxide film is regrown on the trench surface to recover the etching damages. After removing the silicon nitride layer, a thick CVD oxide layer, which is formed of TEOS-oxide or BPSG, etc., is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. A sacrificial oxide is grown and removed for recovering the polish damages. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: [0012]
FIG. 1 is a cross-sectional view of a semiconductor wafer illustrating the step of forming a pad oxide and a nitride layer on the substrate according to the present invention: [0013]
FIG. 2 is a cross-sectional view of a semiconductor wafer illustrating the step of defining the trench regions on the substrate according to the present invention; [0014]
FIG. 3 is a cross-sectional view of a semiconductor wafer illustrating the step of forming silicon spacers on the sidewalls of the nitride layer according to the present invention; [0015]
FIG. 4 is a cross-sectional view of a semiconductor wafer illustrating the step of recessing the silicon substrate to form shallow trenches in the substrate according to the present invention; [0016]
FIG. 5 is a cross-sectional view of a semiconductor wafer illustrating the step of performing a channel stopping implantation according to the present invention; [0017]
FIG. 6 is a cross-sectional view of a semiconductor wafer illustrating the step of performing a thermal oxidation to recover damages according to the present invention; [0018]
FIG. 7 is a cross-sectional view of a semiconductor wafer illustrating the step of removing the nitride layer according to the present invention; [0019]
FIG. 8 is a cross-sectional view of a semiconductor wafer illustrating the step of depositing a CVD oxide on the substrate and refilling the trench regions according to the present invention: [0020]
FIG. 9 is a cross-sectional view of a semiconductor wafer illustrating the step of etching back the CVD oxide and the thermal oxide outside the trench regions according to the present invention; and [0021]
FIG. 10 is a cross-sectional view of a semiconductor wafer illustrating the step of fabricating MOSFET on the substrate according to the present invention.[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention proposes a simple method to fabricate shallow trenches for isolation. The method described here includes many process steps well known in the art like photolithography, etching or chemical vapor deposition (CVD) which are not discussed in detail. In addition, the present invention utilizes silicon sidewall spacers and a thick thermal oxide film to prevent etching damages and the sharp trench corner effects. [0023]
Referring to FIG. 1, a single [0024] crystal silicon substrate 2 with a <100> crystallographic orientation is provided. A silicon oxide layer 4 with the thickness about 50-500 angstroms is formed on the surface of the substrate 2 to serve as a pad oxide. This pad oxide layer 4 can be grown by using low pressure chemical vapor deposition (LPCVD) at a temperature of about 400-750° C., or using thermal oxidation at a temperature of about 800-1100° C. A silicon nitride layer 6 is then deposited, for example, using a LPCVD process at a temperature of about 700-800° C., on the silicon oxide layer 4. The thickness of the silicon nitride layer 6 is about 500-4000 angstroms. The pad oxide layer 4 acts here as a buffer to cushion the transmission of stress between the silicon substrate and the silicon nitride layer 6.
Turning next to FIG. 2, the trench pattern is now defined on the [0025] silicon nitride layer 6 by using a conventional manner of photoresist photolithography including photoresist coating, exposure, and development processes. A dry etching process then follows to etch the thick silicon nitride layer 6 and expose the trench region of the pad oxide layer 4. A reactive ion etching (RIE) with plasma gases containing fluoride such as CF₄/O₂, CF₂/H₂, CHF₃or NF₃is preferable for this anisotropic etching.
Next, after the photoresist is removed and wet cleaned, a pair of [0026] silicon spacers 8 with a thickness of about 200 to 1000 angstroms are formed on the sidewalls of the silicon nitride layer 6 as shown in FIG. 3. These silicon spacers 8 are formed of amorphous silicon or polysilicon by a blanket deposition for silicon layer over the semiconductor substrate 2 followed by an etching back. The suitable deposition method can be LPCVD at a temperature of about 400-575° C. for amorphous silicon and 575-650° C. for polysilicon. The method for etching back should be a dry etching using Cl₂, BCl₃, HBr, SF₆or SiCl₄as the etching gases. The exposed portion of pad oxide layer 4 is then removed by a dry etching with plasma gases such as CF₄, CHF₃, C₂F₆or C₃F₈. A wet etching using buffered oxide-etching (BOE) solution or diluted solution of hydrofluoric acid (HF) as the etchant can be a substitutional choice for this oxide etching.
Thereafter, another dry etching using Cl[0027] ₂, BCl₃, HBr, SF₆or SiCl₄as the plasma source is carried out. At this anisotropic etching step, the exposed portion of the semiconductor substrate 2 is recessed by using the patterned silicon nitride layer 6 and the silicon spacers 8 as the etching hard mask. The trench 10 with a depth deep enough for isolation is thus opened and shown in FIG. 4. During the recessing process of silicon substrate, the silicon spacers 8 are also removed.
An ion implantation is then optionally carried out with the ions of opposite conductive type to that of the channel of the active devices, as shown in FIG. 5, wherein the arrows indicate the implanting direction. This opposite type ion implantation is performed for the [0028] channel stop 12 to achieve a better device isolation. A thermal oxidation in an oxygen containing ambient at a temperature of about 800-1100° C. is now performed. A thick robust thermal oxide layer 14 is grown on the trench surface. The damages induced on the substrate surface by previous dry etching process are recovered through this thermal process, and the trench corners are rounded simultaneously. Alternatively, the thermal oxidation can be performed in N₂O or NO ambient, and then the material of the layer 14 would be silicon oxynitride.
Next, referring to FIG. 7, the masking [0029] silicon nitride layer 6 is removed by a wet etching using hot solution of phosphoric acid (H₃PO₄) as the etchant. A thick dielectric layer 16 is then deposited over the semiconductor substrate 2 and fills the trench region as shown in FIG. 8. The suitable method for forming this thick dielectric layer 16 can be LPCVD, PECVD (plasma-enhanced CVD) or HDPCVD (high-density plasma CVD) with the material of silicon nitride, silicon oxynitride, or silicon oxide, including tetra-ethyl-ortho-silicate-oxide (TEOS-oxide), ozone TEOS-oxide, boro-phospho silicate glass (BPSG), phospho silicate glass (PSG), boro silicate glass, (BSG), undoped silicate glass (USG) or silicon-rich oxide (SRO), and so on.
Now referring to FIG. 9, the [0030] pad oxide layer 4 and the portion of CVD oxide film 16 which exceeds the trench region in the semiconductor substrate 2, are stripped. The preferable method for this step can be chemical mechanical polishing (CMP) process for the global planarization that it can provide. Because the thermal oxide 14 is thickly grown over the trench surface, the same polishing rate is approximately kept at and near the trench corners, and the corner effects such as the gate wrap-around can be improved. The trenching isolation region is thus accomplished.
As to be the end point of the CMP process, the surface of the [0031] semiconductor substrate 2 will suffers from the polishing defects and contamination after this step. For recovering the polishing defects and eliminating the contamination, a thermal oxidation is performed, and a sacrificial oxide layer 18 is regrown on the semiconductor substrate 2.
Finally, referring to FIG. 10, the [0032] sacrificial oxide layer 18 is then etched back by a wet etching process. The preferable etchant for this wet etching is buffered oxide-etching (BOE) solution or diluted solution of hydrofluoric acid (HF). Thereafter the gate oxide layer 20 is regrown on the semiconductor substrate 2. Then the active devices that consist of gates, sources and drains are formed on the active regions to finish the fabrication of the MOS transistor.
According to above processes, the trench region with [0033] thermal oxide 14, CVD dielectric 16 and channel stop 12 is formed in a semiconductor substrate 2 to provide isolation among active devices. The thermal oxide layer 14 is formed on the bottom and the sidewall of the trench region; the CVD dielectric 16 is formed on the bottom of the thermal oxide 14, and the channel stop region 12 is formed beneath the bottom of the thermal oxide 14. By the use of the sidewall spacers, a thick thermal oxide is formed on the trench edges. The silicon damages induced by dry etching process would be reduced through long high temperature oxidation. The trench region have rounded top and bottom corners without suffering from corner effects such as the gate wrap-around. By solving these problems raised from conventional trench isolation technique, the integration of semiconductor fabrication can be greatly increased, and the method of the present invention can be applied in deep sub-micron or smaller CMOS devices.
As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure. [0034]

Claims

What is claimed is:

1. A trench isolation region formed in a semiconductor substrate, said trench isolation region comprising:

a first dielectric film formed on the bottom and the sidewall of a trench by a thermal oxidation using a oxidation mask with opening broader than that of said trench; and

a second dielectric film formed on the bottom of said first oxide film.

2. The trench isolation region according to claim 1, wherein said first dielectric layer is silicon oxide layer.

3. The trench isolation region according to claim 2, wherein said first oxide film is formed with oxidation performed in an oxygen containing ambient at a temperature of about 800 to 1100° C.

4. The trench isolation region according to claim 1, wherein said first dielectric layer is silicon oxynitride layer.

5. The trench isolation region according to claim 4, wherein said first oxide film is formed with oxidation performed in an N₂O ambient at a temperature of about 800 to 1100° C.

6. The trench isolation region according to claim 4, wherein said first oxide film is formed with oxidation performed in an N₂O ambient at a temperature of about 800 to 1100° C.

7. The trench isolation region according to claim 1, wherein said second dielectric layer is formed of silicon nitride.

8. The trench isolation region according to claim 1, wherein said second dielectric layer is formed of silicon oxynitride.

9. The trench isolation region according to claim 1, wherein said second dielectric layer is formed of silicon oxide.

10. The trench isolation region according to claim 9, wherein said silicon oxide is silicon dioxide.

11. The trench isolation region according to claim 9, wherein said silicon oxide is tetra-ethyl-ortho-silicate-oxide (TEOS-oxide).

12. The trench isolation region according to claim 9, wherein said silicon oxide is ozone TEOS-oxide.

13. The trench isolation region according to claim 9, wherein said silicon oxide is boro-phospho silicate glass (BPSG).

14. The trench isolation region according to claim 9, wherein said silicon oxide is phospho silicate glass (PSG).

15. The trench isolation region according to claim 9, wherein said silicon oxide is boro silicate glass, (BSG).

16. The trench isolation region according to claim 9, wherein said silicon oxide is undoped silicate glass (USG).

17. The trench isolation region according to claim 9, wherein said silicon oxide is silicon-rich oxide (SRO).

18. The trench isolation region according to claim 1, further comprising an impurity doped region beneath said bottom of said first dielectric film.

19. The trench isolation region according to claim 2, wherein said impurity-doped region is doped with the impurity ions having opposite conductive type to that of the channel of adjacent active devices.