US20010054725A1

US20010054725A1 - Semiconductor integrated circuit device and the process of manufacturing the same

Info

Publication number: US20010054725A1
Application number: US09/891,381
Authority: US
Inventors: Ryo Nagai; Norikatsu Takaura; Hisao Asakura
Original assignee: Individual
Current assignee: Longitude Licensing Ltd
Priority date: 2000-06-27
Filing date: 2001-06-27
Publication date: 2001-12-27
Anticipated expiration: 2021-06-27
Also published as: TW495967B; KR100713057B1; US6399453B2; JP2002016237A; KR20020001604A

Abstract

This invention obtains desired operating characteristics from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9 n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9 n to convert it into p-type amorphous silicon 9 p. Amorphous silicon 9 p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.

Description

BACKGROUND OF THE INVENTION

This invention is in relation to a semiconductor integrated circuit device and the method of its fabrication, and in particular to a semiconductor integrated circuit device having an MISFET (metal-insulator-semiconductor field-effect transistor) with p-type-conductive silicon gate electrodes.

N-type silicon gate electrodes are normally used in a CMOS (complementary metal-oxide semiconductor) device in which n-channel MISFETs and p-channel MISFETs are formed in the same substrate. In this type of CMOS device, the n-channel MISFETs are often in the surface-channel configuration with the p-channel MISFETs in the embedded-channel configuration.

When, however, as processes of fabricating semiconductor integrated circuit devices continually become finer, a designing process with a fineness of 0.2 μm or narrower is applied to the p-channel MISFET, the embedded-channel configuration is suspected to be insufficient in terms of preventing the short channel effect. The p-channel MISFET will thus have to be in the surface-channel configuration with p-type silicon gate electrodes. The CMOS device in the so-called dual-gate configuration, which comprises an n-channel MISFET with n-type silicon gate electrodes and a p-channel MISFET with p-type silicon gate electrodes, is being considered.

P-type impurities such as boron (B) are implanted in the p-type silicon gate electrode. However, since boron has a high diffusion coefficient in the gate-insulating film, boron may encroach into the substrate of the p-channel MISFET and cause a change in the concentration of boron in the channel region. The threshold voltage of the MISFET is thus shifted, its avalanche breakdown voltage deteriorates, and its operating characteristics will be broadly dispersed.

The method for preventing the shift in the threshold voltage caused by the change in the concentration of boron in the channel region has been disclosed in Official Patent Gazette H.6-275788. Boron ions are implanted into an n-type polysilicon film, into which n-type impurities have been uniformly placed, and convert the film into p-type polysilicon. The gate electrodes are then formed by patterning this polysilicon film. After that, impurities are implanted into the substrate with the gate electrodes acting as masks for self-alignment. Here, since the activation temperature of the implanted impurities is set rather low, in the range from 800 to 900° C., the diffusion of boron is prevented.

SUMMARY OF THE INVENTION

The inventors, however, found that when boron ions are implanted in the polycrystalline silicon film, boron atoms reach the gate-insulating film and even the interface with the substrate by the channeling effect. The result is a change in the concentration of boron in the channel region.

Moreover, when the gate electrodes are used as masks for the self-aligned implantation of impurities in the substrate, the impurities are simultaneously implanted in the polycrystalline silicon film, which configures the gate electrodes. The threshold voltage would then be expected to change and cause deterioration in the reproducibility of the MISFET's operating characteristics.

The objective of this invention is to provide a technique that can obtain the desired operating characteristics for an MISFET with p-type silicon gate electrodes.

The objectives and novel features of this invention will be clarified by the following specification description together with accompanying drawings.

A typical example of the invention disclosed in this application is briefly summarized in the following.

(1) The semiconductor integrated circuit device of this invention having an MISFET comprises:

a gate-insulating film located on the substrate;

gate electrodes, which are located on the gate-insulating film and constructed of the p-type polycrystalline silicon film, in which p-type impurities and n-type impurities have been implanted;

an insulating film, which is located over the p-type polycrystalline silicon film and has the same flat form as the p-type polycrystalline silicon film; and

the source and drain of a p-channel or of an n-channel, which are located in the substrate on both sides of the gate electrode.

(2) The method of fabricating a semiconductor integrated circuit device of this invention, when forming an MISFET with p-type silicon gate electrodes, comprises the steps of:

forming a gate-insulating film on the surface of the substrate;

depositing an amorphous silicon film on the gate-insulating film;

forming an n-type amorphous silicon film by ion-implanting n-type impurities in the amorphous silicon film;

converting the n-type amorphous silicon film into a p-type amorphous silicon film by ion-implanting p-type impurities in the n-type amorphous silicon film;

converting the p-type amorphous silicon film into a p-type polycrystalline silicon film by a process of crystallization;

forming gate electrodes by etching the insulating film, which has been deposited on the p-type polycrystalline silicon film immediately before this process, and p-type polycrystalline silicon film in turn; and

forming a semiconductor region in which the source and drain are to be constructed.

Referring to the method described above, implanting the n-type impurities in the p-type polycrystalline silicon film, of which the gate electrodes are constructed, prevents the diffusion of the p-type impurities such as boron, which have been injected in said p-type polycrystalline silicon film. This prevents changes in the concentration of boron in the channel region.

Again referring to the method described above, the channeling effect is prevented by implanting the n-type impurities and p-type impurities in the amorphous silicon film, which has been deposited over the gate-insulating film. As a result, changes in the concentration of boron in the channel region, which are caused by the ion-implanted impurities reaching the gate-insulating film and even the interface with the substrate, are prevented.

Again referring to the method described above, the concentration of impurities in the p-type polycrystalline silicon film, of which the gate electrodes are constructed, and the concentration of impurities in the semiconductor region, of which the source and drain are constructed, are optimized independently. As a result, the optimal device configuration for an MISFET can easily be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0027]
FIG. 2 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0028]
FIG. 3 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0029]
In FIG. 4, ([0030] a) and (b) are magnified cross-sectional views of part of the semiconductor substrate and show the method for fabricating DRAM, which is one embodiment of this invention.
FIG. 5 is a graph that shows the concentration of impurities in the n-type amorphous silicon and p-type amorphous silicon films. [0031]
In FIG. 6, ([0032] a), (b), and (c) are magnified cross-sectional views of part of the semiconductor substrate and show the method for fabricating DRAM, which is one embodiment of this invention.
FIG. 7 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0033]
FIG. 8 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0034]
FIG. 9 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0035]
In FIG. 10, ([0036] a), (b), and (c) are schematic magnified views of the semiconductor substrate and respectively show the memory-cell-selecting MISFET, n-channel MISFET, and p-channel MISFET of DRAM, which is one embodiment of this invention.
FIG. 11 is a schematic magnified view of the semiconductor substrate and shows the p-type silicon gate electrode of the p-channel MISFET, which is one embodiment of this invention. [0037]
FIG. 12 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0038]
FIG. 13 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0039]
FIG. 14 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0040]
FIG. 15 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0041]
FIG. 16 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0042]
FIG. 17 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0043]
FIG. 18 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0044]
FIG. 19 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0045]
FIG. 20 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0046]
FIG. 21 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0047]
FIG. 22 is a cross-sectional view through the key parts of the semiconductor substrate and shows the method for fabricating DRAM, which is one embodiment of this invention. [0048]
FIG. 23 is a graph that shows the relation of the gate voltage and drain current for the p[0049] ⁺-gate p-channel MISFET and n⁺-gate p-channel MISFET.
FIG. 24 is a graph that shows differences in threshold voltage between p[0050] ⁺-gate p-channel MISFETs and n⁺gate p-channel MISFETs.
FIG. 25 is a graph that shows the dispersion in threshold voltage of the p[0051] ⁺-gate p-channel MISFET.
FIG. 26 is a graph that shows the effect of the implantation of phosphorus in p[0052] ⁺-gate p-channel MISFETs on differences in threshold voltage between p⁺-gate p-channel MISFETs and n⁺-gate p-channel MISFETs.
FIG. 27 is a graph that shows the effect of the implantation of phosphorus on the dispersion in threshold voltage of p[0053] ⁺-gate p-channel MISFETs.
FIG. 28 is a graph that shows the dispersion in threshold voltage of the n[0054] ⁺-gate p-channel MISFET and n⁺gate n-channel MISFET.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

This invention is described below in detail based on an embodiment shown in accompanying drawings. [0055]
Identical numerical references in the figures describing the embodiment refer to the same items and their descriptions are not repeated. [0056]
The method for fabricating DRAM (dynamic random access memory), which is one embodiment of this invention, is described with the use of FIGS. [0057] 1 to 22.
As shown in FIG. 1, p-[0058] type substrate 1 with a specific resistance of approximately 10 Ωcm is prepared, and groove 2 is formed in the major surface of this substrate 1. Thermal oxidation is applied to substrate 1 to form silicon oxide film 3. After that, a silicon oxide film is deposited, and polished by CMP (chemical-mechanical polishing) so that a silicon oxide film only remains in groove 2. Isolation region 4 is thus formed.
Moreover, n-type impurities such as phosphorus (P) ions are implanted in the region of [0059] substrate 1, where memory cells are to be formed (region A: memory array), to form n-type semiconductor region 5. P-type impurities such as boron (B) ions are implanted in the memory array and part of the peripheral circuit (region B), (the region where an n-channel MISFET is to be formed), to form p-type well 6. N-type impurities such as phosphorus ions are implanted in the other part of the peripheral circuit (region B), (the region where a p-channel MISFET is to be formed), to form n-type well 7. After the ion implantation of boron and phosphorus, impurities such as boron fluoride (BF₂) ions are implanted in p-type well 6 and n-type well 7 for adjusting the threshold voltage of the MISFET. N-type semiconductor region 5 is aimed to prevent the encroachment of noise from the input/output circuit into p-type well 6 of the memory array via substrate 1.
As shown in FIG. 2, the surfaces of both p-[0060] type well 6 and n-type well 7 are wet-cleaned by using a solution of hydrofluoric acid (HF). Substrate 1 is then wet-oxidized at approximately 850° C. to form clean gate-insulating film 8, made of silicon oxide with a depth of approximately 6 to 7 nm, over the surfaces of both p-type well 6 and n-type well 7. An amorphous silicon film with a depth of 100 nm or less, for example 70 nm or so, is then deposited on the surface of gate-insulating film 8 by chemical vapor deposition (CVD). After that, the n-type impurities, for example phosphorous ions, are implanted over the entire surface of this amorphous silicon film to form n-type amorphous silicon film 9 n.
As shown in FIG. 3, p-type impurities such as boron ions are then implanted with [0061] photoresist pattern 10 as the mask. Accordingly, n-type amorphous silicon film 9 n in the region where the p-channel MISFETs of the memory array (region A) and peripheral circuit (region B) are to be formed, is converted to p-type amorphous silicon film 9 p.
In FIG. 4, ([0062] a) and (b) are schematic magnified views that show the method for fabricating n-type amorphous silicon film 9 n and p-type amorphous silicon film 9 p. Firstly, as shown in FIG. 4 (a), phosphorus ions are implanted over the entire surface of the amorphous silicon film, which has been deposited on the surface of gate-insulating film 8, to form n-type amorphous silicon film 9 n. After that, as shown in FIG. 4 (b), boron ions are implanted with photoresist pattern 10 as the mask. Since the conductivity type of exposed n-type amorphous silicon film 9 n is reversed so that it becomes p-type amorphous silicon film 9 p, n-type amorphous silicon film 9 n and p-type amorphous silicon film 9 p have been formed as the same amorphous silicon film.
Here, as shown in FIG. 5, in order to reverse the conductivity type of n-type [0063] amorphous silicon film 9 n so that it becomes p-type amorphous silicon film 9 p, the dosage of boron ions to be implanted in n-type amorphous silicon film 9 n should be relatively greater than the dosage of phosphorus ions which has been implanted. For example, with the accelerating energy of 10 keV applying a dosage of 2×10¹⁵cm⁻²as the conditions of phosphorus-ion implantation, the accelerating energy of 5 keV applying a dosage of 3×10¹⁵cm⁻²are suitable conditions for boron-ion implantation.
In addition, to reverse the conductivity type of n-type [0064] amorphous silicon film 9 n to that of p-type amorphous silicon film 9 p without implanting excess boron ions, it is desired that the concentration of impurities in n-type amorphous silicon film 9 n be set as low as possible. However, on the other hand, when the concentration of impurities in n-type amorphous silicon film 9 n is low, the problem of depletion in n-type amorphous silicon film 9 n arises.
When optimization of the concentration of impurities in n-type [0065] amorphous silicon film 9 n and the concentration of impurities in p-type amorphous silicon film 9 p is required, n-type amorphous silicon film 9 n and p-type amorphous silicon film 9 p are formed by, for example, the procedure shown in FIG. 6 (a), (b), and (c). Firstly, as shown in FIG. 6 (a), phosphorus ions are implanted to a relatively low concentration over the entire surface of the amorphous silicon film, which has been deposited on the surface of gate-insulating film 8, to form n-type amorphous silicon film 9 n. After that, as shown in FIG. 6 (b), boron ions are implanted, with photoresist pattern 10 p as the mask, to reverse the conductivity type of n-type amorphous silicon film 9 n so that it becomes p-type amorphous silicon film 9 p. Then, as shown in FIG. 6 (c), phosphorus ions are implanted, with photoresist pattern 10 n (the inverse of photoresist pattern 10 p) as the mask. Consequently, the number of phosphorus atoms in n-type amorphous silicon film 9 n can be optimized to higher concentration as designed.
After removing [0066] photoresist pattern 10, as shown in FIG. 7, substrate 1 is annealed at 950° C. for 10 to 60 seconds to crystallize n-type amorphous silicon film 9 n and p-type amorphous silicon film 9 p. This converts n-type amorphous silicon film 9 n to n-type polycrystalline silicon film 9 nc, and p-type amorphous silicon film 9 p to p-type polycrystalline silicon 9 pc.
In an alternative method, phosphorus ions are implanted over the entire surface of the amorphous silicon film to form n-type [0067] amorphous silicon film 9 n, then this n-type amorphous silicon film 9 n is crystallized by annealing so that it becomes n-type polycrystalline silicon film 9 nc. Boron ions are then implanted in n-type polycrystalline silicon film 9 nc with photoresist pattern 10 as the mask. As a result, some of n-type polycrystalline silicon film 9 nc is converted to p-type polycrystalline silicon film 9 pc.
Next, sputtering is used to deposit a tungsten nitride (WN) film to a depth of approximately 5 nm and a tungsten (W) film to a depth of approximately 100 nm on n-type [0068] polycrystalline silicon film 9 nc and p-type polycrystalline silicon film 9 pc. Silicon nitride film 11 is then deposited to a depth of approximately 150 nm by CVD.
After that, [0069] gate electrodes 9A, 9B, and 9C are formed by patterning these films with a photoresist as the mask. Gate electrode 9A functions not only as a gate electrode of the memory-cell-selecting MISFET but also as word line WL outside the active region. The base of this gate electrode 9A (word line WL) is made of p-type polycrystalline silicon film 9 pc. Gate electrode 9B functions as a gate electrode of the n-channel MISFET of the peripheral circuit, and the base of this gate electrode 9B is made of n-type polycrystalline silicon film 9 nc. Furthermore, gate electrode 9C functions as a gate electrode of the p-channel MISFET of the peripheral circuit, and the base of this gate electrode 9C is made of p-type polycrystalline silicon film 9 pc.
Since [0070] gate electrode 9A (word line WL) is mainly made up of a tungsten (W) film and a polycrystalline silicon film, that is, it is in the so-called polymetal configuration, its resistance is lower than that of a gate electrode made up of a polycrystalline silicon film. As a consequence, signal delays in the word lines are reduced. Gate electrode 9A (word line WL) can also be made up of a bilayer film, which includes a refractory-metal silicide film and a polycrystalline silicon film, i.e., the so-called polycide configuration. In the same way as with the polymetal configuration, the resistance of a gate electrode in the polycide configuration is lower than that of a gate electrode made up of only a polycrystalline silicon film, so signal delays in the word lines are reduced.
The tungsten nitride (WN) film, which is deposited between the tungsten (W) film and the polycrystalline silicon film, functions as a barrier material. This film prevents reaction between the tungsten (W) film and the polycrystalline silicon film during high-temperature annealing and thus the formation of a high-resistance silicide layer at their interface. A tungsten nitride (WN) film is not the only suitable barrier material; a titanium nitride (TiN) film can also be used. [0071]
The method of using hydrofluoric acid (HF), etc., to remove the dry-etching residue and the photoresist residue, which have remained on the surface of [0072] substrate 1, is described in the following paragraphs.
As shown in FIG. 8, p-type impurities such as boron ions are implanted in n-well [0073] 7 of the peripheral circuit to form, on both sides of gate electrode 9C, p⁻-type semiconductor regions 12 in n-well 7. N-type impurities such as phosphorus ions are then implanted in p-well 6 of the peripheral circuit to form, on both sides of gate electrode 9B, n⁻-type semiconductor regions 13 in p-well 6. Furthermore, n−type impurities such as phosphorus ions are implanted in p-well 6 of the memory array to form, on both sides of gate electrode 9A, n-type semiconductor regions 14 in p-well 6. The creation of memory-cell-selecting MISFET Qs is thus, almost complete. Substrate 1 is also annealed at 950° C. for approximately 10 seconds after the ion implantation.
As shown in FIG. 9, [0074] silicon nitride film 15 is deposited on substrate 1 by plasma CVD to a depth of approximately 50 nm, and silicon nitride film 15 in the memory array is then covered by a photoresist. After that, silicon nitride film 15 in the peripheral circuit is anisotropically etched. As a result, side-wall spacers 16 are formed on sidewalls of gate electrodes 9B and 9C. Silicon nitride film 15 in the memory array acts as an etching stopper to prevent etching of the silicon oxide film in groove 2 of element region 4, during the later step of forming contact holes (openings) in the space between gate electrodes 9A (word line WL) by dry etching.
After removing said photoresist, p[0075] ⁺-type impurities such as boron ions are implanted in n-well 7 of the peripheral circuit to form p⁺-type semiconductor regions 17 (source and drain) for the p-channel MISFET. N-type impurities such as arsenic (As) ions are implanted in p-well 6 of the peripheral circuit to form n⁺-type semiconductor regions 18 (source and drain) for the n-channel MISFET. In addition, substrate 1 is annealed at 950° C. for 10 seconds after the ion implantation. The creation of p-channel MISFET Qp and n-channel MISFET Qn of the peripheral circuit is thus, almost complete.
In FIG. 10, ([0076] a), (b), and (c)are schematic magnified views of memory-cell-selecting MISFET Qs, n-channel MISFET Qn, and p-channel MISFET Qp. The base of gate electrode 9A (word line WL) for memory-cell-selecting MISFET Qs is made of p-type polycrystalline silicon film 9 pc, in which phosphorus and boron ions have been implanted. Gate electrode 9A (word line WL) is thus in the so-called p⁺-gate n-channel configuration ((a) in FIG. 10). The base of gate electrode 9B for n-channel MISFET Qn is made of n-type polycrystalline silicon film 9 nc, in which phosphorus ions have been implanted. Gate electrode 9B is thus in the so-called n⁺-gate n-channel configuration ((b) in FIG. 10). Furthermore, the base of gate electrode 9C for p-channel MISFET Qp is made of p-type polycrystalline silicon film 9 pc, in which phosphorus and boron ions have been implanted. Gate electrode 9C is thus in the so-called p⁺-gate p-channel configuration ((c)in FIG. 10).
FIG. 11 is a schematic magnified view of p-channel MISFET Qp. Though the base of [0077] gate electrode 9C is made of p-type polycrystalline silicon film 9 pc, in which phosphorus and boron ions have been implanted, the concentration of boron must be higher than that of phosphorus in p-type polycrystalline silicon film 9 pc.
Next, as shown in FIG. 12, spin-on-glass (SOG) [0078] film 19 is formed over substrate 1 to a depth of approximately 300 nm by spin-coating. Substrate 1 is then annealed at 800° C. for approximately 60 seconds to sinter spin-on-glass (SOG) film 19.
After [0079] silicon oxide film 20 is deposited to a depth of approximately 600 nm on spin-on-glass (SOG) film 19, this silicon oxide film 20 is polished by CMP to flatten its surface. Silicon oxide film 20 is deposited by plasma CVD, for example, tetraethyl orthosilicate (TEOS: Si(OC₂H₃)₄) and ozone (O₃) as source gases.
Furthermore, [0080] silicon oxide film 21 is deposited to a depth of approximately 100 nm on silicon oxide film 20. This silicon oxide film 21 is deposited to cover the fine scratches on the surface of said silicon oxide film 20 that are a result of CMP. Silicon oxide film 21 is deposited by plasma CVD, for example, TEOS and O₃as source gases. As an alternative to silicon oxide film 21, a phospho-silicate glass (PSG) film can be deposited on silicon oxide film 20.
Moreover, [0081] photoresist 22 is formed on silicon oxide film 21. Silicon oxide films 20 and 21 and spin-on-glass (SOG) film 19, located on the upper part of n-type semiconductor regions 14 (source and drain) of memory-cell-selecting MISFET Qs, are removed by dry etching with this photoresist 22 as the mask.
In addition, said etching is performed under the following condition. The etching rates of [0082] silicon oxide films 20 and 21 and spin-on-glass (SOG) film 19 are greater than that of silicon nitride film 15. As a result, silicon nitride film 15 which covers the upper parts of n-type semiconductor region 14 and isolation region 4 must not be completely etched out.
Next, [0083] contact hole 23 is formed over one (source or drain) n-type semiconductor region 14 and contact hole 24 is formed over the other (source or drain) n-type semiconductor region 14. For this process, said photoresist 22 is used as a mask for dry-etching to remove silicon nitride film 15 and gate-insulating film 8 over respective n-type semiconductor regions 14 (source and drain) of the memory-cell-selecting MISFET Qs.
The conditions of this etching are such that the [0084] silicon nitride film 15 is etched more quickly than the silicon oxide films (the silicon oxide films in gate-insulating film 8 and isolation region 4) so that n-type semiconductor region 14 and isolation region 4 are not deeply etched. The conditions of this etching are also such that silicon nitride film 15 is anisotropically etched so that silicon nitride film 15 remains on the sidewalls of gate electrodes 9A (word lines WL). Contact holes 23 and 24 with their fine diameters, below the limitations of photolithographic resolution, are formed by a method that is self-aligning with respect to gate electrodes 9A (word lines WL).
Next, [0085] photoresist 22 is removed. A polycrystalline silicon film, doped with n-type impurities (for example, phosphorous), is deposited by CVD on silicon oxide film 21, and plugs 25 are then formed of the materials that remain inside contact holes 23 and 24 after CMP has been used to polish this polycrystalline silicon film as shown in FIG. 13.
Next, [0086] silicon oxide film 26 is deposited to a thickness of approximately 200 nm on silicon oxide film 21, and substrate 1 is annealed at approximately 800° C. Silicon oxide film 26 is deposited by plasma CVD, for example, TEOS and O₃as source gases. Furthermore, n-type impurities in the polycrystalline silicon film which constitutes plugs 25 diffuse by this annealing into n-type semiconductor region 14 (source and drain) of the memory-cell-selecting MISFET Qs from the bottom of contact holes 23 and 24. The resistance of n-type semiconductor region 14 (source and drain) is thus lowered.
Next, [0087] silicon oxide film 26 on said contact hole 23 is removed by dry-etching with a photoresist as a mask and the surfaces of plugs 25 are exposed. Said photoresist is then removed. A new photoresist is then used as a mask for dry etching through silicon oxide films 26, 21, and 20, SOG film 19, and gate-insulating film 8 in the peripheral circuit region. Contact hole 27 is thus made over n⁺-type semiconductor region 18 (source and drain) of the n-channel MISFET Qn, and contact hole 28 is made over p⁺-type semiconductor region 17 (source and drain) of the p-channel MISFET Qp.
Next, said photoresist is removed and bit line BL and first-[0088] layer wiring 29 are then formed on silicon oxide film 26 as shown in FIG. 15. For example, a titanium (Ti) film with a thickness of approximately 50 nm and a TiN film with a thickness of approximately 50 nm are deposited on silicon oxide film 26 by sputtering; further films, of W with a thickness of approximately 150 nm and of silicon nitride 30 a with a thickness of approximately 200 nm, are then deposited on the resulting surface by CVD. A photoresist is then used as a mask for patterning these films to form bit line BL and first-layer wiring 29.
A Ti film is deposited on [0089] silicon oxide film 26, and the Ti film and substrate 1 are then made to react by applying annealing at approximately 800° C. to substrate 1. This forms a layer of low-resistance titanium silicide (TiSi₂) 31 over the surfaces of p⁺-type semiconductor region 17 (source and drain) of p-channel MISFET Qp, n⁺-type semiconductor region 18 (source and drain) of n-channel MISFET Qn, and plugs 25 embedded in contact holes 23. The contact resistance of wiring (bit line BL and first-layer wiring 29) connected to p⁺-type semiconductor region 17, n⁺ type semiconductor region 18, and plugs 25 is thus reduced. Furthermore, the sheet resistance can be reduced to 2Ω/□ or less because bit line BL is constituted with the structure of W/TiN/Ti, so that bit line BL and first-layer wiring 29 in the peripheral circuits can be concurrently formed in the same process.
Next, said photoresist is removed. [0090] Sidewall spacers 30 b are then formed on the sidewalls of respective bit line BL and first-layer wiring 29. In order to form sidewall spacers 30 b, a silicon nitride film is deposited on a whole region including bit line BL and first-layer wiring 29 and this silicon nitride film is then anisotropically etched.
Next, [0091] SOG film 32 is spin-coated on a whole region including bit line BL and first-layer wiring 29 to a thickness of approximately 300 nm. Substrate 1 is then annealed at 800° C. for approximately one minute to sinter SOG film 32 as shown in FIG. 16.
Next, [0092] silicon oxide film 33 is deposited on SOG film 32 to a thickness of approximately 600 nm. This silicon oxide film 33 is then polished by CMP to flatten its surface. Silicon oxide film 33 is deposited by plasma CVD, for example, TEOS and O₃as source gases.
Next, [0093] silicon oxide film 34 is deposited to a thickness of approximately 100 nm on silicon oxide film 33. This silicon oxide film 34 is deposited to cover the fine scratches which have been created by CMP on the surface of said silicon oxide film 33. Silicon oxide film 34 is deposited by plasma CVD, for example, TEOS and O₃as source gases.
Next, [0094] silicon oxide films 34 and 33, SOG film 32, and silicon oxide film 26 over plugs 25 embedded in contact holes 24 are removed by dry-etching, using a photoresist as a mask to form through holes 35 which reach the surfaces of plugs 25. The conditions of this etching are such that the silicon nitride film is etched more quickly than the silicon oxide films 34, 33, and 26, and SOG film 32 so that silicon nitride film 30 a on bit line BL and sidewall spacers 30 b are not deeply etched even when there is a deviation between the alignments of through hole 35 and bit line BL. Through hole 35 is thus formed in a manner such that is self-aligned with bit line BL.
Next, said photoresist is removed and plugs [0095] 36 are formed inside through holes 35. Specifically, a polycrystalline silicon film to which n-type impurities (for example, phosphorous) have been doped is deposited on silicon oxide film 34. This polycrystalline silicon film is then etched back and the polycrystalline silicon film remains in through holes 35 to form plugs 36.
Next, [0096] silicon nitride film 37 is deposited on silicon oxide film 34 to a thickness of approximately 100 nm by CVD as shown in FIG. 17. Silicon oxide film 38 is then formed on silicon nitride film 37 to a thickness of approximately 1.3 μm. Next, grooves 39 are formed over through holes 35 by dry etching using a photoresist as a mask to remove silicon oxide film 38 and silicon nitride film 37. Silicon oxide film 38 is deposited by plasma CVD, for example, TEOS and 03 as source gases.
Next, said photoresist is removed. [0097] Amorphous silicon film 40 is then deposited by CVD, at approximately 600° C., on silicon oxide film 38 as shown in FIG. 18. This amorphous silicon film 40 is used as a material of the storage electrode of a capacitor. Materials other than amorphous silicon film 40 that are suitable for use as the storage electrode include metal films such as a film 40 of ruthenium (Ru) or of TiN.
Next, [0098] SOG film 41 is spin-coated on amorphous silicon film 40 to a thickness (for example, approximately 2 μm) that exceeds the depth of groove 39. SOG film 41 is then etched back to expose the amorphous silicon film 40 on silicon oxide film 38.
Furthermore, [0099] amorphous silicon film 40 remains within grooves 39 (on the inner walls and bottoms) after etching back of amorphous silicon film 40 on silicon oxide film 38. This is shown in FIG. 19. Next, the storage electrode of a capacitor is formed by wet-etching of SOG film 41 inside groove 39.
Next, a tantalum oxide (Ta[0100] ₂O₅) film 42 is deposited on the storage electrode to a thickness of approximately 20 nm. This deposition is by thermal CVD at 600° C. or below, using Ta(C₂H₅)₅and O₃as source gases. Next, Ta₂O₅film 42 is crystallized by annealing substrate 1 in an atmosphere of nitrogen and at approximately 650 to 700° C. for approximately 60 seconds. Afterwards, RTA (rapid thermal annealing) at approximately 600° C. can be applied to substrate 1 in an atmosphere of oxygen. Furthermore, oxygen defects in Ta₂O₅film 42 are recovered by applying ozone-processing at 600° or below to substrate 1. Ta₂O₅film 42, to which crystallizing processing and ozone processing are applied, is used as a capacitance-insulating film material of capacitor C.
Next, a metal film of, for example, Ru or TiN is deposited to a thickness of approximately 150 nm on Ta[0101] ₂O₅film 42 by sputtering or CVD. Said metal film and Ta₂O₅ 42 film are then patterned by dry-etching using a photoresist as a mask to form capacitors C. Capacitors C are comprised of plate electrode 43 made up of a metal film (a film of Ru or of TiN), capacitance-insulating film made up of Ta₂O₅film 42, and a storage electrode made up of amorphous silicon film 40. A DRAM memory cell comprised of memory-cell-selecting MISFET Qs and capacitors C which are connected in series with the memory-cell-selecting MISFET Qs has thus been completed.
Next, a silicon oxide film is deposited on [0102] plate electrode 43 to form insulating film 44. A connecting hole is opened in the peripheral circuit region for connection to first-layer wiring 29 and for the forming of plug 45. To form plug 45, adhesive layer 45 a made up of a Ti film and a TiN film is deposited on insulating film 44, W film 45 is deposited by blanket CVD. W film 45 b and bonding layer 45 a are then etched back. It is possible to form the Ti film and TiN film by sputtering, however, CVD is also applicable. Furthermore, Ti film 46 a, aluminum (Al) film 46 b, and TiN film 46 c are deposited, in that order and by sputtering, on insulting film 44. They are then patterned to form second-layer wiring 46.
Finally, [0103] silicon oxide film 47 a, SOG film 47 b, and silicon oxide film 47 c are deposited, in that order, on second-layer wiring 46 to form interlayer insulating film 47. Plugs 48 are then formed in the same manner as second-layer wiring 46. Said silicon oxide films 47 a and 47 c are deposited by plasma CVD, for example, TEOS and O₃as source gases. Furthermore, third-layer wiring 49 is formed and the DRAM shown in FIG. 22 has almost been completed.
A passivation film is then deposited on the multiple layers of wiring and the top layer of wiring. This is not illustrated. [0104]
Next, the characteristics of these transistors are shown in FIGS. [0105] 23 to 28:
[0106] case 1, an n⁺-gate p-channel MISFET, the gate electrode of which is made up of an n-type polycrystalline silicon film in which n-type impurities (for example, phosphorous) have been implanted;
[0107] case 2, a p⁺-gate p-channel MISFET, the gate electrode of which is made up of a p-type polycrystalline silicon film in which p-type impurities (for example, boron) have been implanted, and
[0108] case 3, a p⁺-gate p-channel MISFET, the gate electrode of which is made up of a p-type polycrystalline silicon film in which n-type impurities (for example, phosphorous) and p-type impurities (for example, boron) have been implanted.
FIG. 23 shows one example of the gate voltage-drain current characteristics of n[0109] ⁺-gate p-channel MISFETs (case 1) and p⁺-gate p-channel MISFETs (case 2). The difference between the threshold voltages of the n⁺-gate p-channel MISFETs and the p⁺-gate p-channel MISFETs should be 1.1 V, as this corresponds to the band-gap width of silicon (Si). However, the threshold voltages of the p⁺-gate p-channel MISFETs are lowered in this case because of leakage of boron, and the difference thus becomes approximately 1.3 V, and dispersion of the threshold voltages is thus increased.
FIG. 24 shows the relation between the differences between the threshold voltages of n[0110] ⁺-gate p-channel MISFETs (case 1) and p⁺-gate p-channel MISFETs (case 2) and the dosages of boron ions (accelerated energy 5 keV) which are implanted in the p-type polycrystalline silicon films that configure the gate electrodes of the p⁺-gate p-channel MISFETs (case 2). The figure shows the tendency for the difference between threshold voltages to increase above 1.1 V, that is, above the band-gap width, with increasing dosage. The difference thus appears to be caused by the increased leakage of boron in the p⁺-gate p-channel MISFET that corresponds to the increased dosage.
FIG. 25 shows the relation between the dispersion (3σ) of the threshold voltages of p[0111] ⁺-gate p-channel MISFETs (case 2) and the dosages of boron ions (accelerated energy 5 keV) which are implanted in the p-type polycrystalline silicon films that configure the gate electrodes of the p⁺-gate p-channel MISFETs (case 2). The figure shows that the dispersion of threshold voltages increases with the dosage. The difference thus appears to be caused by the increased leakage of boron in the p⁺-gate p-channel MISFET that corresponds to the increased dosage.
FIG. 26 shows differences between the threshold voltages of n[0112] ⁺-gate p-channel MISFETs (case 1) and p⁺-gate p-channel MISFETs (case 2) and between the threshold voltages of n⁺-gate p-channel MISFETs (case 1) and p⁺-gate p-channel MISFETs (case 3). In the drawing, D1 indicates the value with regard to p⁺-gate p-channel MISFETs (case 2) in which boron ions have been implanted at a dosage of approximately 2×10¹⁵cm⁻²; D2 indicates the value with regard to p⁺-gate p-channel MISFETs (case 3) in which boron ions have been implanted at a dosage of approximately 2×10¹⁵cm⁻²and phosphorous ions have been implanted at a dosage of approximately 1×10¹⁴cm⁻²(accelerated energy 10 keV); and D3 indicates the value with regard to p⁺-gate p-channel MISFETs (case 3) in which boron ions have been implanted at a dosage of approximately 3×10¹⁵cm⁻²and phosphorous ions have been implanted at a dosage of approximately 2×10¹⁴cm⁻²(accelerated energy 10 keV).
FIG. 27 shows the dispersions (3σ) of threshold voltages in the p[0113] ⁺-gate p-channel MISFETs (cases 2 and 3) used to obtain D1, D2, and D3 in the above-described FIG. 26. In addition, FIG. 28 shows the dispersions (3σ) of the threshold voltages of n⁺-gate p-channel MISFETs and n⁺-gate n-channel MISFETs.
FIGS. 26 and 27 show that the dispersion of threshold voltages is suppressed at the same time as the differences in threshold voltages are decreased according to the increased dosage of phosphorous. In particular, despite the high dosage of boron, approximately 3×10[0114] ¹⁵cm², in the p⁺-gate p-channel MISFETs (case 3) as shown at D3, the differences between the threshold voltages are small because phosphorous is present. Dispersion of the threshold voltages is also suppressed and approaches the dispersion of approximately 10 mV of the n⁺-gate MISFETs shown in FIG. 28. Phosphorous coexisting with boron in a polycrystalline silicon film has priority in occupying the grain boundaries of silicon. It can be inferred that this suppresses the high-speed diffusion of boron along the grain boundaries of the silicon and prevents so-called boron leakage, in which boron reaches the channel region on the surface of a substrate.
In this embodiment, gate-insulating [0115] film 8 was made up of a silicon oxide film, however, it can be made up of an silicon oxynitride film through which boron leaks less than through a silicon oxide film. The silicon oxynitride film is formed by applying annealing at, for example, approximately 650° C., and in an atmosphere of nitrogen, to a silicon oxide layer formed on the surface of substrate 1.
In this embodiment, the diffusion of boron implanted in p-type [0116] polycrystalline silicon film 9 pc is suppressed to prevent the leakage of boron into the channel region. This is done by implanting phosphorous in p-type polycrystalline silicon film 9 pc which configures gate electrodes 9A (word lines WL) of the memory-cell-selecting MISFET Qs and in p-type polycrystalline silicon film 9 pc which configures gate electrode 9C of p-channel MISFET Qp.
In addition, when p-type [0117] polycrystalline silicon film 9 pc is formed to configure gate electrodes 9A (word lines WL) and 9C and n-type polycrystalline silicon film 9 nc is formed to configure gate electrode 9B, the channeling effect in an amorphous silicon film with a thickness of 100 nm or less can be suppressed by ion-implanting impurities into the amorphous silicon film that is deposited on the substrate. Consequently, changes in the concentrations of impurities in the channel region, caused by the phenomenon that the ion-implanted impurities reach gate-insulating film 8 and even the interface with substrate 1, can thus be prevented.
In addition, placing a [0118] silicon nitride film 11 over gate electrodes 9A (word lines WL), 9B, and 9C prevents the implantation of impurities in p-type polycrystalline silicon film 9 pc which configures gate electrodes 9A and 9C (word lines WL) and in n-type polycrystalline silicon film 9 nc which configures gate electrode 9B, during the formation of the source and drain (n-type semiconductor region 14) of memory-cell-selecting MISFET Qs, the source and drain (p⁻ type semiconductor region 12 and p⁺-type semiconductor region 17) of p-channel MISFET Qp, and the source and drain (n⁻ type semiconductor region 13 and n⁺-type semiconductor region 18) of n-channel MISFET Qn. Optimization of the concentrations of impurities in p-type polycrystalline silicon film 9 pc and n-type polycrystalline silicon film 9 nc and optimization of the concentrations of impurities in the source and drain are then possible respectively. The most suitable device structures can thus be easily obtained for memory-cell-selecting MISFET Qs, p-channel MISFET Qp, and n-channel MISFET Qn.
In addition, when forming the sources and drains of memory-cell-selecting MISFET Qs (n-type semiconductor region [0119] 14), p-channel MISFET Qp (p⁻-type semiconductor region 12 and p⁺-type semiconductor region 17), and n-channel MISFET Qn (n⁻-type semiconductor region 13 and n⁻-type semiconductor region 18), impurities are ion-implanted into substrate 1 and then activated by the application of annealing at 950° C. for approximately 10 seconds. Furthermore, to improve the reliability of the capacitance-insulating film of capacitor C, annealing is applied to crystallize the capacitance-insulating film right after it has been formed. Boron readily diffuses during annealing as described above. However, implanting phosphorous in p-type polycrystalline silicon film 9 pc suppresses the diffusion of boron which has been implanted in p-type polycrystalline silicon film 9 pc. Leakage of boron to the channel region is thus prevented, and this makes it possible to apply annealing to substrate 1. The most suitable concentration profile can thus be obtained for the sources and drains of memory-cell-selecting MISFET Qs (n-type semiconductor region 14), p-channel MISFET Qp (p⁻-type semiconductor region 12 and p⁺-type semiconductor region 17), and n-channel MISFET Qn (n⁻-type semiconductor region 13 and n⁺-type semiconductor region 18). The reliability of capacitor C is also improved.
In addition, [0120] silicon nitride film 15 which will be used as an etching stopper is formed, over gate electrodes 9A (word lines WL) of memory-cell-selecting MISFET Qs, by plasma CVD. Although this silicon nitride film contains hydrogen which facilitates the diffusion of boron, the diffusion of boron is suppressed by the phosphorous which has been implanted in p-type polycrystalline silicon film 9 pc. Leakage of boron is thus prevented, so changes in the operating characteristics of the memory-cell-selecting MISFET Qs can be suppressed by using said silicon nitride film 15. Consequently, even when p-type polycrystalline silicon film 9 pc is used as gate electrodes 9A (word lines WL) of memory-cell-selecting MISFET Qs, silicon nitride film 15 can be used as an etching stopper, so fine contact holes 23 and 24 can be formed in the spaces between gate electrodes 9A (word lines WL).
This invention has been described in detail above on the basis of an embodiment. However, this invention is not restricted to this embodiment; various modifications are possible without deviating from the essential points of the invention. [0121]
For example, the embodiment described above was an application to the method for fabricating a memory-cell-selecting MISFET of a memory array which configures a DRAM and an n-channel MISFET and p-channel MISFET in the peripheral circuits. The invention can also be applied to any method for fabricating an MISFET which has a gate electrode of p-type silicon. [0122]
Typical advantages obtained from the invention disclosed in this application are briefly described in the following paragraphs. [0123]
This invention effectively prevents the leakage of boron to the channel region by suppressing the diffusion of boron from the p-type silicon gate electrode and thus prevents changes in the operating characteristics of MISFETs in which the gate electrode is of p-type silicon. [0124]
In addition, this invention prevents the changes in concentration in the channel region that occur because of the channeling effect. Changes in the operating characteristics of an MISFET in which the gate electrode is of p-type silicon of a thickness of approximately 100 nm or less can thus be prevented. [0125]
In addition, this invention allows the independent setting of the concentrations of impurities in the p-type polycrystalline silicon film which configures the p-type silicon gate electrode and in the semiconductor region which configures the source and drain. Furthermore, the diffusion of boron from the p-type silicon gate electrode is suppressed and the leakage of boron to the channel region can be prevented, so that relatively high-temperature annealing can be applied. Thus the most suitable device structure for a given MISFET can be obtained. [0126]

Claims

What is claimed is:

1. A semiconductor integrated circuit device having an MISFET that includes:

a gate-insulating film located over a substrate;

a gate electrode, which is located over said gate-insulating film and constructed of a polycrystalline silicon film that exhibits a first conductivity and in which p-type impurities and n-type impurities have been implanted;

an insulating film, which is located over said polycrystalline silicon film and has the same flat form as said polycrystalline silicon film; and

a source and drain, which are located in said substrate, on both sides of said gate electrode, and constructed of a semiconductor region that exhibits a second conductivity.

2. A semiconductor integrated circuit device, as defined in

claim 1

, wherein said first conductivity is p-type and said second conductivity is p-type or n-type.

3. A semiconductor integrated circuit device, as defined in

claim 1

, wherein said insulating film is a silicon nitride film.

4. A semiconductor integrated circuit device having, on the same substrate:

a first MISFET that includes

a first gate-insulating film located over a substrate,

a first gate electrode, which is located over said first gate insulating film and constructed of a p-type polycrystalline silicon film, and

a source and drain, which are located in said substrate on both sides of said first gate electrode and constructed of a p-type semiconductor region; and

a second MISFET that includes

a second gate-insulating film located over a substrate,

a second gate electrode, which is located over said second gate insulating film and constructed of a p-type polycrystalline silicon film, and

a source and drain, which are located in said substrate on both sides of said second gate electrode and constructed of an n-type semiconductor region;

wherein p-type impurities and n-type impurities are implanted in the p-type polycrystalline silicon films which constitute said first gate electrode and said second gate electrode.

5. A semiconductor integrated circuit device having, on the same substrate:

a first MISFET that includes

a first gate-insulating film located over a substrate,

a second MISFET that includes

a second gate-insulating film located over a substrate,

a second gate electrode, which is located over said second gate insulating film and constructed of an n-type polycrystalline silicon film, and

wherein p-type impurities and n-type impurities are implanted in the p-type polycrystalline silicon film which constitutes said first gate electrode.

6. A semiconductor integrated circuit device having a memory cell comprising, in series connection:

an MISFET that includes

a gate-insulating film located over a substrate,

a gate electrode, which is located over said gate insulating film and constructed of a p-type polycrystalline silicon, and

a source and drain, which are located in said substrate on both sides of said gate electrode and constructed of an n-type semiconductor region; and

a capacitor;

wherein p-type impurities and n-type impurities are implanted in the p-type polycrystalline silicon film which constitutes said gate electrode.

7. A method for fabricating a semiconductor integrated circuit device having an MISFET with a p-type gate electrode, comprising the steps of:

(a) forming a gate-insulating film over the surface of the substrate;

(b) depositing an amorphous silicon film over said gate-insulating film;

(c) forming an n-type film by ion-implanting n-type impurities in said amorphous silicon film;

(d) converting said n-type film into a p-type film by ion-implanting p-type impurities in said n-type film; and

(e) forming said gate electrode by etching said p-type film.

8. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 7

, wherein said n-type impurities are phosphorus and said p-type impurities are boron.

9. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 7

, wherein said gate insulating film is a silicon oxynitride film.

10. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 7

, and further comprising the step, after step (d), of crystallizing said p-type film.

11. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 7

, and further comprising the step, after step (c), of crystallizing said n-type film.

12. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 7

, and further comprising the steps, before step (e), of depositing a refractory-metal film on said p-type film and, in step (e), etching, in order, said refractory-metal film and said p-type film.

13. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 7

, and further comprising the steps, before step (e), of depositing a refractory-metal film and insulating film on said p-type film and, in step (e), etching, in order, said insulating film, said refractory-metal film and said p-type film.

14. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 7

, and further comprising the step of (f) forming semiconductor regions to constitute a source and drain.

15. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 7

, and further comprising the steps of:

(f) forming semiconductor regions to constitute a source and drain; and

(g) forming a capacitor connected to one of the semiconductor regions that constitute said source and drain.

16. A method for fabricating a semiconductor integrated circuit device having a first MISFET with a source and drain constructed of p-type semiconductor regions and a second MISFET with a source and drain constructed of n-type semiconductor regions, comprising the steps of:

(a) forming a gate-insulating film over the surface of the substrate;

(b) depositing an amorphous silicon film over said gate-insulating film;

(c)forming an n-type film by ion-implanting n-type impurities in said amorphous silicon film;

(d) converting said n-type film, at least in the region where said first MISFET will be formed, into a p-type film by ion-implanting p-type impurities in said n-type film; and

(e) forming the gate electrode of said first MISFET by etching said p-type film.

17. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

18. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, wherein said gate insulating film is a silicon oxynitride film.

19. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, and further comprising the step, after said step (d), of crystallizing said p-type film.

20. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, and further comprising the step, after said step (c), of crystallizing said n-type film.

21. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, and further comprising the steps, before said step (e), of depositing a refractory-metal film on said p-type film and, in step (e), etching, in order, said refractory-metal film and said p-type film.

22. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, and further comprising the steps, before said step (e), of depositing, in order, a refractory-metal film and insulating film on said p-type film, and in said step (e), etching, in order, said insulating film, said refractory-metal film, and said p-type film.

23. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, and further comprising the step of (e) forming p-type semiconductor regions to constitute the source and drain of said first MISFET.

24. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, wherein the region where said second MISFET will be formed is masked against the ion-implantation of said step (d).

25. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, wherein said step (d) includes a step in which the region where said second MISFET will be formed is masked while p-type impurities are ion-implanted in said n-type film and a step in which the region where said first MISFET will be formed is masked while n-type impurities are ion-implanted in said n-type film.

26. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, wherein the dose of said ion-implanted p-type impurities is relatively larger than the dose of said ion-implanted n-type impurities.

27. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, wherein the thickness of said amorphous silicon film is 100 nm or less.

28. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 16

, and further comprising the steps of:

(f) forming p-type semiconductor regions which constitute the source and drain of said first MISFET;

(g) forming, in order, a silicon nitride film and a silicon oxide film on said substrate;

(h) using a photoresist pattern as a mask in forming an opening in said silicon oxide film and said silicon nitride film by etching said silicon oxide film with said silicon nitride film as an etching stopper and then etching said silicon nitride film; and

(i) forming plugs inside said opening.

29. A method for fabricating a semiconductor integrated circuit device having a first MISFET with a source and drain constructed of a p-type semiconductor region and a second MISFET having a source and drain constructed of an n-type semiconductor region, comprising the steps of:

(a) forming a gate-insulating film over the surface of the substrate;

(b) depositing an amorphous silicon film over said gate-insulating film;

(d) converting said n-type film, in the region where said first MISFET will be formed, into a p-type film by ion-implanting p-type impurities in said n-type film; and

(e) forming the gate electrode of said first MISFET by etching said p-type film and forming the gate electrode of said second MISFET by etching said n-type film.

30. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

31. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

, wherein said gate insulating film is a silicon oxynitride film.

32. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

, and further comprising the steps, after said step (d), of crystallizing said p-type film and n-type film.

33. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

, and further comprising the steps, after said step (c), of crystallizing said n-type film.

34. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

, and further comprising the steps, before said step (e), of depositing a refractory-metal film on said p-type film and said n-type film, and in step (e), etching, in order, said refractory-metal film and said p-type film and, simultaneously and in order, said refractory-metal film and said n-type film.

35. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

, and further comprising the steps, before said step (e), of depositing, in order, a refractory-metal film and insulating film on said p-type and n-type films, and in step (e), etching, in order, said cap of insulating film, said refractory-metal film, and said p-type film and, simultaneously and in order, said insulating film, said refractory-metal film, and said n-type film.

36. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

, and further comprising the steps of (f) forming p-type semiconductor regions which constitute the source and drain of said first MISFET and forming n-type semiconductor regions which constitute the source and drain of said second MISFET.

37. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

38. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

39. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

40. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

, wherein the thickness of said amorphous silicon film is 100 nm or less.

41. A method for fabricating a semiconductor integrated circuit device, as defined in

claim 29

, and further comprising the steps of:

(f) forming p-type semiconductor regions which constitute the source and drain of said first MISFET and forming n-type semiconductor region which constitute the source and drain of said second MISFET;

(i) forming plugs inside said opening.

42. A method for fabricating a semiconductor integrated circuit device having a memory cell in which an MISFET and a capacitor are connected in series, comprising the steps of:

(a) forming a gate-insulating film over the surface of the substrate;

(b) depositing an amorphous silicon film over said gate-insulating film;

(d) converting said n-type film into a p-type film by ion-implanting p-type impurities in said n-type film;

(e) forming a gate electrode by etching said p-type film;

(f) forming n-type semiconductor regions which constitute the source and drain of said MISFET;

(g) forming the first capacitor electrode connected to one of the n-type semiconductor regions which constitute said source and drain;

(h) forming a dielectric film on the surface of said first capacitor electrode;

(i) annealing said substrate; and

(j) forming the second capacitor electrode on said dielectric film.