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US20010042897A1 - Copper fuse for integrated circuit - Google Patents

Copper fuse for integrated circuit Download PDF

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Publication number
US20010042897A1
US20010042897A1 US09/495,625 US49562500A US2001042897A1 US 20010042897 A1 US20010042897 A1 US 20010042897A1 US 49562500 A US49562500 A US 49562500A US 2001042897 A1 US2001042897 A1 US 2001042897A1
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US
United States
Prior art keywords
copper
pads
copper pads
fuse
metal
Prior art date
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Granted
Application number
US09/495,625
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US6455913B2 (en
Inventor
Wen-Kuan Yeh
Chin-Yung Lin
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United Microelectronics Corp
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Individual
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Filing date
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Priority to US09/495,625 priority Critical patent/US6455913B2/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, CHIH-YUNG, YEH, WEN-KUAN
Publication of US20010042897A1 publication Critical patent/US20010042897A1/en
Application granted granted Critical
Publication of US6455913B2 publication Critical patent/US6455913B2/en
Anticipated expiration legal-status Critical
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    • H10W20/493

Definitions

  • the present invention relates to a semiconductor structure in integrated circuit (IC). More particularly, the present invention relates to a copper fuse of semiconductor structure for IC.
  • the invention provides a structure of a copper fuse in an IC, by which structure RC delay is reduced.
  • the invention provides a structure of a copper fuse for an IC, which fuse includes two copper pads formed on a semiconductor substrate where the copper pads are isolated from each other with dielectrics.
  • a metal line formed over the semiconductor substrate covers the two metal pads wherein one end of the metal line is connected to one of the two copper pads and the other end of the metal line is connected to the other of the two copper pads.
  • a passivation layer formed over the semiconductor substrate covers the two copper pads.
  • FIG. 1 is a schematic, cross-sectional view illustrating a structure of a copper fuse according to one preferred embodiment of this invention.
  • FIG. 2 is a schematic, top view of FIG. 1, where the cross-sectional view along the line I-I is shown in FIG. 1.
  • a tungsten plug is subsequently formed in the device region 100 a of an IC structure.
  • Such metallization processes as wiring line and vias are carried out by damascene, for example, where the wiring lines and the vias are isolated from with dielectrics 102 .
  • a passivation layer 104 a is deposited and then patterned by photolithography to form a pad window such that a metal pad 106 a made of copper, for example, is exposed.
  • a barrier layer 108 a such as TiN or TaN is formed on the metal pad layer 106 a .
  • An aluminum layer 110 a is formed and patterned to complete the wire bonding process of the device region 100 a for the back-end process of the IC.
  • a copper fuse set up in the peripheral region 100 b is first to form two metal copper pads 106 b in the dielectrics 102 .
  • the two copper pads 106 b connected to corresponding devices (not shown) are formed by damascene, for example, when the metal pad 106 a is formed.
  • the passivation layer 104 b is formed when the passivation layer 104 a is formed in order to cover the two copper pads 106 b .
  • the passivation layer 106 b can be silicon oxide/silicon nitride, for example.
  • a barrier layer 108 b such as TiN or TaN formed by sputtering is then formed on the copper pads 106 b .
  • a metal layer 110 b is formed by sputtering to cover the copper pads 106 b to electrically connect the two copper pads 106 b .
  • the barrier layer 108 b is used to improve the adhesion of the copper pads 106 b and the metal layer 110 b , and the metal layer 110 b can be aluminum, for example.
  • the metal layer 110 b and the barrier layer 108 are patterned to form parallel fuses, as shown in FIG. 2.
  • One end of the metal layer 110 b is connected to one copper pad 106 b and the other end of the metal layer 1106 b is connected to the other copper pad 106 b.
  • the two copper pads 106 b and the metal line 110 b constitute the copper fuse structure of the preferred embodiment in the invention.
  • the copper pads 106 b are electrically insulated and electrically connected by the metal layer 110 b . Therefore, when any one of the fuses in FIG. 2 must be disconnected, the metal line 110 b can be blown off by laser power such that the copper pads 106 b can be prevented from being damaged.
  • the copper pads 106 b in this embodiment is covered by the passivation layer 104 b and the metal layer 110 b so that the copper pads 106 b are isolated from the air.
  • the copper pads 106 b are not exposed. Therefore, oxidation on the surface of the copper pads 104 b can be avoided.
  • the copper pads are used as a portion of the fuses, thereby reducing RC delay.
  • the process to form the copper fuses in this embodiment is compatible with the back-end process of the device region 100 a for IC structure. Thus, the manufacturing cost does not increase.
  • the copper fuse structure utilizes an aluminum metal line to cover and electrically connect to the two copper pads.
  • the copper pads serve as a part of the fuses to reduce RC delay, and in addition, the fuse is disconnected by blowing off the aluminum line.
  • the aluminum line and the passivation layer covering the copper pads is capable of preventing the copper pads from being oxidized by air.

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A copper fuse structure for integrated circuit employs two copper pads formed over a semiconductor substrate. The two copper pads are electrically insulated by dielectrics. An aluminum line is utilized to cover and electrically connect the two copper pads.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of Invention [0001]
  • The present invention relates to a semiconductor structure in integrated circuit (IC). More particularly, the present invention relates to a copper fuse of semiconductor structure for IC. [0002]
  • 2. Description of Related Art [0003]
  • As the design rule of the semiconductor process approaches or is less than 0.18 μm, copper gradually replaces aluminum as an interconnect in the metallization process since copper has lower resistance that can reduce RC delay. However, copper easily reacts with the oxygen in the surroundings to form a thin copper oxide on its surface, which leads to the failure of electrical contact. As a result, it is difficult to substitute copper for aluminum when forming a fuse in an IC as, in the IC industry, at the current line width. [0004]
  • SUMMARY OF THE INVENTION
  • The invention provides a structure of a copper fuse in an IC, by which structure RC delay is reduced. [0005]
  • As embodied and broadly described herein, the invention provides a structure of a copper fuse for an IC, which fuse includes two copper pads formed on a semiconductor substrate where the copper pads are isolated from each other with dielectrics. A metal line formed over the semiconductor substrate covers the two metal pads wherein one end of the metal line is connected to one of the two copper pads and the other end of the metal line is connected to the other of the two copper pads. A passivation layer formed over the semiconductor substrate covers the two copper pads. [0006]
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.[0007]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, [0008]
  • FIG. 1 is a schematic, cross-sectional view illustrating a structure of a copper fuse according to one preferred embodiment of this invention; and [0009]
  • FIG. 2 is a schematic, top view of FIG. 1, where the cross-sectional view along the line I-I is shown in FIG. 1.[0010]
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Referring to FIG. 1, after the formation of a MOS device and contact (not shown), a tungsten plug is subsequently formed in the [0011] device region 100 a of an IC structure. Such metallization processes as wiring line and vias are carried out by damascene, for example, where the wiring lines and the vias are isolated from with dielectrics 102. Thereafter, a passivation layer 104 a is deposited and then patterned by photolithography to form a pad window such that a metal pad 106 a made of copper, for example, is exposed. A barrier layer 108 a such as TiN or TaN is formed on the metal pad layer 106 a. An aluminum layer 110 a is formed and patterned to complete the wire bonding process of the device region 100 a for the back-end process of the IC.
  • Referring to FIG. 1 and FIG. 2 simultaneously, a copper fuse set up in the [0012] peripheral region 100 b is first to form two metal copper pads 106 b in the dielectrics 102. The two copper pads 106 b connected to corresponding devices (not shown) are formed by damascene, for example, when the metal pad 106 a is formed. Thereafter, the passivation layer 104 b is formed when the passivation layer 104 a is formed in order to cover the two copper pads 106 b. The passivation layer 106 b can be silicon oxide/silicon nitride, for example. As the passivation layer 104 a in the device region 100 a is patterned, photolithography is also employed to form an opening 112 in the passivation layer 104 b so that the two copper pads are exposed. A barrier layer 108 b such as TiN or TaN formed by sputtering is then formed on the copper pads 106 b. A metal layer 110 b is formed by sputtering to cover the copper pads 106 b to electrically connect the two copper pads 106 b. The barrier layer 108 b is used to improve the adhesion of the copper pads 106 b and the metal layer 110 b, and the metal layer 110 b can be aluminum, for example. Thereafter, the metal layer 110 b and the barrier layer 108 are patterned to form parallel fuses, as shown in FIG. 2. One end of the metal layer 110 b is connected to one copper pad 106 b and the other end of the metal layer 1106 b is connected to the other copper pad 106 b.
  • The two [0013] copper pads 106 b and the metal line 110 b constitute the copper fuse structure of the preferred embodiment in the invention. The copper pads 106 b are electrically insulated and electrically connected by the metal layer 110 b. Therefore, when any one of the fuses in FIG. 2 must be disconnected, the metal line 110 b can be blown off by laser power such that the copper pads 106 b can be prevented from being damaged.
  • The [0014] copper pads 106 b in this embodiment is covered by the passivation layer 104 b and the metal layer 110 b so that the copper pads 106 b are isolated from the air. When the back end process is complete, the copper pads 106 b are not exposed. Therefore, oxidation on the surface of the copper pads 104 b can be avoided. In addition, the copper pads are used as a portion of the fuses, thereby reducing RC delay.
  • Moreover, the process to form the copper fuses in this embodiment is compatible with the back-end process of the [0015] device region 100 a for IC structure. Thus, the manufacturing cost does not increase.
  • The copper fuse structure utilizes an aluminum metal line to cover and electrically connect to the two copper pads. The copper pads serve as a part of the fuses to reduce RC delay, and in addition, the fuse is disconnected by blowing off the aluminum line. Moreover, the aluminum line and the passivation layer covering the copper pads is capable of preventing the copper pads from being oxidized by air. [0016]
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. [0017]

Claims (9)

What is claimed is:
1. A copper fuse for an integrated circuit, comprising:
at least two copper pads, located on a semiconductor substrate; and
a metal line, one end being electrically connected to one of the two copper pads and the other end being electrically connected to the other of the two copped pads; wherein at least the two copper pads and the metal line are used as a fuse.
2. The copper fuse according to
claim 1
, wherein the metal layer includes aluminum.
3. The copper fuse according to
claim 1
, wherein a barrier layer is located between the metal line and the two copper pads.
4. The copper fuse according to
claim 3
, wherein the barrier layer includes TaN.
5. The copper fuse according to
claim 1
, further including a passivation layer covering the two copper pads.
6. A copper fuse for integrated circuit, comprising:
two copper pads, formed on a semiconductor substrate, the two copper pads insulated with a dielectrics;
a metal line having a first end and a second end, formed on the semiconductor substrate, covering the two copper pads wherein the first end is connected to one of the two copper pads and the second end is connected to the other of the two copped pads; and
a passivation layer, formed on the semiconductor substrate and covering the two copper pads
wherein the two copper pads and the metal line are used as a fuse.
7. The copper fuse according to
claim 6
, wherein the metal layer includes aluminum.
8. The copper fuse according to
claim 6
, wherein a barrier layer is located between the metal line and the two copper pads.
9. The copper fuse according to
claim 8
, wherein the barrier layer includes TaN.
US09/495,625 2000-01-31 2000-01-31 Copper fuse for integrated circuit Expired - Lifetime US6455913B2 (en)

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Application Number Priority Date Filing Date Title
US09/495,625 US6455913B2 (en) 2000-01-31 2000-01-31 Copper fuse for integrated circuit

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Application Number Priority Date Filing Date Title
US09/495,625 US6455913B2 (en) 2000-01-31 2000-01-31 Copper fuse for integrated circuit

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US20010042897A1 true US20010042897A1 (en) 2001-11-22
US6455913B2 US6455913B2 (en) 2002-09-24

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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566171B1 (en) * 2001-06-12 2003-05-20 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
WO2003085735A1 (en) * 2002-04-02 2003-10-16 Infineon Technologies Ag Beol process for cu metallizations free from al-wirebond pads
US6693343B2 (en) * 2000-12-28 2004-02-17 Infineon Technologies Ag Self-passivating Cu laser fuse
US6730982B2 (en) 2001-03-30 2004-05-04 Infineon Technologies Ag FBEOL process for Cu metallizations free from Al-wirebond pads
US20040219720A1 (en) * 2002-09-17 2004-11-04 Jeng Shin-Puu Metal fuse for semiconductor devices
US20040224444A1 (en) * 2003-01-09 2004-11-11 Katsuhiro Hisaka Fuse layout and method of trimming
US20050212081A1 (en) * 2004-03-25 2005-09-29 Hyuck-Jin Kang Fuse region of a semiconductor device and method of fabricating the same
US20060163734A1 (en) * 2005-01-24 2006-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fuse structure and method for making the same
US20090273055A1 (en) * 2004-06-29 2009-11-05 Kong-Beng Thei Fuse Structure
US7964934B1 (en) 2007-05-22 2011-06-21 National Semiconductor Corporation Fuse target and method of forming the fuse target in a copper process flow
US8030733B1 (en) * 2007-05-22 2011-10-04 National Semiconductor Corporation Copper-compatible fuse target
US20120261793A1 (en) * 2011-04-13 2012-10-18 International Business Machines Corporation Electrical fuse and method of making the same
US9245846B2 (en) * 2014-05-06 2016-01-26 International Business Machines Corporation Chip with programmable shelf life
US20170194240A1 (en) * 2016-01-05 2017-07-06 Samsung Electronics Co., Ltd. Package substrate, method for fabricating the same, and package device including the package substrate
US10170425B2 (en) * 2014-11-12 2019-01-01 International Business Machines Corporation Microstructure of metal interconnect layer
US10615119B2 (en) * 2017-12-12 2020-04-07 International Business Machines Corporation Back end of line electrical fuse structure and method of fabrication
US10991655B2 (en) * 2018-08-24 2021-04-27 Shenzhen Weitongbo Technology Co., Ltd. E-fuse and manufacturing method thereof, and memory cell
WO2022182382A1 (en) * 2021-02-24 2022-09-01 Microchip Technology Incorporated Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals
US11600566B2 (en) 2021-02-24 2023-03-07 Microchip Technology Incorporated Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7328830B2 (en) * 2002-12-20 2008-02-12 Agere Systems Inc. Structure and method for bonding to copper interconnect structures
KR100735529B1 (en) * 2006-02-09 2007-07-04 삼성전자주식회사 Semiconductor memory device and manufacturing method thereof

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US5741720A (en) * 1995-10-04 1998-04-21 Actel Corporation Method of programming an improved metal-to-metal via-type antifuse
US5731624A (en) * 1996-06-28 1998-03-24 International Business Machines Corporation Integrated pad and fuse structure for planar copper metallurgy
US6175145B1 (en) * 1997-07-26 2001-01-16 Samsung Electronics Co., Ltd. Method of making a fuse in a semiconductor device and a semiconductor device having a fuse
US6144096A (en) * 1998-10-05 2000-11-07 Advanced Micro Devices, Inc. Low resistivity semiconductor barrier layers and manufacturing method therefor

Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6844245B2 (en) 2000-12-28 2005-01-18 Infineon Technologies Ag Method of preparing a self-passivating Cu laser fuse
US6693343B2 (en) * 2000-12-28 2004-02-17 Infineon Technologies Ag Self-passivating Cu laser fuse
US20040135230A1 (en) * 2000-12-28 2004-07-15 Hans-Joachim Barth Self-passivating Cu laser fuse
US6730982B2 (en) 2001-03-30 2004-05-04 Infineon Technologies Ag FBEOL process for Cu metallizations free from Al-wirebond pads
US6806551B2 (en) 2001-06-12 2004-10-19 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
US6566171B1 (en) * 2001-06-12 2003-05-20 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
WO2003085735A1 (en) * 2002-04-02 2003-10-16 Infineon Technologies Ag Beol process for cu metallizations free from al-wirebond pads
US20040219720A1 (en) * 2002-09-17 2004-11-04 Jeng Shin-Puu Metal fuse for semiconductor devices
US7205588B2 (en) * 2002-09-17 2007-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Metal fuse for semiconductor devices
US7119414B2 (en) * 2003-01-09 2006-10-10 Oki Electric Industry Co., Ltd. Fuse layout and method trimming
US20040224444A1 (en) * 2003-01-09 2004-11-11 Katsuhiro Hisaka Fuse layout and method of trimming
US20050212081A1 (en) * 2004-03-25 2005-09-29 Hyuck-Jin Kang Fuse region of a semiconductor device and method of fabricating the same
US7352050B2 (en) * 2004-03-25 2008-04-01 Samsung Electronics Co., Ltd. Fuse region of a semiconductor region
US8174091B2 (en) 2004-06-29 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Fuse structure
US20090273055A1 (en) * 2004-06-29 2009-11-05 Kong-Beng Thei Fuse Structure
US9099467B2 (en) 2004-06-29 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. E-fuse structure design in electrical programmable redundancy for embedded memory circuit
US8629050B2 (en) 2004-06-29 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. E-fuse structure design in electrical programmable redundancy for embedded memory circuit
US20060163734A1 (en) * 2005-01-24 2006-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fuse structure and method for making the same
US8030733B1 (en) * 2007-05-22 2011-10-04 National Semiconductor Corporation Copper-compatible fuse target
US7964934B1 (en) 2007-05-22 2011-06-21 National Semiconductor Corporation Fuse target and method of forming the fuse target in a copper process flow
US20120261793A1 (en) * 2011-04-13 2012-10-18 International Business Machines Corporation Electrical fuse and method of making the same
CN103688349A (en) * 2011-04-13 2014-03-26 国际商业机器公司 Electrical fuse and method of making the same
US8952486B2 (en) * 2011-04-13 2015-02-10 International Business Machines Corporation Electrical fuse and method of making the same
GB2504418B (en) * 2011-04-13 2015-03-11 Ibm Electrical fuse and method of making the same
WO2013095692A3 (en) * 2011-04-13 2013-10-24 International Business Machines Corporation Electrical fuse and method of making the same
CN103688349B (en) * 2011-04-13 2016-08-24 国际商业机器公司 Electric fuse and manufacture method thereof
GB2504418A (en) * 2011-04-13 2014-01-29 Ibm Electrical fuse and method of making the same
US9245846B2 (en) * 2014-05-06 2016-01-26 International Business Machines Corporation Chip with programmable shelf life
US9337148B2 (en) 2014-05-06 2016-05-10 International Business Machines Corporation Chip with programmable shelf life
US10170425B2 (en) * 2014-11-12 2019-01-01 International Business Machines Corporation Microstructure of metal interconnect layer
US20170194240A1 (en) * 2016-01-05 2017-07-06 Samsung Electronics Co., Ltd. Package substrate, method for fabricating the same, and package device including the package substrate
US10134666B2 (en) * 2016-01-05 2018-11-20 Samsung Electronics Co., Ltd. Package substrate, method for fabricating the same, and package device including the package substrate
US9960107B2 (en) * 2016-01-05 2018-05-01 Samsung Electronics Co., Ltd. Package substrate, method for fabricating the same, and package device including the package substrate
US10615119B2 (en) * 2017-12-12 2020-04-07 International Business Machines Corporation Back end of line electrical fuse structure and method of fabrication
US20200161239A1 (en) * 2017-12-12 2020-05-21 International Business Machines Corporation Back end of line electrical fuse structure and method of fabrication
US10916501B2 (en) * 2017-12-12 2021-02-09 International Business Machines Corporation Back end of line electrical fuse structure and method of fabrication
US10991655B2 (en) * 2018-08-24 2021-04-27 Shenzhen Weitongbo Technology Co., Ltd. E-fuse and manufacturing method thereof, and memory cell
WO2022182382A1 (en) * 2021-02-24 2022-09-01 Microchip Technology Incorporated Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals
US11600566B2 (en) 2021-02-24 2023-03-07 Microchip Technology Incorporated Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals

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