US20010042897A1 - Copper fuse for integrated circuit - Google Patents
Copper fuse for integrated circuit Download PDFInfo
- Publication number
- US20010042897A1 US20010042897A1 US09/495,625 US49562500A US2001042897A1 US 20010042897 A1 US20010042897 A1 US 20010042897A1 US 49562500 A US49562500 A US 49562500A US 2001042897 A1 US2001042897 A1 US 2001042897A1
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- United States
- Prior art keywords
- copper
- pads
- copper pads
- fuse
- metal
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- H10W20/493—
Definitions
- the present invention relates to a semiconductor structure in integrated circuit (IC). More particularly, the present invention relates to a copper fuse of semiconductor structure for IC.
- the invention provides a structure of a copper fuse in an IC, by which structure RC delay is reduced.
- the invention provides a structure of a copper fuse for an IC, which fuse includes two copper pads formed on a semiconductor substrate where the copper pads are isolated from each other with dielectrics.
- a metal line formed over the semiconductor substrate covers the two metal pads wherein one end of the metal line is connected to one of the two copper pads and the other end of the metal line is connected to the other of the two copper pads.
- a passivation layer formed over the semiconductor substrate covers the two copper pads.
- FIG. 1 is a schematic, cross-sectional view illustrating a structure of a copper fuse according to one preferred embodiment of this invention.
- FIG. 2 is a schematic, top view of FIG. 1, where the cross-sectional view along the line I-I is shown in FIG. 1.
- a tungsten plug is subsequently formed in the device region 100 a of an IC structure.
- Such metallization processes as wiring line and vias are carried out by damascene, for example, where the wiring lines and the vias are isolated from with dielectrics 102 .
- a passivation layer 104 a is deposited and then patterned by photolithography to form a pad window such that a metal pad 106 a made of copper, for example, is exposed.
- a barrier layer 108 a such as TiN or TaN is formed on the metal pad layer 106 a .
- An aluminum layer 110 a is formed and patterned to complete the wire bonding process of the device region 100 a for the back-end process of the IC.
- a copper fuse set up in the peripheral region 100 b is first to form two metal copper pads 106 b in the dielectrics 102 .
- the two copper pads 106 b connected to corresponding devices (not shown) are formed by damascene, for example, when the metal pad 106 a is formed.
- the passivation layer 104 b is formed when the passivation layer 104 a is formed in order to cover the two copper pads 106 b .
- the passivation layer 106 b can be silicon oxide/silicon nitride, for example.
- a barrier layer 108 b such as TiN or TaN formed by sputtering is then formed on the copper pads 106 b .
- a metal layer 110 b is formed by sputtering to cover the copper pads 106 b to electrically connect the two copper pads 106 b .
- the barrier layer 108 b is used to improve the adhesion of the copper pads 106 b and the metal layer 110 b , and the metal layer 110 b can be aluminum, for example.
- the metal layer 110 b and the barrier layer 108 are patterned to form parallel fuses, as shown in FIG. 2.
- One end of the metal layer 110 b is connected to one copper pad 106 b and the other end of the metal layer 1106 b is connected to the other copper pad 106 b.
- the two copper pads 106 b and the metal line 110 b constitute the copper fuse structure of the preferred embodiment in the invention.
- the copper pads 106 b are electrically insulated and electrically connected by the metal layer 110 b . Therefore, when any one of the fuses in FIG. 2 must be disconnected, the metal line 110 b can be blown off by laser power such that the copper pads 106 b can be prevented from being damaged.
- the copper pads 106 b in this embodiment is covered by the passivation layer 104 b and the metal layer 110 b so that the copper pads 106 b are isolated from the air.
- the copper pads 106 b are not exposed. Therefore, oxidation on the surface of the copper pads 104 b can be avoided.
- the copper pads are used as a portion of the fuses, thereby reducing RC delay.
- the process to form the copper fuses in this embodiment is compatible with the back-end process of the device region 100 a for IC structure. Thus, the manufacturing cost does not increase.
- the copper fuse structure utilizes an aluminum metal line to cover and electrically connect to the two copper pads.
- the copper pads serve as a part of the fuses to reduce RC delay, and in addition, the fuse is disconnected by blowing off the aluminum line.
- the aluminum line and the passivation layer covering the copper pads is capable of preventing the copper pads from being oxidized by air.
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- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A copper fuse structure for integrated circuit employs two copper pads formed over a semiconductor substrate. The two copper pads are electrically insulated by dielectrics. An aluminum line is utilized to cover and electrically connect the two copper pads.
Description
- 1. Field of Invention
- The present invention relates to a semiconductor structure in integrated circuit (IC). More particularly, the present invention relates to a copper fuse of semiconductor structure for IC.
- 2. Description of Related Art
- As the design rule of the semiconductor process approaches or is less than 0.18 μm, copper gradually replaces aluminum as an interconnect in the metallization process since copper has lower resistance that can reduce RC delay. However, copper easily reacts with the oxygen in the surroundings to form a thin copper oxide on its surface, which leads to the failure of electrical contact. As a result, it is difficult to substitute copper for aluminum when forming a fuse in an IC as, in the IC industry, at the current line width.
- The invention provides a structure of a copper fuse in an IC, by which structure RC delay is reduced.
- As embodied and broadly described herein, the invention provides a structure of a copper fuse for an IC, which fuse includes two copper pads formed on a semiconductor substrate where the copper pads are isolated from each other with dielectrics. A metal line formed over the semiconductor substrate covers the two metal pads wherein one end of the metal line is connected to one of the two copper pads and the other end of the metal line is connected to the other of the two copper pads. A passivation layer formed over the semiconductor substrate covers the two copper pads.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
- FIG. 1 is a schematic, cross-sectional view illustrating a structure of a copper fuse according to one preferred embodiment of this invention; and
- FIG. 2 is a schematic, top view of FIG. 1, where the cross-sectional view along the line I-I is shown in FIG. 1.
- Referring to FIG. 1, after the formation of a MOS device and contact (not shown), a tungsten plug is subsequently formed in the
device region 100 a of an IC structure. Such metallization processes as wiring line and vias are carried out by damascene, for example, where the wiring lines and the vias are isolated from withdielectrics 102. Thereafter, apassivation layer 104 a is deposited and then patterned by photolithography to form a pad window such that ametal pad 106 a made of copper, for example, is exposed. Abarrier layer 108 a such as TiN or TaN is formed on themetal pad layer 106 a. Analuminum layer 110 a is formed and patterned to complete the wire bonding process of thedevice region 100 a for the back-end process of the IC. - Referring to FIG. 1 and FIG. 2 simultaneously, a copper fuse set up in the
peripheral region 100 b is first to form twometal copper pads 106 b in thedielectrics 102. The twocopper pads 106 b connected to corresponding devices (not shown) are formed by damascene, for example, when themetal pad 106 a is formed. Thereafter, thepassivation layer 104 b is formed when thepassivation layer 104 a is formed in order to cover the twocopper pads 106 b. Thepassivation layer 106 b can be silicon oxide/silicon nitride, for example. As thepassivation layer 104 a in thedevice region 100 a is patterned, photolithography is also employed to form anopening 112 in thepassivation layer 104 b so that the two copper pads are exposed. Abarrier layer 108 b such as TiN or TaN formed by sputtering is then formed on thecopper pads 106 b. Ametal layer 110 b is formed by sputtering to cover thecopper pads 106 b to electrically connect the twocopper pads 106 b. Thebarrier layer 108 b is used to improve the adhesion of thecopper pads 106 b and themetal layer 110 b, and themetal layer 110 b can be aluminum, for example. Thereafter, themetal layer 110 b and the barrier layer 108 are patterned to form parallel fuses, as shown in FIG. 2. One end of themetal layer 110 b is connected to onecopper pad 106 b and the other end of the metal layer 1106 b is connected to theother copper pad 106 b. - The two
copper pads 106 b and themetal line 110 b constitute the copper fuse structure of the preferred embodiment in the invention. Thecopper pads 106 b are electrically insulated and electrically connected by themetal layer 110 b. Therefore, when any one of the fuses in FIG. 2 must be disconnected, themetal line 110 b can be blown off by laser power such that thecopper pads 106 b can be prevented from being damaged. - The
copper pads 106 b in this embodiment is covered by thepassivation layer 104 b and themetal layer 110 b so that thecopper pads 106 b are isolated from the air. When the back end process is complete, thecopper pads 106 b are not exposed. Therefore, oxidation on the surface of thecopper pads 104 b can be avoided. In addition, the copper pads are used as a portion of the fuses, thereby reducing RC delay. - Moreover, the process to form the copper fuses in this embodiment is compatible with the back-end process of the
device region 100 a for IC structure. Thus, the manufacturing cost does not increase. - The copper fuse structure utilizes an aluminum metal line to cover and electrically connect to the two copper pads. The copper pads serve as a part of the fuses to reduce RC delay, and in addition, the fuse is disconnected by blowing off the aluminum line. Moreover, the aluminum line and the passivation layer covering the copper pads is capable of preventing the copper pads from being oxidized by air.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (9)
1. A copper fuse for an integrated circuit, comprising:
at least two copper pads, located on a semiconductor substrate; and
a metal line, one end being electrically connected to one of the two copper pads and the other end being electrically connected to the other of the two copped pads; wherein at least the two copper pads and the metal line are used as a fuse.
2. The copper fuse according to , wherein the metal layer includes aluminum.
claim 1
3. The copper fuse according to , wherein a barrier layer is located between the metal line and the two copper pads.
claim 1
4. The copper fuse according to , wherein the barrier layer includes TaN.
claim 3
5. The copper fuse according to , further including a passivation layer covering the two copper pads.
claim 1
6. A copper fuse for integrated circuit, comprising:
two copper pads, formed on a semiconductor substrate, the two copper pads insulated with a dielectrics;
a metal line having a first end and a second end, formed on the semiconductor substrate, covering the two copper pads wherein the first end is connected to one of the two copper pads and the second end is connected to the other of the two copped pads; and
a passivation layer, formed on the semiconductor substrate and covering the two copper pads
wherein the two copper pads and the metal line are used as a fuse.
7. The copper fuse according to , wherein the metal layer includes aluminum.
claim 6
8. The copper fuse according to , wherein a barrier layer is located between the metal line and the two copper pads.
claim 6
9. The copper fuse according to , wherein the barrier layer includes TaN.
claim 8
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/495,625 US6455913B2 (en) | 2000-01-31 | 2000-01-31 | Copper fuse for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/495,625 US6455913B2 (en) | 2000-01-31 | 2000-01-31 | Copper fuse for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20010042897A1 true US20010042897A1 (en) | 2001-11-22 |
| US6455913B2 US6455913B2 (en) | 2002-09-24 |
Family
ID=23969346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/495,625 Expired - Lifetime US6455913B2 (en) | 2000-01-31 | 2000-01-31 | Copper fuse for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | US6455913B2 (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566171B1 (en) * | 2001-06-12 | 2003-05-20 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
| WO2003085735A1 (en) * | 2002-04-02 | 2003-10-16 | Infineon Technologies Ag | Beol process for cu metallizations free from al-wirebond pads |
| US6693343B2 (en) * | 2000-12-28 | 2004-02-17 | Infineon Technologies Ag | Self-passivating Cu laser fuse |
| US6730982B2 (en) | 2001-03-30 | 2004-05-04 | Infineon Technologies Ag | FBEOL process for Cu metallizations free from Al-wirebond pads |
| US20040219720A1 (en) * | 2002-09-17 | 2004-11-04 | Jeng Shin-Puu | Metal fuse for semiconductor devices |
| US20040224444A1 (en) * | 2003-01-09 | 2004-11-11 | Katsuhiro Hisaka | Fuse layout and method of trimming |
| US20050212081A1 (en) * | 2004-03-25 | 2005-09-29 | Hyuck-Jin Kang | Fuse region of a semiconductor device and method of fabricating the same |
| US20060163734A1 (en) * | 2005-01-24 | 2006-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fuse structure and method for making the same |
| US20090273055A1 (en) * | 2004-06-29 | 2009-11-05 | Kong-Beng Thei | Fuse Structure |
| US7964934B1 (en) | 2007-05-22 | 2011-06-21 | National Semiconductor Corporation | Fuse target and method of forming the fuse target in a copper process flow |
| US8030733B1 (en) * | 2007-05-22 | 2011-10-04 | National Semiconductor Corporation | Copper-compatible fuse target |
| US20120261793A1 (en) * | 2011-04-13 | 2012-10-18 | International Business Machines Corporation | Electrical fuse and method of making the same |
| US9245846B2 (en) * | 2014-05-06 | 2016-01-26 | International Business Machines Corporation | Chip with programmable shelf life |
| US20170194240A1 (en) * | 2016-01-05 | 2017-07-06 | Samsung Electronics Co., Ltd. | Package substrate, method for fabricating the same, and package device including the package substrate |
| US10170425B2 (en) * | 2014-11-12 | 2019-01-01 | International Business Machines Corporation | Microstructure of metal interconnect layer |
| US10615119B2 (en) * | 2017-12-12 | 2020-04-07 | International Business Machines Corporation | Back end of line electrical fuse structure and method of fabrication |
| US10991655B2 (en) * | 2018-08-24 | 2021-04-27 | Shenzhen Weitongbo Technology Co., Ltd. | E-fuse and manufacturing method thereof, and memory cell |
| WO2022182382A1 (en) * | 2021-02-24 | 2022-09-01 | Microchip Technology Incorporated | Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals |
| US11600566B2 (en) | 2021-02-24 | 2023-03-07 | Microchip Technology Incorporated | Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7328830B2 (en) * | 2002-12-20 | 2008-02-12 | Agere Systems Inc. | Structure and method for bonding to copper interconnect structures |
| KR100735529B1 (en) * | 2006-02-09 | 2007-07-04 | 삼성전자주식회사 | Semiconductor memory device and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5741720A (en) * | 1995-10-04 | 1998-04-21 | Actel Corporation | Method of programming an improved metal-to-metal via-type antifuse |
| US5731624A (en) * | 1996-06-28 | 1998-03-24 | International Business Machines Corporation | Integrated pad and fuse structure for planar copper metallurgy |
| US6175145B1 (en) * | 1997-07-26 | 2001-01-16 | Samsung Electronics Co., Ltd. | Method of making a fuse in a semiconductor device and a semiconductor device having a fuse |
| US6144096A (en) * | 1998-10-05 | 2000-11-07 | Advanced Micro Devices, Inc. | Low resistivity semiconductor barrier layers and manufacturing method therefor |
-
2000
- 2000-01-31 US US09/495,625 patent/US6455913B2/en not_active Expired - Lifetime
Cited By (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6844245B2 (en) | 2000-12-28 | 2005-01-18 | Infineon Technologies Ag | Method of preparing a self-passivating Cu laser fuse |
| US6693343B2 (en) * | 2000-12-28 | 2004-02-17 | Infineon Technologies Ag | Self-passivating Cu laser fuse |
| US20040135230A1 (en) * | 2000-12-28 | 2004-07-15 | Hans-Joachim Barth | Self-passivating Cu laser fuse |
| US6730982B2 (en) | 2001-03-30 | 2004-05-04 | Infineon Technologies Ag | FBEOL process for Cu metallizations free from Al-wirebond pads |
| US6806551B2 (en) | 2001-06-12 | 2004-10-19 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
| US6566171B1 (en) * | 2001-06-12 | 2003-05-20 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
| WO2003085735A1 (en) * | 2002-04-02 | 2003-10-16 | Infineon Technologies Ag | Beol process for cu metallizations free from al-wirebond pads |
| US20040219720A1 (en) * | 2002-09-17 | 2004-11-04 | Jeng Shin-Puu | Metal fuse for semiconductor devices |
| US7205588B2 (en) * | 2002-09-17 | 2007-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal fuse for semiconductor devices |
| US7119414B2 (en) * | 2003-01-09 | 2006-10-10 | Oki Electric Industry Co., Ltd. | Fuse layout and method trimming |
| US20040224444A1 (en) * | 2003-01-09 | 2004-11-11 | Katsuhiro Hisaka | Fuse layout and method of trimming |
| US20050212081A1 (en) * | 2004-03-25 | 2005-09-29 | Hyuck-Jin Kang | Fuse region of a semiconductor device and method of fabricating the same |
| US7352050B2 (en) * | 2004-03-25 | 2008-04-01 | Samsung Electronics Co., Ltd. | Fuse region of a semiconductor region |
| US8174091B2 (en) | 2004-06-29 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fuse structure |
| US20090273055A1 (en) * | 2004-06-29 | 2009-11-05 | Kong-Beng Thei | Fuse Structure |
| US9099467B2 (en) | 2004-06-29 | 2015-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | E-fuse structure design in electrical programmable redundancy for embedded memory circuit |
| US8629050B2 (en) | 2004-06-29 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | E-fuse structure design in electrical programmable redundancy for embedded memory circuit |
| US20060163734A1 (en) * | 2005-01-24 | 2006-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fuse structure and method for making the same |
| US8030733B1 (en) * | 2007-05-22 | 2011-10-04 | National Semiconductor Corporation | Copper-compatible fuse target |
| US7964934B1 (en) | 2007-05-22 | 2011-06-21 | National Semiconductor Corporation | Fuse target and method of forming the fuse target in a copper process flow |
| US20120261793A1 (en) * | 2011-04-13 | 2012-10-18 | International Business Machines Corporation | Electrical fuse and method of making the same |
| CN103688349A (en) * | 2011-04-13 | 2014-03-26 | 国际商业机器公司 | Electrical fuse and method of making the same |
| US8952486B2 (en) * | 2011-04-13 | 2015-02-10 | International Business Machines Corporation | Electrical fuse and method of making the same |
| GB2504418B (en) * | 2011-04-13 | 2015-03-11 | Ibm | Electrical fuse and method of making the same |
| WO2013095692A3 (en) * | 2011-04-13 | 2013-10-24 | International Business Machines Corporation | Electrical fuse and method of making the same |
| CN103688349B (en) * | 2011-04-13 | 2016-08-24 | 国际商业机器公司 | Electric fuse and manufacture method thereof |
| GB2504418A (en) * | 2011-04-13 | 2014-01-29 | Ibm | Electrical fuse and method of making the same |
| US9245846B2 (en) * | 2014-05-06 | 2016-01-26 | International Business Machines Corporation | Chip with programmable shelf life |
| US9337148B2 (en) | 2014-05-06 | 2016-05-10 | International Business Machines Corporation | Chip with programmable shelf life |
| US10170425B2 (en) * | 2014-11-12 | 2019-01-01 | International Business Machines Corporation | Microstructure of metal interconnect layer |
| US20170194240A1 (en) * | 2016-01-05 | 2017-07-06 | Samsung Electronics Co., Ltd. | Package substrate, method for fabricating the same, and package device including the package substrate |
| US10134666B2 (en) * | 2016-01-05 | 2018-11-20 | Samsung Electronics Co., Ltd. | Package substrate, method for fabricating the same, and package device including the package substrate |
| US9960107B2 (en) * | 2016-01-05 | 2018-05-01 | Samsung Electronics Co., Ltd. | Package substrate, method for fabricating the same, and package device including the package substrate |
| US10615119B2 (en) * | 2017-12-12 | 2020-04-07 | International Business Machines Corporation | Back end of line electrical fuse structure and method of fabrication |
| US20200161239A1 (en) * | 2017-12-12 | 2020-05-21 | International Business Machines Corporation | Back end of line electrical fuse structure and method of fabrication |
| US10916501B2 (en) * | 2017-12-12 | 2021-02-09 | International Business Machines Corporation | Back end of line electrical fuse structure and method of fabrication |
| US10991655B2 (en) * | 2018-08-24 | 2021-04-27 | Shenzhen Weitongbo Technology Co., Ltd. | E-fuse and manufacturing method thereof, and memory cell |
| WO2022182382A1 (en) * | 2021-02-24 | 2022-09-01 | Microchip Technology Incorporated | Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals |
| US11600566B2 (en) | 2021-02-24 | 2023-03-07 | Microchip Technology Incorporated | Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals |
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| US6455913B2 (en) | 2002-09-24 |
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