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US12148676B2 - Embedded chip package and manufacturing method thereof - Google Patents

Embedded chip package and manufacturing method thereof Download PDF

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Publication number
US12148676B2
US12148676B2 US18/389,264 US202318389264A US12148676B2 US 12148676 B2 US12148676 B2 US 12148676B2 US 202318389264 A US202318389264 A US 202318389264A US 12148676 B2 US12148676 B2 US 12148676B2
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Prior art keywords
chip
frame
post
photosensitive polymer
polymer dielectric
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US20240087972A1 (en
Inventor
Xianming Chen
Jindong FENG
Benxia Huang
Lei Feng
Wenshi Wang
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Zhuhai Access Semiconductor Co Ltd
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Zhuhai Access Semiconductor Co Ltd
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Assigned to ZHUHAI ACCESS SEMICONDUCTOR CO., LTD. reassignment ZHUHAI ACCESS SEMICONDUCTOR CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, XIANMING, HUANG, BENXIA, FENG, Jindong, FENG, LEI, WANG, WENSHI
Publication of US20240087972A1 publication Critical patent/US20240087972A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
    • H—ELECTRICITY
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables

Definitions

  • the present invention relates to chip package, and specifically to an embedded chip package and a manufacturing method thereof.
  • passive devices such as resistor, capacitor, inductor
  • active devices such as IC
  • This method can shorten the line length between elements and improve electrical characteristics, and also can improve effective PCB packaging area and reduce many solder bumps on the PCB surface, thus improving packaging reliability and lowering cost, and thus is a perfect high-density packaging technology.
  • the packaging material is the thermosetting polymer (such as prepreg (PP) or epoxy resin type polymer such as Ajinomoto buildup film (ABF)) or the thermoplastic polymer (such as polyethylene (PE)).
  • PP prepreg
  • ABSF Ajinomoto buildup film
  • PE polyethylene
  • thermosetting dielectric cured under certain temperature and pressure conditions
  • a method of laser drilling is used to expose the conduction post(s) (terminal) of the chip or device.
  • a method of electroplating and hole-filling is used to fill the laser hole(s) with Cu, thus achieving electrical connection.
  • this method is not suitable for embedding of a die and a device without a conduction post having a high aspect ratio because the conductive metal pad on the outer layer of the die has a thickness of only 2 ⁇ 5 ⁇ m and the conduction terminal of the device without a conduction post has a thickness of only 6 ⁇ 15 ⁇ m, and the energy produced by laser radiation is too high to the metal pad or terminal having such thickness, enough to damage the whole chip structure or break down the conduction terminal of the device.
  • a Chinese application publication CN106997870A discloses an embedded structure with both sides conducted. Also, the thermosetting dielectric is used as the packaging material to fix the chip, and then a method of plasma dry etching is used to open the chip back face to achieve connection of both sides.
  • a method of plasma dry etching is used to open the chip back face to achieve connection of both sides.
  • the etching time is long and the efficiency is low.
  • the thickness of the packaging material is 15 ⁇ m ⁇ 50 ⁇ m, and in the case of forming a large opening for heat dissipation, it is necessary for the dry etching to take the etching time of 50 min ⁇ 150 min, low in operation efficiency.
  • a small via such as a via with its diameter lower than 200 ⁇ m
  • the gas of the dry etching has a lower exchange rate in the small via
  • the etching rate is further decreased and the via bottom has a poor quality (diameter, roundness, etc.), difficult to achieve excellent heat/electric conduction performance.
  • the laser energy is prone to produce a stress in the chip or device and may cause damage of the chip or device. Therefore, it is not suitable for embedding of a die/a device without a conduction post.
  • the panel frame is generally made of glass fiber composite material (such as BT), and thus there is a problem of exposure of glass fiber after grinding, which would lead to weakened capability of fine circuits.
  • Cu on the glass fiber has a poor bonding force and is prone to be peeled; and the exposed glass fiber is prone to form an electromigration channel, leading to failure in electrical properties and reduction in life.
  • One of the objectives of the present invention is to provide an embedded chip package using a photosensitive polymer dielectric material as the packaging material as well as the manufacturing method thereof, so as to overcome the technical defect(s) in the prior art.
  • the first aspect relates to an embedded chip package comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.
  • the photosensitive polymer dielectric material is selected from a group comprising polyimide photosensitive resin and polyphenylene oxide photosensitive resin.
  • the frame further comprises at least one frame via-post which extends through the height of the frame from a first frame face to a second frame face of the frame.
  • the terminal face of the chip comprises a metal terminal pad which is conductively connected to the first wiring layer through a first via-post surrounded in the photosensitive polymer dielectric.
  • the back face of the chip is formed thereon with a second via-post surrounded by the photosensitive polymer dielectric.
  • the second via-post is conductively connected the back face of the chip and the second wiring layer.
  • the second wiring layer comprises a heat dissipation pad.
  • the back face of the chip is provided with a Si via connected to the terminal on the terminal face of the chip, or is provided with the chips stacked back to back such that the back face of the chip is provided with a terminal.
  • a third via-post and a fourth via-post are formed on the both ends of the frame via-post respectively from both sides of the frame, wherein the third via-post is conductively connected to the first wiring layer and the fourth via-post is conductively connected to the second wiring layer.
  • the chip is selected from at least one of integrated circuit, passive device and active device.
  • the chip comprises power device or chips stacked and combined back to back.
  • the frame via-post, the frame via-post, the first via-post, the second via-post, the third via-post and the fourth via-post comprises Cu.
  • the second aspect relates to a method for manufacturing an embedded chip package, comprising the following steps:
  • the photosensitive polymer dielectric material is selected from a group comprising polyimide photosensitive resin and polyphenylene oxide photosensitive resin.
  • the metal seed layer comprises Ti, W, or Ti/W alloys.
  • the first wiring layer is conductively connected through the first via-post to the terminal pad of the chip
  • the second wiring layer is conductively connected through the second via-post to the back face of the chip.
  • the frame via-post, the frame via-post, the first via-post, the second via-post, the third via-post and the fourth via-post comprises Cu.
  • the method further comprises: after the Cu electroplating, removing the photoresist layer and etching off the exposed metal seed layer.
  • the method further comprises: performing layer building-up and re-wiring on the first and/or second wiring layers to stack and construct an additional wiring layer.
  • the method further comprises: applying a solder mask onto the first wiring layer and/or the second wiring layer.
  • the method further comprises: cutting the chip socket array into individual package chips.
  • the photosensitive polymer dielectric as mentioned herein means a type of photosensitive resin material having relatively low dielectric constant and dielectric loss.
  • the photosensitive polymer dielectric commonly used now is a negative one which can excite a photoinitiator to cross-link and polymerize small-molecule unsaturated organic oligomers to form a stable solid organic polymer product, under the effect of light (such as UV light or visible light) or high energy rays (such as electron beam).
  • the photosensitive resin is used as a photoresist material such as that for photolithography.
  • this type of photosensitive polymer dielectric it is necessary for this type of photosensitive polymer dielectric to have some special properties, such as relatively high dielectric properties within a relatively broad temperature range and frequency range (for example, a dielectric constant of 2.5 ⁇ 3.4, a dielectric loss of 0.001 ⁇ 0.01, a dielectric strength of 100 KV ⁇ 400 KV), and to have a relatively excellent adhesion, a relatively low stress, etc.
  • the photosensitive polymer dielectric is used as the chip packaging material, thus enabling to simplify the steps of the manufacturing process, improve the production efficiency and lower the cost. For example, it is possible to simultaneously form a plurality of patterns and then simultaneously perform electroplating and filling. Moreover, it is possible to avoid a risk of damage to embedded chips due to traditional hole-opening methods, thus improving the yield rate. Furthermore, as it is not necessary in the present method to grind the panel or frame, there is no risk of exposing glass fibers, for example.
  • FIG. 1 is a schematic side view of a first embedded chip structure
  • FIG. 2 is a schematic side view of a second embedded chip structure
  • FIG. 3 is a schematic side view of a third embedded chip structure
  • FIGS. 4 A to 4 I schematically show intermediate structures obtained by steps of the method of the present invention.
  • the present invention relates to an embedded chip package, characterized in that a chip and a frame are embedded in a photosensitive polymer dielectric serving as a packaging material, an opening is formed directly on the back face of the chip with a metal post (such as Cu post) being deposited therein, while an opening is also formed on the terminal face of the chip by applying the photosensitive polymer dielectric to form a metal post for conducting a terminal of the chip, thereby forming a structure in which both sides of the chip can be used for conduction or heat dissipation.
  • a metal post such as Cu post
  • the photosensitive polymer dielectric used in the present invention is mainly selected from polyimide photosensitive resin and polyphenylene oxide photosensitive resin, such as Microsystems HD-4100, Hitachi PVF-02, etc.
  • the metal post formed on the chip terminal face is used for connecting the chip terminal with the first wiring layer.
  • the metal post formed on the chip back face is generally used as a heat dissipation pad or is connected to a heat dissipation device such that the heat can be dissipated more effectively.
  • the chip back face is also provided with a terminal (for example, the chip has a structure with a Si via passing through the chip, or there are a plurality of chips stacked in a back-to-back 3 D manner)
  • a Cu post formed on the chip back face also can provide a function of electric connection.
  • PoP package-on-package
  • the embedded chip package 100 comprises a chip 140 having a terminal face 141 and a back face 142 separated by a height of the chip.
  • the chip 140 is disposed in a cavity 130 surrounded by a frame 110 which has a first frame face 111 coplanar with the chip terminal face 141 and an opposite second frame face 112 .
  • the frame 110 has a thickness larger than the height of the chip 140 , generally by 15 ⁇ 50 ⁇ m, such that the second frame face 112 is higher than the back face 142 of the chip 140 .
  • a gap between the chip 140 and the frame 110 is filled with a photosensitive polymer dielectric packaging material 160 comprising a polyimide photosensitive resin or a polyphenylene oxide photosensitive resin.
  • the packaging material 160 not only covers the chip back face 142 and the second frame face 112 , but also can cover the chip terminal face 141 and the first frame face 111 .
  • the packaging material 160 it is possible to form a layer of via-post respectively on both surfaces of the chip package 100 so as to accordingly conduct a first wiring layer 131 with a second wiring layer 132 .
  • One or more conductive via-posts 120 may be conFIGured to pass through the thickness of the frame 110 . These via-posts 120 connect the first frame face 111 and the second frame face 112 .
  • the chip 140 may be a device having a Si via passing through the chip or may comprise a plurality of chips stacked back to back such that the back face 142 of the chip 140 is provided with a terminal which is electrically connectable.
  • the frame 110 has a first polymer matrix, and may comprise glass fiber and ceramic fillers.
  • the frame 110 is made from a prepreg of woven glass fibers impregnated with polymer.
  • FIG. 2 it shows an embedded chip package 200 with a heat dissipation pad formed on the chip back face.
  • the embedded chip package 200 is similar in structure to the chip package 100 of FIG. 1 , with a difference only in that a heat dissipation pad 250 is formed by filling a heat dissipation metal in a large opening formed on the chip back face 142 .
  • This type of chip package 200 is applicable to large power devices, especially chips required to enable electric conduction on a single face and heat dissipation on both faces.
  • the chip packages 100 and 200 of FIGS. 1 and 2 are not limited to the case required to enable electric conduction on both faces or the case required to enable electric conduction on a single face and heat dissipation on both faces, and they are also applicable to the case required to enable electric conduction on a single face (the terminal face) of the chip, without any opening on the back face.
  • the chip terminal face 141 may be covered with a photosensitive polymer dielectric 161 to lead out a metal terminal, or a wiring layer can be formed directly on the chip terminal face 141 flushing with the surface 111 of the frame 110 , 210 , without a layer of the photosensitive polymer dielectric 161 .
  • FIG. 3 shows that on both sides of the chip package 100 of FIG. 1 , additional wiring layers 351 , 352 are further formed to build up a multi-layer interconnection structure 300 . Also, on the chip package 200 of FIG. 2 , it is possible to further build up an additional layer to form package-on-package (PoP) as well as a similar interconnection structure.
  • PoP package-on-package
  • the layer building up processing may be performed simultaneously on both sides of the frame. It is also to be understood that as the seed layers may be sputtered on both sides of the frame and the chip, additional wiring layers and conduction structures may be constructed on both sides. Once the wiring layer having a conductor feature structure is formed on the packaged one side or both sides, it is possible to attach another chip onto the conductor feature structure by means of technologies of Ball Grid Array (BGA) or Land Grid Array (LGA), etc.
  • BGA Ball Grid Array
  • LGA Land Grid Array
  • the packaging technologies described herein may be used to package chips having circuits on both sides.
  • the wafer can be processed on both sides, for example, with a processor chip on one side and a memory chip on the other side.
  • the packaging technologies described herein are not limited to IC chip packaging.
  • the chips comprise passive devices selected from fuse, capacitor, inductor and filter.
  • FIGS. 4 A to 4 I a method for manufacturing the embedded chip package structure of FIG. 1 is shown. However, it is to be understood that the method may be applicable to manufacture other similar structures, such as those shown in FIGS. 2 and 3 .
  • the method comprises the step of obtaining a chip socket array comprising a first polymer frame 110 (referring to FIG. 4 A ), wherein each through socket 130 is defined by the frame 110 , and optionally at least one frame via-post 120 passing through the frame 110 is included.
  • a chip socket array comprising a first polymer frame 110 (referring to FIG. 4 A ), wherein each through socket 130 is defined by the frame 110 , and optionally at least one frame via-post 120 passing through the frame 110 is included.
  • an organic frame 110 according to the US patent publication US20160165731A1 wherein the frame 110 has upper and lower surfaces 112 , 111 and a cavity or socket 130 in an array arrangement generated based on the chip size.
  • the frame 110 has a thickness which is larger than and is close to the chip thickness, generally larger than the chip thickness by 15 ⁇ 50 ⁇ m.
  • the frame 110 is placed on an adhesive tape 150 .
  • the chip 140 facing downwards (i.e. its terminal face facing downwards), is placed into a cavity 130 of the frame 110 such that the chip terminal face 141 is in contact with the adhesive tape 150 (referring to FIG. 4 B ).
  • the adhesive tape 150 is generally a commercially available transparent film which can be decomposed by heating or exposure to UV light. It is possible to perform imaging through the adhesive tape to achieve alignment or exposure, thus facilitating curing of the photosensitive polymer dielectric.
  • a photosensitive polymer dielectric 160 (such as a polyimide photosensitive resin or a polyphenylene oxide photosensitive resin) serving as the packaging material is laminated or coated such that the photosensitive polymer dielectric 160 fully fills the gap between the chip 140 and the frame 110 and covers the back face 142 of the chip, an upper surface 112 of the frame and an upper surface 122 of the Cu post 120 (referring to FIG. 4 C ).
  • the photosensitive polymer dielectric 160 on the side of the chip back face is exposed by an exposure machine and is developed to form a first pattern.
  • the photosensitive polymer dielectric in hole positions in the first pattern is not cured and thus is removed. Therefore, the first pattern comprises a first blind via 171 exposing the upper surface 122 of the frame via-post 120 on the frame 110 and a second blind via 172 exposing the back face 142 of the chip 140 (referring to FIG. 4 C ).
  • the adhesive tape 150 is removed, and the photosensitive polymer dielectric 161 is laminated or coated onto the terminal face 141 of the chip 140 and the lower surface 111 of the frame.
  • the photosensitive polymer dielectric 161 is exposed and developed to form a second pattern.
  • the second pattern comprises a third blind via 173 exposing a metal terminal pad on the terminal face 141 of the chip 140 and a fourth blind via 174 exposing a lower end face 121 of the frame via-post 120 on the frame lower surface 111 (referring to FIG. 4 D ).
  • the adhesive tape 150 may be burned out or removed by exposure to UV light.
  • the photosensitive polymer dielectrics 160 and 161 may be the same or different photosensitive polymer dielectrics, and may be different only in thickness.
  • a chemical plating or sputtering method is used to form metal seed layers 180 on the surfaces of the photosensitive polymer dielectrics 160 , 161 and in the blind vias 171 , 172 , 173 , 174 (referring to FIG. 4 E ).
  • the metal commonly used for the seed layer is selected from Ti, Cu, or Ti-Wu alloys, but is not limited to the above metals.
  • Photoresist layers 190 are applied onto the metal seed layers 180 on both sides of the package 100 , and a third pattern comprising a first wiring layer and a second wiring layer is formed directly by means of exposure and development.
  • the third pattern of the photoresist layer 190 formed by exposure and development exposes the metal seed layers 180 in positions where it is necessary to form the first and second wiring layers (referring to FIG. 4 F ).
  • An electroplating method is used to plate and fill Cu into the first, second and third patterns such that all the opened blind vias and openings on the wiring layers are filled with Cu simultaneously to form first, second, third and fourth via-posts 120 a , 120 b , 120 c , 120 d as well as the first and second wiring layers 131 , 132 (referring to FIG. 4 G ).
  • a dry-film remover agent is used to remove the photoresist layer 190 , and then an etching method is used to remove the exposed metal seed layers 180 (referring to FIG. 4 H ).
  • the layer building up and re-wiring processes can be performed for several times on the upper and lower surfaces of the substrate, without any surface treatment, to stack and construct an additional wiring layer.
  • the dielectric for the layer building up may be the photosensitive polymer dielectric or the traditional packaging material, such as a thermosetting dielectric or a thermoplastic dielectric.
  • the method for the layer building up to form an additional wiring layer may be a common method, such as dry etching, etc.
  • the finished embedded chip package may be applied with a solder mask 195 on one side or both sides of the outer layer by coating or laminating.
  • the solder resist comprises AUS308 or AUS410, etc., but is not limited to the above materials.
  • a specific solder mask window 196 may be formed by photoresist exposure and development (referring to FIG. 4 I ).
  • the panel array can be cut and divided into individual chip packages.
  • the dividing or cutting may be achieved by using a rotating saw blade or other cutting technologies, such as using a laser.

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Abstract

Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.

Description

PRIORITY
The present application is a divisional application of U.S. patent application Ser. No. 17/044,087, filed on Sep. 30, 2020, which is a National Stage entry from International Application No. PCT/CN2020/089735, filed May 12, 2020, which claims priority to the benefit of Chinese Patent Application No. 202010255623.9 filed on Apr. 2, 2020, in the Chinese Intellectual Property Office, the entire contents of which are incorporated herein by reference.
BACKGROUND 1. Field of the Invention
The present invention relates to chip package, and specifically to an embedded chip package and a manufacturing method thereof.
2. Description of the Related Art
With the vigorous development of the electronics industry, it is time for the electronic products to have multiple functions, miniaturized appearance and high performance. The increasing requirements on high density, multifunction and miniaturization bring new challenges to packages and substrates. Many new packaging technologies are developed accordingly, comprising the embedded package technology.
With the embedded package technology, passive devices (such as resistor, capacitor, inductor) or even active devices (such as IC) are embedded into the inside of the packaged substrate. This method can shorten the line length between elements and improve electrical characteristics, and also can improve effective PCB packaging area and reduce many solder bumps on the PCB surface, thus improving packaging reliability and lowering cost, and thus is a perfect high-density packaging technology.
However, either for the wafer scale embedding technology or for the panel scale embedding technology, the packaging material is the thermosetting polymer (such as prepreg (PP) or epoxy resin type polymer such as Ajinomoto buildup film (ABF)) or the thermoplastic polymer (such as polyethylene (PE)). In order to achieve heat dissipation on both sides of the chip, it is necessary to expose an opening on the packaging material to form a via-post, a terminal or a heat dissipation pad. Commonly used methods comprise laser drilling and mask dry etching on the packaging material. However, these methods have obvious technical defects.
In the US patent publication US20190124772A1, it is disclosed that the thermosetting dielectric (cured under certain temperature and pressure conditions) is used as the packaging material. Then, a method of laser drilling is used to expose the conduction post(s) (terminal) of the chip or device. Finally, a method of electroplating and hole-filling is used to fill the laser hole(s) with Cu, thus achieving electrical connection. However, this method is not suitable for embedding of a die and a device without a conduction post having a high aspect ratio because the conductive metal pad on the outer layer of the die has a thickness of only 2˜5 μm and the conduction terminal of the device without a conduction post has a thickness of only 6˜15 μm, and the energy produced by laser radiation is too high to the metal pad or terminal having such thickness, enough to damage the whole chip structure or break down the conduction terminal of the device.
A Chinese application publication CN106997870A discloses an embedded structure with both sides conducted. Also, the thermosetting dielectric is used as the packaging material to fix the chip, and then a method of plasma dry etching is used to open the chip back face to achieve connection of both sides. When using this method to form a large opening (such as an opening of millimeter or centimeter scale), especially in the case of large thickness of packaging material, the etching time is long and the efficiency is low. For example, in the application, the thickness of the packaging material is 15 μm˜50 μm, and in the case of forming a large opening for heat dissipation, it is necessary for the dry etching to take the etching time of 50 min˜150 min, low in operation efficiency. In the case of forming a small via (such as a via with its diameter lower than 200 μm), as the gas of the dry etching has a lower exchange rate in the small via, the etching rate is further decreased and the via bottom has a poor quality (diameter, roundness, etc.), difficult to achieve excellent heat/electric conduction performance.
Therefore, there are disadvantages in the prior art as below:
In the case of using laser drilling to form an opening on the common packaging material, the laser energy is prone to produce a stress in the chip or device and may cause damage of the chip or device. Therefore, it is not suitable for embedding of a die/a device without a conduction post.
In the case of using dry etching to form an opening on the common packaging material, it is difficult to achieve a small opening. Besides, even for a large opening, there are disadvantages of long work flow, low manufacturing output, limitation on product design, poor uniformity, short life, etc. In addition, for the dry etching, it is generally necessary to grind the packaging material to make it thinner. However, the panel frame is generally made of glass fiber composite material (such as BT), and thus there is a problem of exposure of glass fiber after grinding, which would lead to weakened capability of fine circuits. For example, Cu on the glass fiber has a poor bonding force and is prone to be peeled; and the exposed glass fiber is prone to form an electromigration channel, leading to failure in electrical properties and reduction in life.
SUMMARY
One of the objectives of the present invention is to provide an embedded chip package using a photosensitive polymer dielectric material as the packaging material as well as the manufacturing method thereof, so as to overcome the technical defect(s) in the prior art.
The first aspect relates to an embedded chip package comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.
Preferably, the photosensitive polymer dielectric material is selected from a group comprising polyimide photosensitive resin and polyphenylene oxide photosensitive resin.
In some embodiments, the frame further comprises at least one frame via-post which extends through the height of the frame from a first frame face to a second frame face of the frame.
In some embodiments, the terminal face of the chip comprises a metal terminal pad which is conductively connected to the first wiring layer through a first via-post surrounded in the photosensitive polymer dielectric.
In some embodiments, the back face of the chip is formed thereon with a second via-post surrounded by the photosensitive polymer dielectric.
Preferably, the second via-post is conductively connected the back face of the chip and the second wiring layer. Preferably, the second wiring layer comprises a heat dissipation pad.
In some embodiments, the back face of the chip is provided with a Si via connected to the terminal on the terminal face of the chip, or is provided with the chips stacked back to back such that the back face of the chip is provided with a terminal.
In some embodiments, a third via-post and a fourth via-post are formed on the both ends of the frame via-post respectively from both sides of the frame, wherein the third via-post is conductively connected to the first wiring layer and the fourth via-post is conductively connected to the second wiring layer.
Generally, the chip is selected from at least one of integrated circuit, passive device and active device. Preferably, the chip comprises power device or chips stacked and combined back to back.
Preferably, the frame via-post, the frame via-post, the first via-post, the second via-post, the third via-post and the fourth via-post comprises Cu.
The second aspect relates to a method for manufacturing an embedded chip package, comprising the following steps:
    • obtaining a chip socket array comprising a frame, wherein the frame is formed therein with a frame via-post passing through a height of the frame;
    • placing the chip socket array onto an adhesive tape;
    • placing a chip, with its terminal face facing downwards, into a cavity of the chip socket array surrounded by the frame;
    • laminating or coating a first photosensitive polymer dielectric onto the chip and the frame such that the photosensitive polymer dielectric fully fills a gap between the chip and the frame and covers the back face of the chip and an upper surface of the frame;
    • exposing and developing the first photosensitive polymer dielectric to form a first pattern which forms a first blind via exposing an end of the frame via-post at the upper surface of the frame and a second blind via revealing the back face of the chip;
    • removing the adhesive tape, and laminating or coating a second photosensitive polymer dielectric onto the terminal face of the chip and a lower surface of the frame;
    • exposing and developing the second photosensitive polymer dielectric to form a second pattern which forms a third blind via exposing a terminal of the chip and a fourth blind via exposing an end of the frame via-post at the lower surface of the frame;
    • applying a metal seed layer onto the first pattern and the second pattern;
    • applying a photoresist layer onto the metal seed layer, and patterning the photoresist layer to form a third pattern comprising a first wiring layer and a second wiring layer; and
    • performing Cu electroplating to simultaneously fill the first, second and third patterns to form first, second, third and fourth via-posts and the first and second wiring layers.
In some embodiments, the photosensitive polymer dielectric material is selected from a group comprising polyimide photosensitive resin and polyphenylene oxide photosensitive resin.
In some embodiments, the metal seed layer comprises Ti, W, or Ti/W alloys.
In some embodiments, the first wiring layer is conductively connected through the first via-post to the terminal pad of the chip, the second wiring layer is conductively connected through the second via-post to the back face of the chip.
Preferably, the frame via-post, the frame via-post, the first via-post, the second via-post, the third via-post and the fourth via-post comprises Cu.
In some embodiments, the method further comprises: after the Cu electroplating, removing the photoresist layer and etching off the exposed metal seed layer.
In some embodiments, the method further comprises: performing layer building-up and re-wiring on the first and/or second wiring layers to stack and construct an additional wiring layer.
In some embodiments, the method further comprises: applying a solder mask onto the first wiring layer and/or the second wiring layer.
Generally, the method further comprises: cutting the chip socket array into individual package chips.
The photosensitive polymer dielectric as mentioned herein means a type of photosensitive resin material having relatively low dielectric constant and dielectric loss. The photosensitive polymer dielectric commonly used now is a negative one which can excite a photoinitiator to cross-link and polymerize small-molecule unsaturated organic oligomers to form a stable solid organic polymer product, under the effect of light (such as UV light or visible light) or high energy rays (such as electron beam).
Generally, the photosensitive resin is used as a photoresist material such as that for photolithography. In the packaging applications as mentioned herein, however, it is necessary for this type of photosensitive polymer dielectric to have some special properties, such as relatively high dielectric properties within a relatively broad temperature range and frequency range (for example, a dielectric constant of 2.5˜3.4, a dielectric loss of 0.001˜0.01, a dielectric strength of 100 KV˜400 KV), and to have a relatively excellent adhesion, a relatively low stress, etc.
Herein, the photosensitive polymer dielectric is used as the chip packaging material, thus enabling to simplify the steps of the manufacturing process, improve the production efficiency and lower the cost. For example, it is possible to simultaneously form a plurality of patterns and then simultaneously perform electroplating and filling. Moreover, it is possible to avoid a risk of damage to embedded chips due to traditional hole-opening methods, thus improving the yield rate. Furthermore, as it is not necessary in the present method to grind the panel or frame, there is no risk of exposing glass fibers, for example.
BRIEF DESCRIPTION OF THE DRAWINGS
In order to better understand the present invention and illustrate the embodiments of the present invention, the accompanying drawings are referred to only in an exemplary way.
Now specifically referring to the figures/drawings, it should be emphasized that the specific graphical representation is provided only in an exemplary way, and only for the purpose of discussion of the preferred embodiments of the present invention. The graphical representation is provided for the reason that the figures are believed to be useful to make the principle(s) and concept(s) of the present invention understood easily. In this regard, it is intended to illustrate the structural details of the present invention only in a detail degree necessary to generally understand the present invention. In the figures:
FIG. 1 is a schematic side view of a first embedded chip structure;
FIG. 2 is a schematic side view of a second embedded chip structure;
FIG. 3 is a schematic side view of a third embedded chip structure; and
FIGS. 4A to 4I schematically show intermediate structures obtained by steps of the method of the present invention.
 DETAILED DESCRIPTION
The present invention relates to an embedded chip package, characterized in that a chip and a frame are embedded in a photosensitive polymer dielectric serving as a packaging material, an opening is formed directly on the back face of the chip with a metal post (such as Cu post) being deposited therein, while an opening is also formed on the terminal face of the chip by applying the photosensitive polymer dielectric to form a metal post for conducting a terminal of the chip, thereby forming a structure in which both sides of the chip can be used for conduction or heat dissipation.
The photosensitive polymer dielectric used in the present invention is mainly selected from polyimide photosensitive resin and polyphenylene oxide photosensitive resin, such as Microsystems HD-4100, Hitachi PVF-02, etc.
The metal post formed on the chip terminal face is used for connecting the chip terminal with the first wiring layer. The metal post formed on the chip back face is generally used as a heat dissipation pad or is connected to a heat dissipation device such that the heat can be dissipated more effectively. If the chip back face is also provided with a terminal (for example, the chip has a structure with a Si via passing through the chip, or there are a plurality of chips stacked in a back-to-back 3D manner), a Cu post formed on the chip back face also can provide a function of electric connection.
In addition, on the back face and the terminal face of the chip, it is also possible to further perform layer building-up to stack and construct an additional wiring layer to form a multi-layer interconnected structure, thus forming a so-called package-on-package (PoP) structure.
Referring to FIG. 1 , it shows an embedded chip package 100 with both faces being connected. The embedded chip package 100 comprises a chip 140 having a terminal face 141 and a back face 142 separated by a height of the chip. The chip 140 is disposed in a cavity 130 surrounded by a frame 110 which has a first frame face 111 coplanar with the chip terminal face 141 and an opposite second frame face 112. The frame 110 has a thickness larger than the height of the chip 140, generally by 15˜50 μm, such that the second frame face 112 is higher than the back face 142 of the chip 140. A gap between the chip 140 and the frame 110 is filled with a photosensitive polymer dielectric packaging material 160 comprising a polyimide photosensitive resin or a polyphenylene oxide photosensitive resin.
In contrast with prior embedded chip packages, in the chip package 100, the packaging material 160 not only covers the chip back face 142 and the second frame face 112, but also can cover the chip terminal face 141 and the first frame face 111. Thus, by photolithography and plate-filling, it is possible to form a layer of via-post respectively on both surfaces of the chip package 100 so as to accordingly conduct a first wiring layer 131 with a second wiring layer 132.
One or more conductive via-posts 120 (such as Cu via-posts) may be conFIGured to pass through the thickness of the frame 110. These via-posts 120 connect the first frame face 111 and the second frame face 112.
The chip 140 may be a device having a Si via passing through the chip or may comprise a plurality of chips stacked back to back such that the back face 142 of the chip 140 is provided with a terminal which is electrically connectable.
The frame 110 has a first polymer matrix, and may comprise glass fiber and ceramic fillers. In some embodiments, the frame 110 is made from a prepreg of woven glass fibers impregnated with polymer.
Referring to FIG. 2 , it shows an embedded chip package 200 with a heat dissipation pad formed on the chip back face. The embedded chip package 200 is similar in structure to the chip package 100 of FIG. 1 , with a difference only in that a heat dissipation pad 250 is formed by filling a heat dissipation metal in a large opening formed on the chip back face 142. This type of chip package 200 is applicable to large power devices, especially chips required to enable electric conduction on a single face and heat dissipation on both faces.
The chip packages 100 and 200 of FIGS. 1 and 2 are not limited to the case required to enable electric conduction on both faces or the case required to enable electric conduction on a single face and heat dissipation on both faces, and they are also applicable to the case required to enable electric conduction on a single face (the terminal face) of the chip, without any opening on the back face. In the chip packages 100 and 200 of FIGS. 1 and 2 , according the design requirement(s), the chip terminal face 141 may be covered with a photosensitive polymer dielectric 161 to lead out a metal terminal, or a wiring layer can be formed directly on the chip terminal face 141 flushing with the surface 111 of the frame 110, 210, without a layer of the photosensitive polymer dielectric 161.
FIG. 3 shows that on both sides of the chip package 100 of FIG. 1 , additional wiring layers 351, 352 are further formed to build up a multi-layer interconnection structure 300. Also, on the chip package 200 of FIG. 2 , it is possible to further build up an additional layer to form package-on-package (PoP) as well as a similar interconnection structure.
It is to be understood that the layer building up processing may be performed simultaneously on both sides of the frame. It is also to be understood that as the seed layers may be sputtered on both sides of the frame and the chip, additional wiring layers and conduction structures may be constructed on both sides. Once the wiring layer having a conductor feature structure is formed on the packaged one side or both sides, it is possible to attach another chip onto the conductor feature structure by means of technologies of Ball Grid Array (BGA) or Land Grid Array (LGA), etc.
It is to be understood that the packaging technologies described herein may be used to package chips having circuits on both sides. Thus, the wafer can be processed on both sides, for example, with a processor chip on one side and a memory chip on the other side.
It is to be understood that the packaging technologies described herein are not limited to IC chip packaging. In some embodiments, the chips comprise passive devices selected from fuse, capacitor, inductor and filter.
Referring to FIGS. 4A to 4I, a method for manufacturing the embedded chip package structure of FIG. 1 is shown. However, it is to be understood that the method may be applicable to manufacture other similar structures, such as those shown in FIGS. 2 and 3 .
The method comprises the step of obtaining a chip socket array comprising a first polymer frame 110 (referring to FIG. 4A), wherein each through socket 130 is defined by the frame 110, and optionally at least one frame via-post 120 passing through the frame 110 is included. It is possible to make an organic frame 110 according to the US patent publication US20160165731A1 wherein the frame 110 has upper and lower surfaces 112, 111 and a cavity or socket 130 in an array arrangement generated based on the chip size. The frame 110 has a thickness which is larger than and is close to the chip thickness, generally larger than the chip thickness by 15˜50 μm.
The frame 110 is placed on an adhesive tape 150. The chip 140, facing downwards (i.e. its terminal face facing downwards), is placed into a cavity 130 of the frame 110 such that the chip terminal face 141 is in contact with the adhesive tape 150 (referring to FIG. 4B). The adhesive tape 150 is generally a commercially available transparent film which can be decomposed by heating or exposure to UV light. It is possible to perform imaging through the adhesive tape to achieve alignment or exposure, thus facilitating curing of the photosensitive polymer dielectric.
On the frame 110 comprising the chip 140, a photosensitive polymer dielectric 160 (such as a polyimide photosensitive resin or a polyphenylene oxide photosensitive resin) serving as the packaging material is laminated or coated such that the photosensitive polymer dielectric 160 fully fills the gap between the chip 140 and the frame 110 and covers the back face 142 of the chip, an upper surface 112 of the frame and an upper surface 122 of the Cu post 120 (referring to FIG. 4C).
The photosensitive polymer dielectric 160 on the side of the chip back face is exposed by an exposure machine and is developed to form a first pattern. The photosensitive polymer dielectric in hole positions in the first pattern is not cured and thus is removed. Therefore, the first pattern comprises a first blind via 171 exposing the upper surface 122 of the frame via-post 120 on the frame 110 and a second blind via 172 exposing the back face 142 of the chip 140 (referring to FIG. 4C).
It is also possible to perform auxiliary exposure on the side of the adhesive tape to facilitate rapid curing of the photosensitive polymer dielectric filled between the frame and the chip.
Then, the adhesive tape 150 is removed, and the photosensitive polymer dielectric 161 is laminated or coated onto the terminal face 141 of the chip 140 and the lower surface 111 of the frame. The photosensitive polymer dielectric 161 is exposed and developed to form a second pattern. The second pattern comprises a third blind via 173 exposing a metal terminal pad on the terminal face 141 of the chip 140 and a fourth blind via 174 exposing a lower end face 121 of the frame via-post 120 on the frame lower surface 111 (referring to FIG. 4D).
According to the specific adhesive tape as used, the adhesive tape 150 may be burned out or removed by exposure to UV light. The photosensitive polymer dielectrics 160 and 161 may be the same or different photosensitive polymer dielectrics, and may be different only in thickness.
A chemical plating or sputtering method is used to form metal seed layers 180 on the surfaces of the photosensitive polymer dielectrics 160, 161 and in the blind vias 171, 172, 173, 174 (referring to FIG. 4E). The metal commonly used for the seed layer is selected from Ti, Cu, or Ti-Wu alloys, but is not limited to the above metals.
Photoresist layers 190 are applied onto the metal seed layers 180 on both sides of the package 100, and a third pattern comprising a first wiring layer and a second wiring layer is formed directly by means of exposure and development. The third pattern of the photoresist layer 190 formed by exposure and development exposes the metal seed layers 180 in positions where it is necessary to form the first and second wiring layers (referring to FIG. 4F).
An electroplating method is used to plate and fill Cu into the first, second and third patterns such that all the opened blind vias and openings on the wiring layers are filled with Cu simultaneously to form first, second, third and fourth via- posts 120 a, 120 b, 120 c, 120 d as well as the first and second wiring layers 131, 132 (referring to FIG. 4G).
A dry-film remover agent is used to remove the photoresist layer 190, and then an etching method is used to remove the exposed metal seed layers 180 (referring to FIG. 4H).
According to the specific requirement(s), the layer building up and re-wiring processes can be performed for several times on the upper and lower surfaces of the substrate, without any surface treatment, to stack and construct an additional wiring layer. The dielectric for the layer building up may be the photosensitive polymer dielectric or the traditional packaging material, such as a thermosetting dielectric or a thermoplastic dielectric. The method for the layer building up to form an additional wiring layer may be a common method, such as dry etching, etc.
The finished embedded chip package may be applied with a solder mask 195 on one side or both sides of the outer layer by coating or laminating. The solder resist comprises AUS308 or AUS410, etc., but is not limited to the above materials. On the solder mask 195, a specific solder mask window 196 may be formed by photoresist exposure and development (referring to FIG. 4I).
Finally, the panel array can be cut and divided into individual chip packages. The dividing or cutting may be achieved by using a rotating saw blade or other cutting technologies, such as using a laser.
It will be appreciated by those skilled in the art that the present invention is not limited to the contents as specifically illustrated and described above. Moreover, the scope of the present invention is defined by the appended claims, comprising combinations and sub-combinations of the various technical features as described above as well as the variations and modifications thereof, which can be anticipated by those skilled in the art by reading the above description.

Claims (9)

What is claimed is:
1. A method for manufacturing an embedded chip package, the method comprising:
obtaining a chip socket array comprising a frame, wherein the frame is formed therein with a frame via-post passing through a height of the frame;
placing the chip socket array onto an adhesive tape;
placing a chip, with a terminal face of the chip facing downwards, into a cavity of the chip socket array surrounded by the frame;
laminating or coating a first photosensitive polymer dielectric onto the chip and the frame such that the first photosensitive polymer dielectric fully fills a gap between the chip and the frame and covers a back face of the chip and an upper surface of the frame;
exposing and developing the first photosensitive polymer dielectric to form a first pattern which forms a first blind via exposing an end of the frame via-post at the upper surface of the frame and a second blind via revealing the back face of the chip;
removing the adhesive tape, and laminating or coating a second photosensitive polymer dielectric onto the terminal face of the chip and a lower surface of the frame;
exposing and developing the second photosensitive polymer dielectric to form a second pattern which forms a third blind via exposing a terminal of the chip and a fourth blind via exposing an end of the frame via-post at the lower surface of the frame;
applying a metal seed layer onto the first pattern and the second pattern;
applying a photoresist layer onto the metal seed layer, and patterning the photoresist layer to form a third pattern comprising a first wiring layer and a second wiring layer; and
performing Cu electroplating to simultaneously fill the first, second and third patterns to form first, second, third and fourth via-posts and the first and second wiring layers.
2. The method according to claim 1, wherein the first photosensitive polymer dielectric and the second photosensitive polymer dielectric are selected from polyimide photosensitive resin or polyphenylene oxide photosensitive resin.
3. The method according to claim 1, wherein the metal seed layer comprises Ti, W, or Ti/W alloys.
4. The method according to claim 1, wherein the first wiring layer is conductively connected through the first via-post to a terminal pad of the chip, the second wiring layer is conductively connected through the second via-post to the back face of the chip.
5. The method according to claim 1, wherein the frame via-post, the first via-post, the second via-post, the third via-post and the fourth via-post comprises Cu.
6. The method according to claim 1, further comprising:
after the Cu electroplating, removing the photoresist layer and etching off the metal seed layer.
7. The method according to claim 6, further comprising:
performing layer building-up and re-wiring on the first and/or second wiring layers to stack and construct an additional wiring layer.
8. The method according to claim 1, further comprising:
applying a solder mask onto the first wiring layer and/or the second wiring layer.
9. The method according to claim 1, further comprising:
cutting the chip socket array into individual package chips.
US18/389,264 2020-04-02 2023-11-14 Embedded chip package and manufacturing method thereof Active US12148676B2 (en)

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CN202010255623.9 2020-04-02
CN202010255623.9A CN111554639A (en) 2020-04-02 2020-04-02 Embedded chip package and method of manufacturing the same
US17/044,087 US11854920B2 (en) 2020-04-02 2020-05-12 Embedded chip package and manufacturing method thereof
PCT/CN2020/089735 WO2021196351A1 (en) 2020-04-02 2020-05-12 Embedded chip package and manufacturing method therefor
US18/389,264 US12148676B2 (en) 2020-04-02 2023-11-14 Embedded chip package and manufacturing method thereof

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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554639A (en) * 2020-04-02 2020-08-18 珠海越亚半导体股份有限公司 Embedded chip package and method of manufacturing the same
CN113053849B (en) * 2021-03-04 2022-02-15 珠海越亚半导体股份有限公司 Embedded support frame and substrate of integrated inductor and manufacturing method thereof
CN115224016A (en) * 2021-04-20 2022-10-21 长电科技管理有限公司 Stacked package module and method for manufacturing the same
TWI795959B (en) * 2021-04-23 2023-03-11 強茂股份有限公司 Surface-mounted power semiconductor packaging component and its manufacturing method
CN113471347A (en) * 2021-05-14 2021-10-01 南通越亚半导体有限公司 LED embedded packaging substrate and manufacturing method thereof
CN113451259B (en) * 2021-05-14 2023-04-25 珠海越亚半导体股份有限公司 Multi-device fractional embedded packaging substrate and manufacturing method thereof
CN113555290B (en) * 2021-07-16 2025-08-05 奈电软性科技电子(珠海)有限公司 A rewiring method for double-sided electrode chip and a core board
US12205865B2 (en) 2021-11-01 2025-01-21 Micron Technology, Inc. Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same
US20230139175A1 (en) * 2021-11-01 2023-05-04 Micron Technology, Inc. Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same
CN114361040B (en) * 2021-11-18 2023-03-24 珠海越亚半导体股份有限公司 A double-sided interconnection embedded chip packaging structure and manufacturing method thereof
CN115103509A (en) * 2022-05-06 2022-09-23 珠海越亚半导体股份有限公司 Integrated inductor embedded substrate and manufacturing method thereof
US12368142B2 (en) * 2022-05-27 2025-07-22 Taiwan Semiconductor Manufacturing Company Limited Double side integration semiconductor package and method of forming the same
US20240021488A1 (en) * 2022-07-15 2024-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated Circuit Package and Method
TWI814612B (en) * 2022-10-12 2023-09-01 創新服務股份有限公司 Substrate electronic component implantation method and device
CN115799074A (en) * 2022-11-30 2023-03-14 上海美维科技有限公司 Manufacturing method of embedded packaging structure
CN117238894B (en) * 2023-09-26 2024-07-09 江苏卓胜微电子股份有限公司 Packaging structure, chip structure and preparation method of chip structure
TWI879344B (en) * 2023-12-25 2025-04-01 友達光電股份有限公司 Semiconductor structure and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190237382A1 (en) * 2018-01-29 2019-08-01 Samsung Electronics Co., Ltd. Semiconductor package including a thermal conductive layer and method of manufacturing the same
US20200328160A1 (en) * 2019-04-12 2020-10-15 Samsung Electro-Mechanics Co., Ltd. Semiconductor package

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100867631B1 (en) * 2007-02-01 2008-11-10 삼성전자주식회사 Semiconductor device and manufacturing method thereof
US20110290540A1 (en) * 2010-05-25 2011-12-01 Samsung Electro-Mechanics Co., Ltd. Embedded printed circuit board and method of manufacturing the same
US20150279814A1 (en) * 2014-04-01 2015-10-01 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Embedded chips
US10381326B2 (en) * 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9666559B2 (en) * 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9554469B2 (en) 2014-12-05 2017-01-24 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Method of fabricating a polymer frame with a rectangular array of cavities
US9929100B2 (en) * 2015-04-17 2018-03-27 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US9911700B2 (en) * 2016-01-26 2018-03-06 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Embedded packages
KR101952865B1 (en) * 2016-10-10 2019-02-27 삼성전기주식회사 Fan-out semiconductor package and photosensitive resin composition
JP6858576B2 (en) * 2017-01-30 2021-04-14 新光電気工業株式会社 Manufacturing method of semiconductor devices
KR20190013051A (en) * 2017-07-31 2019-02-11 삼성전기주식회사 Fan-out semiconductor package
EP4531102A3 (en) 2017-10-25 2025-07-02 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding component with pre-connected pillar in component carrier
CN110858548A (en) * 2018-08-22 2020-03-03 深南电路股份有限公司 Embedded chip and its manufacturing method
KR102164794B1 (en) * 2018-08-27 2020-10-13 삼성전자주식회사 Fan-out semiconductor package
CN111554639A (en) * 2020-04-02 2020-08-18 珠海越亚半导体股份有限公司 Embedded chip package and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190237382A1 (en) * 2018-01-29 2019-08-01 Samsung Electronics Co., Ltd. Semiconductor package including a thermal conductive layer and method of manufacturing the same
US20200328160A1 (en) * 2019-04-12 2020-10-15 Samsung Electro-Mechanics Co., Ltd. Semiconductor package

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