TWM638620U - Testing probes and probe cards - Google Patents
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- TWM638620U TWM638620U TW111211561U TW111211561U TWM638620U TW M638620 U TWM638620 U TW M638620U TW 111211561 U TW111211561 U TW 111211561U TW 111211561 U TW111211561 U TW 111211561U TW M638620 U TWM638620 U TW M638620U
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Abstract
本創作揭露一種測試探針及探針卡。測試探針包含金屬本體、內絕緣層、導電層及外絕緣層。金屬本體的兩端分別為連接端及接觸端。金屬本體的接觸端用以與待測物接觸。內絕緣層包覆金屬本體的部分區段。導電層包覆內絕緣層的部分區段。外絕緣層包覆導電層的部分區段,而導電層的一接地區段是露出於外絕緣層。導電層的接地區段用以接地。本創作的測試探針及包含有所述測試探針的探針卡,通過內絕緣層、導電層、外絕緣層及接地區段的設計,可以使測試探針具有相對較高的訊號解析度。This creation discloses a test probe and a probe card. The test probe includes a metal body, an inner insulating layer, a conductive layer and an outer insulating layer. The two ends of the metal body are the connection end and the contact end respectively. The contact end of the metal body is used for contacting the object to be tested. The inner insulation layer covers a part of the metal body. The conductive layer covers a partial section of the inner insulating layer. The outer insulating layer covers a part of the conductive layer, and a grounding section of the conductive layer is exposed from the outer insulating layer. The ground area of the conductive layer is used for grounding. The test probe and the probe card containing the test probe of the invention can make the test probe have a relatively high signal resolution through the design of the inner insulating layer, the conductive layer, the outer insulating layer and the grounding section .
Description
本創作涉及一種測試探針及探針卡,特別是一種適合對半導體構件(例如各式晶片)進行高頻測試的測試探針及探針卡。The invention relates to a test probe and a probe card, especially a test probe and a probe card suitable for high-frequency testing of semiconductor components (such as various chips).
隨著半導體晶片的操作頻率愈來愈高,在利用探針對晶片進行量測的過程中,各個探針的訊號更容易受到外部訊號或是相鄰的探針的訊號干擾,為此,將造成探針的訊號的解析度降低。As the operating frequency of semiconductor wafers is getting higher and higher, the signals of each probe are more likely to be interfered by external signals or signals of adjacent probes during the process of measuring the wafer with probes. For this reason, it will cause The resolution of the signal from the probe is reduced.
另外,隨著晶片尺寸越來越小,探針的尺寸也隨之越來越小,且多個探針彼此間的距離也隨之越來越小,因此,當探針瞬間有電流通過時,各探針容易發生電弧放電的情況,進而可能發生燒毀探針的問題。In addition, as the size of the wafer becomes smaller and smaller, the size of the probes is also smaller and smaller, and the distance between multiple probes is also smaller and smaller. Therefore, when a current flows through the probes instantaneously , Each probe is prone to arc discharge, and then the problem of burning the probe may occur.
本創作公開一種測試探針及探針卡,主要用以改善現有應用於半導體測試的探針,在對半導體晶片進行高頻測試時,探針容易受到外部訊號干擾的問題,且在探針瞬間有電流通過時,探針容易發生電弧放電的情況,從而容置導致探針發生燒毀的問題。This creation discloses a test probe and a probe card, which are mainly used to improve the existing probes used in semiconductor testing. When performing high-frequency testing on semiconductor chips, the probes are easily interfered by external signals, and the probes are instantly When a current is passed, the probe is prone to arcing, thereby accommodating the problem of burning the probe.
本創作的其中一實施例公開一種測試探針,其包含:一金屬本體、一內絕緣層、一導電層及一外絕緣層。金屬本體的兩端分別定義為一接觸端及一連接端,接觸端用以接觸待測物,金屬本體於連接端具有一未遮蔽區段,且未遮蔽區段的長度,不大於金屬本體的整體長度的3分之1;內絕緣層形成於金屬本體的至少一區段的外圍,內絕緣層未形成於未遮蔽區段;導電層形成於內絕緣層的至少一區段的外圍,且內絕緣層的至少百分之80的區段的外圍都形成有導電層;外絕緣層形成於導電層的部分區段的外圍;其中,導電層鄰近於連接端的一端具有一接地區段,接地區段不形成有外絕緣層,且接地區段是用以接地。較佳地,內絕緣層的至少百分之80至百分之90的區段的外圍都形成有導電層。One embodiment of the present invention discloses a test probe, which includes: a metal body, an inner insulating layer, a conductive layer and an outer insulating layer. The two ends of the metal body are respectively defined as a contact end and a connection end. The contact end is used to contact the object to be tested. The metal body has an unshielded section at the connection end, and the length of the unshielded section is not greater than that of the metal body. 1/3 of the overall length; the inner insulating layer is formed on the periphery of at least one section of the metal body, the inner insulating layer is not formed on the unshielded section; the conductive layer is formed on the outer periphery of at least one section of the inner insulating layer, and A conductive layer is formed on the periphery of at least 80 percent of the section of the inner insulating layer; the outer insulating layer is formed on the periphery of a part of the section of the conductive layer; wherein, one end of the conductive layer adjacent to the connecting end has a grounding section, the grounding The ground section is not formed with an outer insulating layer, and the ground section is used for grounding. Preferably, at least 80% to 90% of the inner insulation layer is formed with a conductive layer on its periphery.
本創作的其中一實施例公開一種探針卡,其包含:本創作的測試探針、一上導板、一下導板及至少一固定構件。上導板包含一接地結構,各個測試探針的連接端固定於上導板,且接地區段與接地結構相連接,接地結構用以接地;各個測試探針鄰近於接觸端的部分區段,固定於下導板;至少一固定構件,其用以使上導板與下導板相互固定。One embodiment of the invention discloses a probe card, which includes: the test probe of the invention, an upper guide plate, a lower guide plate and at least one fixing member. The upper guide plate includes a grounding structure, the connecting ends of each test probe are fixed on the upper guide plate, and the grounding section is connected to the grounding structure, and the grounding structure is used for grounding; On the lower guide plate; at least one fixing member, which is used to fix the upper guide plate and the lower guide plate to each other.
綜上所述,本創作的測試探針及探針卡,通過內絕緣層、導電層、外絕緣層及接地區段等設計,測試探針及探針卡在對半導體晶片進行測試時,特別是進行高頻測試時,測試探針的訊號,將不易受到外部訊號的干擾,且也可以大幅降地相鄰的測試探針彼此發生訊號干擾的問題;另外,測試探針在電流瞬間通過時,也相對不容易發生電弧放電的情況,藉此,確保了測試探針的使用壽命。In summary, the test probes and probe cards of this creation are designed through the inner insulating layer, conductive layer, outer insulating layer and grounding section. When testing the semiconductor wafer, the test probes and probe cards are especially When performing high-frequency testing, the signal of the test probe will not be easily interfered by external signals, and it can also greatly reduce the problem of signal interference between adjacent test probes; in addition, when the current passes through the test probe instantaneously , and it is relatively less prone to arc discharge, thereby ensuring the service life of the test probe.
為能更進一步瞭解本創作的特徵及技術內容,請參閱以下有關本創作的詳細說明與附圖,但是此等說明與附圖僅用來說明本創作,而非對本創作的保護範圍作任何的限制。In order to further understand the characteristics and technical content of this creation, please refer to the following detailed description and drawings about this creation, but these descriptions and drawings are only used to illustrate this creation, not to make any statement on the scope of protection of this creation limit.
於以下說明中,如有指出請參閱特定圖式或是如特定圖式所示,其僅是用以強調於後續說明中,所述及的相關內容大部份出現於該特定圖式中,但不限制該後續說明中僅可參考所述特定圖式。In the following description, if it is pointed out that please refer to the specific drawing or as shown in the specific drawing, it is only used to emphasize in the subsequent description, most of the relevant content mentioned appears in the specific drawing, It is not intended, however, to limit the ensuing description to only those particular drawings referred to.
請一併參閱圖1至圖3,圖1為本創作的測試探針的立體示意圖,圖2為本創作的測試探針沿圖1的剖線II-II的剖面示意圖,圖3為本創作的測試探針沿圖1的剖線III-III的剖面示意圖。本創作的測試探針1包含:一金屬本體11、一內絕緣層12、一導電層13及一外絕緣層14。本創作的測試探針1可以應用於各式半導體物件的測試,例如是各式晶片、晶圓的測試等,且本創作的測試探針1特別適合用來對半導體晶片進行高頻測試。Please refer to Figures 1 to 3 together. Figure 1 is a perspective view of the test probe of this creation, Figure 2 is a schematic cross-sectional view of the test probe of this creation along the section line II-II in Figure 1, and Figure 3 is a schematic view of this creation The schematic cross-sectional view of the test probe along the section line III-III in Fig. 1. The
需說明的是,於本實施例的圖式中,金屬本體11、內絕緣層12、導電層13及外絕緣層14的厚度、長度、彼此間的比例關係,都僅是為了方便理解所繪示,而非依據真實數據進行繪示。It should be noted that in the drawings of this embodiment, the thickness, length, and proportional relationship between the
金屬本體11的兩端分別定義為一接觸端111及一連接端112,接觸端111用以接觸待測物,所述待測物例如是任何半導體物件,例如各式晶片、晶圓等。金屬本體11的連接端112是用來與檢測設備相連接。Two ends of the
於本實施例中,是以金屬本體11可以是大致為矩形柱狀結構(即業界俗稱的方針形式)為例,但金屬本體11的外型不以此為限,在不同的實施例中,金屬本體11也可以是大致為圓柱狀結構。於此所指的金屬本體11與習知的各式半導體測試用探針大致相同,而金屬本體11的外型、材質的選用,可以是與習知的各式半導體測試用探針大致相同;亦即,在不同的實施例中,本創作的測試探針1的部分區段也可以是呈現為彎曲狀。In this embodiment, it is taken as an example that the
內絕緣層12形成於金屬本體11的至少一區段的外圍。在實務中,內絕緣層12例如可以是真空濺鍍的方式,形成於金屬本體11的外圍。內絕緣層12例如可以是氧化鋁或氮化鋁,但不以此為限。如圖3所示,在金屬本體11形成有內絕緣層12的區段的剖面圖中,金屬本體11的外圍是被內絕緣層12所包覆,而內絕緣層12不是僅形成於金屬本體11的某一個外側面。The inner insulating
金屬本體11於連接端112具有一未遮蔽區段113,內絕緣層12未形成於未遮蔽區段113,且未遮蔽區段113的長度113D,可以是不大於金屬本體11的整體長度11D的3分之1。也就是說,內絕緣層12不是完全地包覆於金屬本體11的外圍。The
在其中一個具體實施例中,金屬本體11例如可以是包含一本體部114及一接觸部115,本體部114的一端與接觸部115連接,本體部114的另一端為連接端112,金屬本體11於接觸部115的外徑是由靠近本體部114的方向向遠離本體部114的方向逐漸遞減。內絕緣層12是形成於本體部114,未遮蔽區段113的長度113D是本體部114的整體長度114D的10分之8至10分之9。需強調的是,在不同的實施例中,金屬本體11也可以是僅包含有本體部114而不包含有接觸部115。In one of the specific embodiments, the
導電層13形成於內絕緣層12的至少一區段的外圍,內絕緣層12的至少百分之80的區段的外圍都形成有導電層13。在實際應用中,導電層13是以真空濺鍍的方式形成於內絕緣層12的外圍。較佳地,內絕緣層12的至少百分之80至百分之90的區段的外圍都形成有導電層13。The
較佳地,導電層13可以是一石墨烯合金層,石墨烯合金層中的石墨烯的含量為1ppm~1000ppm,且石墨烯合金層中的其餘合金為鉬(Mo)、鈦(Ti)、銀(Ag)、金(Au)、鈀(Pd)、鉑(Pt)、鎳(Ni)、銅(Cu)、鉻(Cr)、鎢(W)、釩(V)、鈮(Nb)、鋯(Zr) 、鉭(Ta)、鐵(Fe)、鈷(Co)、釕(Ru)、銠(Rh)、銥(Ir)、鋁(Al)、釔(Y)、矽(Si)、鍺(Ge)、錫(Sn)、鉿(Hf)的其中之一。在實務中,石墨烯合金層中其餘合金可以是選用銅,如此,可以降低測試探針1的製造成本。在不同的實施例中,導電層13也可以是包含奈米碳管或富勒烯(Fullerene,俗稱巴克球)。Preferably, the
在導電層13為石墨烯合金層的實施例中,可以是於銅靶材中混入石墨烯粉末,或者,於銅靶材上設置石墨烯粉末,並於真空濺鍍機中通入氬氣,在產生電漿後,將銅金屬與石墨烯共同濺鍍在金屬本體11的內絕緣層12的部分區段,而於內絕緣層12的外圍形成石墨烯合金導電膜(即所述導電層13)。In the embodiment where the
外絕緣層14形成於導電層13的部分區段的外圍。在實際應用中,外絕緣層14可以是以真空濺鍍的方式形成於導電層13的外圍。外絕緣層14例如可以是氧化鋁或氮化鋁,但不以此為限。如圖3所示,在導電層13形成有外絕緣層14的區段的剖面圖中,導電層13的外圍是被外絕緣層14所包覆,而外絕緣層14不是僅形成於導電層13的某一個外側面。The outer
導電層13鄰近於連接端112的一端具有一接地區段131,接地區段131不形成有外絕緣層14,且接地區段131是用以接地。也就是說,導電層13的外圍,不是都被外絕緣層14所包覆,而導電層13未被外絕緣層14所包覆的接地區段131,是用來接地。關於導電層13的接地方式,例如可以是通過與探針卡的相關接地電路連接,來達到接地的效果,或者,導電層13也可以是通過電線等相關構件,間接地達到接地的效果,當然,用來與導電層13相連接的相關構件,是不與金屬本體11相連接。在較佳的實施例,接地區段131沿金屬本體11的長度方向的長度131D,可以是介於1微米(㎛)~1000微米(㎛)。One end of the
值得一提的是,在實際應用中,導電層13及內絕緣層12於鄰近於接觸端111的一端可以是相互齊平,如此,可以避免測試探針1的接觸端111與待測物相接觸時,導電層13靠近接觸端111的區段與相鄰的另一個測試探針1的導電層13相接觸。內絕緣層12鄰近於連接端112的一端,可以是具有一內絕緣層外露區段121,內絕緣層外露區段121未被導電層13所包覆。It is worth mentioning that, in practical applications, the end of the
也就是說,內絕緣層12除了內絕緣層外露區段121是不被導電層13包覆外,內絕緣層12的其餘區段可以是都被導電層13所包覆,而內絕緣層外露區段121的長度121D。較佳地,內絕緣層外露區段121的長度121D,可以是介於1微米(㎛)~1000微米(㎛)。That is to say, except that the exposed section 121 of the inner
通過內絕緣層外露區段121的設計,可以有效地避免用來與接地區段131相接觸的相關構件(例如電線等),接觸到金屬本體11。當然,在不同的實施例中,內絕緣層12也可以是不包含有所述內絕緣層外露區段121。Through the design of the exposed section 121 of the inner insulating layer, it is possible to effectively prevent related components (such as wires, etc.) used to contact the
需特別強調的是,若是利用真空濺鍍的方式,形成內絕緣層12、導電層13及外絕緣層14,則可以使內絕緣層12的厚度是介於10奈米(nm)~2000奈米(nm),導電層13的厚度介於10奈米(nm)~2000奈米(nm),外絕緣層14的厚度介於10奈米(nm)~2000奈米(nm),如此,多個測試探針1可應用於測試小尺寸晶片的探針卡中。It should be emphasized that if the inner insulating
換句話說,若是利用真空濺鍍的方式形成內絕緣層12、導電層13及外絕緣層14,本創作的測試探針1可以是直接取代,用來測試小尺寸晶片的習知的探針卡中的探針,而基本上可以不用額外修改習知的探針卡中的其他結構。In other words, if the inner insulating
依上所述,本創作的測試探針1通過內絕緣層12、導電層13及外絕緣層14的設計,配合使導電層13的接地區段131接地等設計,可以達到有效地降低外來雜訊對於測試探針1的干擾的技術功效,且可以有效地降低測試探針1接收外部訊號的情況,從而可以達到提升測試探針1的訊號解析度的技術功效。According to the above, the
值得一提的是,在實務中,通過使未遮蔽區段113的長度113D,不大於金屬本體11的整體長度11D的3分之1,或者,使未遮蔽區段113的長度113D是本體部114的整體長度114D的10分之8至10分之9等設計,並配合使導電層13包覆內絕緣層12,除了內絕緣層外露區段121的其他區段,且使導電層13接地等設計,將可以確保測試探針1可以達到上述所述的各種技術功效。It is worth mentioning that, in practice, by making the
在現有常見的半導體測試探針,在測試探針瞬間通入電流時,測試探針容易發生電弧放電的情況,為此,可能導致測試探針發生燒毀的問題,本創作的測試探針1通過導電層13及接地區段131的設計,將可以有效地避免測試探針1發生燒毀的問題。In the existing common semiconductor test probes, when the current is applied to the test probes instantly, the test probes are prone to arc discharge. For this reason, the test probes may burn out. The
需特別說明的是,通過外絕緣層14的設計,若測試探針1在對待測物進行測試的過程中,發生了彎曲的情況,各測試探針1的導電層13,也不會相互接觸,而各測試探針1仍然可以正常地運作。It should be noted that, through the design of the outer insulating
請一併參閱圖4及圖5,圖4為本創作的探針卡的剖面示意圖,圖5為圖4的局部放大示意圖。本創作的探針卡(Probe Card)A包含多個測試探針(Probe)1(圖中僅以兩個為示範)、一上導板(Upper Die)2、一下導板(Lower Die)3及多個固定構件4。關於各個測試探針1的詳細說明,請參閱前述實施例,於此不再贅述。Please refer to FIG. 4 and FIG. 5 together. FIG. 4 is a schematic cross-sectional view of the probe card created by the present invention, and FIG. 5 is a partially enlarged schematic view of FIG. 4 . The probe card (Probe Card) A of this creation includes multiple test probes (Probe) 1 (only two are shown in the figure), an upper guide plate (Upper Die) 2, and a lower guide plate (Lower Die) 3 And a plurality of fixing
上導板2包含多個接地結構22,各個測試探針1的連接端112固定於上導板2,且測試探針1的接地區段131與接地結構22相連接,接地結構22用以接地。各個測試探針1鄰近於接觸端111的部分區段,固定於下導板3。固定構件4用以使上導板2與下導板3相互固定。固定構件4主要是用來使上導板2及下導板3相互固定,舉例來說,固定構件4可以是螺絲等構件。The
更詳細來說,上導板2及下導板3例如分別包含有多個上穿孔21及多個下穿孔31,各個測試探針1分別穿過一個上穿孔21及一個下穿孔31,上導板2於形成各個上穿孔21的內壁形成有接地結構22(例如是導電的金屬結構層),各個測試探針1的導電層13的接地區段131,則是對應與上導板2的接地結構22相連接,而各個測試探針1的導電層13則是通過接地區段131及上導板2的接地結構22接地。關於上導板2的接地結構22的接地方式,可以依據需求加以設計,例如上導板2的所有接地結構22相互連接,並通過一電線等構件,直接或間接地連接至大地。需說明的是,只要接地結構22可以與各個測試探針1的導電層13的接地區段131相連接,上導板2的接地結構22設置位置可依據需求變化。In more detail, the
依上所述,本創作的探針卡A與習知的探針卡最大不同之處在於:本創作的探針卡A是包含本創作的測試探針1,且上導板2具有接地結構22,除此之外,本創作的探針卡A可以依據需求,包含有現有各式探針卡所包含的其餘構件及結構。According to the above, the biggest difference between the probe card A of this creation and the conventional probe card is: the probe card A of this creation contains the
本創作的探針卡A通過上導板2的接地結構22及各個測試探針1等設計,探針卡A應用於半導體晶片的高頻測試時,各個測試探針1的量測訊號將不容易受外部雜訊干擾,且相鄰的測試探針1彼此分別產生的訊號,也不容易相互干擾;另外,探針卡A在瞬間通入電流的情況下,各個測試探針1也不容易發生電弧放電的情況,而各個測試探針1不容易發生燒毀的問題。The probe card A of this creation is designed through the
以上所述僅為本創作的較佳可行實施例,非因此侷限本創作的專利範圍,故舉凡運用本創作說明書及圖式內容所做的等效技術變化,均包含於本創作的保護範圍內。The above is only the preferred feasible embodiment of this creation, and does not limit the patent scope of this creation. Therefore, all equivalent technical changes made by using the instructions and drawings of this creation are included in the protection scope of this creation. .
A:探針卡
1:測試探針
11:金屬本體
11D:長度
111:接觸端
112:連接端
113:未遮蔽區段
113D:長度
114:本體部
114D:長度
115:接觸部
12:內絕緣層
121:內絕緣層外露區段
121D:長度
13:導電層
131:接地區段
131D:長度
14:外絕緣層
2:上導板
21:上穿孔
22:接地結構
3:下導板
31:下穿孔
4:固定構件A: Probe card
1: Test probe
11:
圖1為本創作的測試探針的立體示意圖。FIG. 1 is a three-dimensional schematic diagram of the test probe of the present invention.
圖2為本創作的測試探針沿圖1的剖線II-II的剖面示意圖。FIG. 2 is a schematic cross-sectional view of the test probe of the present invention along the section line II-II in FIG. 1 .
圖3為本創作的測試探針沿圖1的剖線III-III的剖面示意圖。FIG. 3 is a schematic cross-sectional view of the test probe of the present invention along the section line III-III in FIG. 1 .
圖4為本創作的探針卡的剖面示意圖。FIG. 4 is a schematic cross-sectional view of the probe card of the present invention.
圖5為圖4的局部放大示意圖。FIG. 5 is a partially enlarged schematic diagram of FIG. 4 .
1:測試探針 1: Test probe
11:金屬本體 11: Metal body
111:接觸端 111: contact end
112:連接端 112: connection end
113:未遮蔽區段 113: Unmasked section
114:本體部 114: body part
115:接觸部 115: contact part
12:內絕緣層 12: Inner insulating layer
121:內絕緣層外露區段 121: Inner insulating layer exposed section
13:導電層 13: Conductive layer
131:接地區段 131: Grounding section
14:外絕緣層 14: Outer insulating layer
Claims (13)
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|---|---|---|---|
| TW111211561U TWM638620U (en) | 2022-10-24 | 2022-10-24 | Testing probes and probe cards |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111211561U TWM638620U (en) | 2022-10-24 | 2022-10-24 | Testing probes and probe cards |
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| Publication Number | Publication Date |
|---|---|
| TWM638620U true TWM638620U (en) | 2023-03-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116381442A (en) * | 2023-04-12 | 2023-07-04 | 渭南木王智能科技股份有限公司 | A high-conductivity injection molded semiconductor test needle |
| TWI855403B (en) * | 2022-10-24 | 2024-09-11 | 洛克半導體材料股份有限公司 | Test probe and probe card |
-
2022
- 2022-10-24 TW TW111211561U patent/TWM638620U/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI855403B (en) * | 2022-10-24 | 2024-09-11 | 洛克半導體材料股份有限公司 | Test probe and probe card |
| CN116381442A (en) * | 2023-04-12 | 2023-07-04 | 渭南木王智能科技股份有限公司 | A high-conductivity injection molded semiconductor test needle |
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