TWM638224U - Semiconductor package - Google Patents
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- TWM638224U TWM638224U TW111210412U TW111210412U TWM638224U TW M638224 U TWM638224 U TW M638224U TW 111210412 U TW111210412 U TW 111210412U TW 111210412 U TW111210412 U TW 111210412U TW M638224 U TWM638224 U TW M638224U
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- thermally conductive
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- heat dissipation
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 230000017525 heat dissipation Effects 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910001338 liquidmetal Inorganic materials 0.000 claims abstract description 20
- 238000007789 sealing Methods 0.000 claims description 32
- 239000010410 layer Substances 0.000 claims description 15
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 8
- 239000000565 sealant Substances 0.000 description 4
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 231100000956 nontoxicity Toxicity 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
本揭露是有關於一種具有導熱密封件的半導體封裝。 The present disclosure relates to a semiconductor package with a thermally conductive seal.
隨著對高性能散熱能力的要求,散熱膏已逐漸無法滿足現今的散熱需求。由發熱元件與散熱裝置的熱阻決定了單位時間內熱量傳遞的多少,由此選用導熱率高、接觸面結合性好的材料對於提升散熱性能十分必要。液態金屬雖具有無毒、揮發性低、導熱係數高等特點,便成為較受歡迎的選擇。然而,液態金屬由於流動性高,填充在發熱元件與散熱裝置之間時容易有外漏及溢流的問題,若額外設置多個隔絕材來防止溢流,除了會增加組裝步驟的繁複程度以外,也會提升元件間的熱阻,降低散熱效能。 With the demand for high-performance heat dissipation, thermal paste has gradually been unable to meet today's heat dissipation requirements. The heat transfer rate per unit time is determined by the thermal resistance of the heating element and the cooling device. Therefore, it is necessary to select materials with high thermal conductivity and good contact surface bonding to improve heat dissipation performance. Although liquid metal has the characteristics of non-toxicity, low volatility and high thermal conductivity, it has become a more popular choice. However, due to the high fluidity of liquid metal, it is easy to have leakage and overflow problems when filling between the heating element and the heat sink. If additional insulating materials are provided to prevent overflow, it will not only increase the complexity of the assembly steps , will also increase the thermal resistance between components and reduce the heat dissipation performance.
本揭露提供一種半導體封裝,其可簡化組裝步驟以及提升散熱效能。 The disclosure provides a semiconductor package, which can simplify assembly steps and improve heat dissipation performance.
本揭露的一種半導體封裝包括基板、第一電子元件、第二電子元件、散熱元件、液態金屬導熱層及導熱密封件。第一電子元 件設置於基板上。第二電子元件與第一電子元件並列設置於基板上。散熱元件設置於第一電子元件上並包括延伸至第二電子元件上方的延伸部。液態金屬導熱層設置於散熱元件與第一電子元件之間並與散熱元件與第一電子元件形成熱耦接。導熱密封件環繞第一電子元件並填充於第一電子元件與第二電子元件之間的間隙以及第二電子元件與延伸部之間的間隙。 A semiconductor package disclosed in the present disclosure includes a substrate, a first electronic component, a second electronic component, a heat dissipation component, a liquid metal heat conduction layer, and a heat conduction seal. first electronic unit components are placed on the substrate. The second electronic component is arranged side by side with the first electronic component on the substrate. The heat dissipation element is disposed on the first electronic component and includes an extension extending above the second electronic component. The liquid metal thermal conduction layer is arranged between the heat dissipation element and the first electronic element and forms a thermal coupling with the heat dissipation element and the first electronic element. The thermally conductive sealing member surrounds the first electronic component and fills the gap between the first electronic component and the second electronic component and the gap between the second electronic component and the extension.
在本揭露的一實施例中,第一電子元件包主動元件,而第二電子元件包括被動元件。 In an embodiment of the present disclosure, the first electronic component includes an active component, and the second electronic component includes a passive component.
在本揭露的一實施例中,第二電子元件環繞第一電子元件設置。 In an embodiment of the present disclosure, the second electronic component is disposed around the first electronic component.
在本揭露的一實施例中,導熱密封件包括一體成形的環型結構。 In an embodiment of the present disclosure, the thermally conductive seal includes an integrally formed ring structure.
在本揭露的一實施例中,導熱密封件包括不連續但彼此連接的多個條狀結構,以共同環繞第一電子元件的周圍。 In an embodiment of the present disclosure, the thermally conductive sealing member includes a plurality of discontinuous but connected strip structures to surround the first electronic component together.
在本揭露的一實施例中,導熱密封件的導熱係數大於1W/mK。 In an embodiment of the present disclosure, the thermal conductivity of the thermally conductive seal is greater than 1 W/mK.
在本揭露的一實施例中,導熱密封件的壓縮率小於70%。 In one embodiment of the present disclosure, the compressibility of the thermally conductive seal is less than 70%.
在本揭露的一實施例中,半導體封裝更包括支撐環,其環繞基板的周圍區域。 In an embodiment of the present disclosure, the semiconductor package further includes a supporting ring surrounding the surrounding area of the substrate.
在本揭露的一實施例中,半導體封裝更包括黏著層,其設置於導熱密封件與第二電子元件之間以及導熱密封件與基板之間。 In an embodiment of the present disclosure, the semiconductor package further includes an adhesive layer disposed between the thermally conductive sealing member and the second electronic component and between the thermally conductive sealing member and the substrate.
在本揭露的一實施例中,半導體封裝更包括輔助密封環, 其環繞設置於導熱密封件的周圍。 In an embodiment of the present disclosure, the semiconductor package further includes an auxiliary sealing ring, It is arranged around the heat conducting seal.
基於上述,本揭露的半導體封裝的第一電子元件與第二電子元件彼此並排設置於基板上,導熱密封件環繞第一電子元件並填充於第一電子元件與第二電子元件之間的間隙以及第二電子元件與散熱元件之間的間隙。如此,半導體封裝100便可利用導熱密封件的高壓縮率,使導熱密封件同時填充散熱元件與第一電子元件之間的間隙以及第二電子元件與散熱元件之間的間隙,而不需以不同尺寸的密封件分別填充這兩個厚度不同的間隙。並且,導熱密封件的高導熱率的特性也可降低半導體封裝的熱阻,進而提升散熱效率。
Based on the above, the first electronic component and the second electronic component of the semiconductor package of the present disclosure are arranged side by side on the substrate, the thermally conductive sealing member surrounds the first electronic component and fills the gap between the first electronic component and the second electronic component and The gap between the second electronic component and the heat sink. In this way, the
100:半導體封裝 100: Semiconductor packaging
110:基板 110: Substrate
120:第一電子元件 120: The first electronic component
130:第二電子元件 130: the second electronic component
140:散熱元件 140: cooling element
142:延伸部 142: Extension
150:液態金屬導熱層 150: liquid metal heat conduction layer
160:導熱密封件 160: thermal seal
170:支撐環 170: support ring
180:黏著層 180: Adhesive layer
182:延伸區 182: Extended area
190:輔助密封環 190: Auxiliary sealing ring
圖1是依照本揭露的一實施例的一種半導體封裝的局部剖面示意圖。 FIG. 1 is a schematic partial cross-sectional view of a semiconductor package according to an embodiment of the disclosure.
圖2是依照本揭露的一實施例的一種半導體封裝的部分元件的立體示意圖。 FIG. 2 is a schematic perspective view of some components of a semiconductor package according to an embodiment of the disclosure.
圖3是依照本揭露的一實施例的一種半導體封裝的局部剖面示意圖。 FIG. 3 is a schematic partial cross-sectional view of a semiconductor package according to an embodiment of the disclosure.
圖4是依照本揭露的一實施例的一種半導體封裝的部分元件的立體示意圖。 FIG. 4 is a schematic perspective view of some components of a semiconductor package according to an embodiment of the disclosure.
有關本揭露之前述及其他技術內容、特點與功效,在以下配合參考圖式之各實施例的詳細說明中,將可清楚的呈現。以下實施例中所提到的方向用語,例如:「上」、「下」、「前」、「後」、「左」、「右」等,僅是參考附加圖式的方向。因此,使用的方向用語是用來說明,而並非用來限制本揭露。並且,在下列各實施例中,相同或相似的元件將採用相同或相似的標號。 The aforementioned and other technical contents, features and effects of the present disclosure will be clearly presented in the following detailed descriptions of the embodiments with reference to the drawings. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the attached drawings. Accordingly, the directional terms used are for illustration, not for limitation of the present disclosure. Also, in the following embodiments, the same or similar components will be given the same or similar symbols.
圖1是依照本揭露的一實施例的一種半導體封裝的局部剖面示意圖。圖2是依照本揭露的一實施例的一種半導體封裝的部分元件的立體示意圖。在此須注意的是,圖2及圖4省略繪示了散熱元件140,以更清楚地呈現散熱元件140下方的結構配置。請參照圖1及圖2,半導體封裝100包括基板110、第一電子元件120、第二電子元件130、散熱元件140、液態金屬導熱層150以及導熱密封件160。第一電子元件120及第二電子元件130設置於基板110上。在一實施例中,第一電子元件120與第二電子元件130以並列的方式設置於基板110上。在本實施例中,第一電子元件120可包括中央處理器(CPU)、圖形處理器(GPU)等主動元件,而第二電子元件130則可包括電容、電阻、電感等被動元件。在一實施例中,第二電子元件130的數量可為多個,其分別環繞第一電子元件120而設置。在本實施例中,第二電子元件130可包括多層陶瓷電容器(Multi-layer Ceramic Capacitor,MLCC),但本揭露並不局限於此。
FIG. 1 is a schematic partial cross-sectional view of a semiconductor package according to an embodiment of the disclosure. FIG. 2 is a schematic perspective view of some components of a semiconductor package according to an embodiment of the disclosure. It should be noted here that the
在一些實施例中,散熱元件140設置於第一電子元件120上,並且,散熱元件140可包括延伸至第二電子元件130上方的延伸部142。在一實施例中,散熱元件140可包括熱管、散熱鰭片等散熱元件,用以貼附於第一電子元件120的發熱表面,以利用熱交換的模式來散熱。為了強化散熱元件140的散熱效率,一般會在散熱元件140與第一電子元件120的兩個接合表面之間塗佈導熱材料,以加強熱傳導效率。據此,在本實施例中,液態金屬導熱層150設置於散熱元件140與第一電子元件120之間,並與散熱元件140及第一電子元件120形成熱耦接。在本實施例中,液態金屬導熱層150為液態金屬導熱膏(熱界面材料),其可包括鎵-銦-錫合金等化學組合。一般而言,液態金屬材料的沸點可高達2000℃,具有非常穩定的物理和化學性質,使其在空氣中不易揮發。液態金屬是一種具有黏性的導熱化合物,其在垂直(C平面)方向具有良好的導熱性。因此,液態金屬導熱層150能夠填充兩個接合表面之間的氣隙以降低熱阻及提升散熱效能。
In some embodiments, the
液態金屬導熱層150的設置主要是用以減少散熱元件140及第一電子元件120之間的氣隙。然而,由於液態金屬導熱層150為液態,因而容易溢流至基板110上及/或第一電子元件120的周圍以外的區域進而導致半導體封裝的可靠性及電性短路等問題。因此,在一些實施例中,導熱密封件160用以環繞第一電子元件120並填充於第一電子元件120與第二電子元件130之間的間隙以及第二電子元件130與散熱元件140的延伸部142之間的間
隙,以防止液態金屬導熱層150溢流至導熱密封件160所框圍的區域之外。
The liquid metal
在一實施例中,導熱密封件160可如圖2所示為一體成形的環型結構,在其他實施例中,導熱密封件也可如圖4所示為不連續但彼此連接的條狀結構,以共同環繞第一電子元件120的周圍。在本實施例中,導熱密封件160的材料可包括矽脂、矽膠等具高導熱係數及高壓縮率的密封材。在一實施例中,導熱密封件160的導熱係數約可大於1W/mK,舉例而言,本實施例的導熱密封件160的導熱係數約介於3W/mK至5W/mK之間。在一實施例中,導熱密封件160的壓縮率約可小於70%,舉例而言,本實施例的導熱密封件160的壓縮率約可小於50%。壓縮率是指一個物體對壓力改變造成的相對體積改變的度量,壓縮率越高代表這個物體對壓力改變所造成的相對體積改變越大。如此,本揭露的半導體封裝100使用具有高壓縮率的高導熱密封件160便可使導熱密封件160同時填充散熱元件140與第一電子元件120之間的間隙以及第二電子元件130與散熱元件140的延伸部142之間的間隙,而不需以不同尺寸的密封件分別填充這兩個厚度不同的間隙。並且,導熱密封件160的高導熱率的特性也可降低半導體封裝100的熱阻,進而提升散熱效率。
In one embodiment, the
在一實施例中,半導體封裝100更可包括支撐環170,其環繞基板110的周圍區域,以增加半導體封裝100的結構強度,進而降低半導體封裝100的翹曲。在一實施例中,支撐環170的
材料可包括金屬等硬度較高的材料,其可環繞基板110的周邊,以增強基板110的結構強度,因而能減少因各材料間的熱膨脹係數(Coefficient of Thermal Expansion,CTE)不同而導致的翹曲問題。
In one embodiment, the
在一實施例中,半導體封裝100更可包括黏著層180,其設置於導熱密封件160與第二電子元件130之間以及導熱密封件160與基板110之間,以將導熱密封件160貼附於第二電子元件130與基板110上。具體而言,黏著層180可先貼附於導熱密封件160上,再將導熱密封件160環繞第一電子元件120設置,使其承靠並貼附於第二電子元件130與基板110上。在一實施例中,黏著層180可包括聚醯亞胺薄膜(polyimide(PI)film)。此外,黏著層180可包括延伸區182,其可延伸貼附至支撐環170的上表面。
In one embodiment, the
圖3是依照本揭露的一實施例的一種半導體封裝的局部剖面示意圖。圖4是依照本揭露的一實施例的一種半導體封裝的部分元件的立體示意圖。在此必須說明的是,本實施例的半導體封裝100與前述實施例的半導體封裝100相似,因此,本實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,本實施例不再重複贅述。以下將主要針對本實施例的半導體封裝100與前述實施例的半導體封裝100之間的差異做說明。
FIG. 3 is a schematic partial cross-sectional view of a semiconductor package according to an embodiment of the disclosure. FIG. 4 is a schematic perspective view of some components of a semiconductor package according to an embodiment of the disclosure. It must be noted here that the
在一實施例中,半導體封裝100a更可包括輔助密封環190,
其環繞設置於導熱密封件160a的周圍,以進一步防止液態金屬導熱層150的溢流。在本實施例中,輔助密封環190與導熱密封件160a可以並排的方式設置於基板110上。在一實施例中,輔助密封環190的材料可包括泡棉。在一實施例中,輔助密封環190的導熱係數約可小於導熱密封件160a的導熱係數。舉例而言,本實施例的輔助密封環190的導熱係數約介於0.04W/mK至0.05W/mK之間。在一實施例中,輔助密封環190的壓縮率約可小於導熱密封件160的壓縮率。舉例而言,本實施例的輔助密封環190的壓縮率約可小於70%。當然,本實施例僅用以舉例說明,本揭露並不以此為限。在本實施例中,導熱密封件160a可如圖4所示為不連續但彼此連接的條狀結構,以共同環繞第一電子元件120的周圍。
In one embodiment, the
綜上所述,本揭露的半導體封裝的第一電子元件與第二電子元件彼此並排設置於基板上,導熱密封件環繞第一電子元件並填充於第一電子元件與第二電子元件之間的間隙以及第二電子元件與散熱元件之間的間隙。如此,半導體封裝100便可利用導熱密封件的高壓縮率,使導熱密封件同時填充散熱元件與第一電子元件之間的間隙以及第二電子元件與散熱元件之間的間隙,而不需以不同尺寸的密封件分別填充這兩個厚度不同的間隙。並且,導熱密封件的高導熱率的特性也可降低半導體封裝的熱阻,進而提升散熱效率。
In summary, in the semiconductor package of the present disclosure, the first electronic component and the second electronic component are arranged side by side on the substrate, and the thermally conductive seal surrounds the first electronic component and fills the space between the first electronic component and the second electronic component. The gap and the gap between the second electronic component and the heat dissipation component. In this way, the
100:半導體封裝 100: Semiconductor packaging
110:基板 110: Substrate
120:第一電子元件 120: The first electronic component
130:第二電子元件 130: the second electronic component
140:散熱元件 140: cooling element
142:延伸部 142: Extension
150:液態金屬導熱層 150: liquid metal heat conduction layer
160:導熱密封件 160: thermal seal
170:支撐環 170: support ring
180:黏著層 180: Adhesive layer
182:延伸區 182: Extended area
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111210412U TWM638224U (en) | 2022-09-23 | 2022-09-23 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111210412U TWM638224U (en) | 2022-09-23 | 2022-09-23 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TWM638224U true TWM638224U (en) | 2023-03-01 |
Family
ID=86691104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW111210412U TWM638224U (en) | 2022-09-23 | 2022-09-23 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWM638224U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI864971B (en) * | 2023-08-18 | 2024-12-01 | 華碩電腦股份有限公司 | Electronic assembly and manufacturing method thereof |
-
2022
- 2022-09-23 TW TW111210412U patent/TWM638224U/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI864971B (en) * | 2023-08-18 | 2024-12-01 | 華碩電腦股份有限公司 | Electronic assembly and manufacturing method thereof |
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