TWM636396U - Semiconductor Package Structure - Google Patents

Abstract

A semiconductor packaging structure, comprising a first chip unit and a second chip unit electrically connected to the first chip unit, the first chip unit has at least one semiconductor layer and at least one conductive layer, and the second chip unit There are a plurality of apertures penetrating through the semiconductor layer and the conductive layer, wherein the first chip unit can be electrically connected with a plurality of input-output joint elements through the plurality of apertures.

Description

Semiconductor Package Structure

The present invention relates to a semiconductor packaging structure, in particular to a method in which a chip unit is used as a substrate.

From the perspective of the die-substrate bonding method in today's packaging technology, it can be roughly divided into wire bond (WB), automatic pressure bonding (Tape automatic bonding, TAB), flip chip (Flip chip, FC) packaging methods, if viewed from the substrate pin type, can be roughly divided into pin insertion type (Pin-through-hole, PTH), surface mount technology (Surface mount technology, SMT), peripheral type (Peripheral package) , and array type (Array area), etc. However, as electronic products continue to evolve towards light, thin, short, and small trends, the technology of chip packaging has gradually changed from the early wire bonding type to flip-chip type, and The substrate pin type has also changed from the pin insertion type to the array type (such as: ball grid array package, Ball Grid Array, BGA).

Please refer to FIG. 1 , which illustrates a flip-chip ball grid array package (FC BGA) structure. A die 910 is disposed on a substrate 920, and a plurality of solder balls 991 are used to electrically connect the die 910 to the substrate 920. , the bottom surface of the substrate 920 is provided with a plurality of pins 992 .

Please refer to FIG. 2 , which illustrates a structure of a wire bonded BGA package (Wire bond BGA). A die 810 is disposed on a substrate 820, and a plurality of metal wires 891 are used between the die 810 and the substrate 820. For connection, a plurality of pins 892 are provided on the bottom surface of the substrate 820 .

From the above-mentioned chip packaging technologies, no matter what it is, a substrate (or a lead frame) must be used as a device for carrying the chip, and the chip and the substrate must be connected by solder balls or metal wires. Linking is one of the mainstream methods of chip packaging technology at present.

However, the current chip testing process must wait for the chip to be packaged, and then use the plurality of pins to perform the electrical test of the chip, and it is impossible to perform an electrical test on the chip before packaging, which will cause the chip in a bad state to enter the packaging process. There is a problem that semiconductor packaging costs are wasted.

In view of this, the purpose of the present invention is to provide a semiconductor packaging structure.

The semiconductor packaging structure includes at least a first chip unit, a second chip unit, and a bonding layer unit.

The first chip unit includes at least one semiconductor layer and at least one conductive layer.

The second chip unit is electrically connected to the first chip unit, and the second chip unit includes a plurality of apertures penetrating the second chip unit.

The junction layer unit includes a plurality of output and input junction elements disposed on the junction layer unit.

Wherein, the first chip unit can be electrically connected to the plurality of input-output joint elements through the plurality of apertures.

Another technical means of the present invention is that the above-mentioned first chip unit, the second chip unit and the bonding layer unit are packaged into an integrated circuit module.

Another technical means of the present invention lies in that the area of the above-mentioned second chip unit is larger than the area of the first chip unit.

Another technical means of the present invention lies in that the area of the above-mentioned second chip unit is equal to the area of the first chip unit.

Yet another technical means of the present invention is that the above-mentioned first chip unit and the second chip unit are packaged into an integrated circuit module.

Another technical measure of the present invention lies in that the material of the above-mentioned semiconductor layer is silicon.

Yet another technical measure of the present invention is that the material of the above-mentioned semiconductor layer is gallium arsenide.

The beneficial effects of the present invention are that the first chip unit is tested through the input-input bonding elements, and the first chip unit can be directly cut into a plurality of crystal grains without going through a general packaging procedure, therefore, the cost can be effectively reduced. Packaging and testing costs and reducing the size of the packaged chip area.

The features and technical contents of the relevant patent applications of the present invention will be clearly presented in the following detailed descriptions of the three preferred embodiments with reference to the drawings. Before proceeding with the detailed description, it should be noted that like elements are denoted by the same reference numerals.

Referring to FIG. 3 , a first preferred embodiment of the present invention, the semiconductor package structure includes a first chip unit 11 , a second chip unit 12 , and a bonding layer unit 13 .

The first and second chip units 11, 12 respectively include at least one semiconductor layer 111 and at least one conductive layer 112, and the material of the semiconductor layer 111 is a semiconductor material (such as: silicon (Si), gallium arsenide (GaAs) , should not be limited to this in actual implementation), and the bonding layer unit 13 is provided with a conductive material.

It should be noted that the first wafer unit 11, the second wafer unit 12, and the bonding layer unit 13 are arranged in such a sequence that the second wafer unit 12 is interposed between the first wafer unit 11 and the bonding layer unit 13. bonding, and the area of the second chip unit 12 is greater than or equal to the area of the first chip unit 11, in addition, since the bonding layer unit 13 is provided with conductive material, it is also possible to use the second chip unit 12 The bottom layer is implemented accordingly.

The first and second chip units 11, 12 and the bonding layer unit 13 are made in the way of semiconductor manufacturing process (such as: exposure, oxide layer deposition, etching, development, etc.), and relevant circuit elements are made in it. Due to an application of semiconductor manufacturing process The manufacturing method of the circuit components is not the main feature of the present invention, please refer to the description of the relevant content in the book "Principles of CMOS VLSI Design" written by Neil H. E. Weste and Kamran Eshraghian, etc., and will not repeat them here.

Then, a plurality of apertures 121 are disposed in the second wafer unit 12 , wherein each aperture 121 penetrates the second wafer unit 12 respectively.

Finally, in the bonding layer unit 13 , a plurality of input/output bonding elements 131 (I/O Pads) are made of conductive materials by means of semiconductor manufacturing process, wherein the multiple input/output bonding elements 131 can extend to the bonding layer unit 13 The bottom surface should not be limited to this in actual implementation.

Please refer to FIG. 4 and FIG. 5 , assuming that the first chip unit 11 has n circuit elements CKT1~CKT4...CKTn manufactured by semiconductor process, and each circuit element CKT1~CKT4...CKTn has Its corresponding conductive pins 110, each conductive pin 110 is electrically connected to a corresponding output and input bonding element 131 through a corresponding aperture 121, so that each circuit element CKT1~CKT4...CKTn can pass through its corresponding A set of reference voltages (not shown in the figure) are received on the output-input bonding element 131 .

After the circuit elements in the first chip unit 11 receive the set of reference voltages and complete the test, each circuit element CKT1~CKT4...CKTn in the first chip unit 11 can be obtained through wafer dicing. Since the plurality of circuit elements CKT1~CKT4...CKTn are supported by the second chip unit 12, and transmit or receive signals through the corresponding input and output bonding elements 131, there is no need to go through such as bonding , glue filling and other traditional packaging processes, so the production cost of these circuit components can be reduced.

Referring to Fig. 6, it is a second preferred embodiment of the present invention, the biggest difference between the second preferred embodiment and the first preferred embodiment is: when the bottom layer of the second chip unit 12 is a conductive layer , the conductive layer can be regarded as the bonding layer unit 13, and a plurality of input and output bonding elements are made of conductive material in the conductive layer, that is to say, the bonding layer unit 13 and the second chip 12 can also be integrated The way of molding is not limited to the way of making separately in the first preferred embodiment.

Please refer to FIG. 7, since the first chip unit 11 provided with a plurality of circuit elements CKT1~CKT4...CKTn does not need to be separately arranged on a lead frame or a substrate as in the prior art, therefore, in this preferred implementation In the example, a plurality of first chip units 11 existing in a wafer (Wafer) 10 are matched with a corresponding second chip unit 12, and each first chip unit 12 can be The conductive pin (Pin) of the chip unit 11 is electrically connected to a bonding layer unit 13 having a plurality of input and output bonding elements 131, so if packaging is required, each first chip unit 11 is connected to the corresponding second chip unit 12, and the bonding layer unit 13 can be directly packaged together, and then through the process of wafer dicing, a plurality of crystal grains D1~D4... Dm, in other words, this preferred embodiment can effectively reduce the area of each of the dies D1-D4...Dm having the plurality of circuit elements CKT1-CKT4...CKTn.

The biggest difference between the present model and the prior art is that, after bonding the first chip unit and the second chip unit, the first chip unit can receive a set of reference voltages through the apertures in the second chip units Therefore, unlike the prior art, the wafer is cut into a plurality of dies, and then the dies are placed on a lead frame or a substrate for packaging and testing.

Therefore, compared with the prior art, the present invention integrates the first chip unit, the second chip unit, and the bonding layer unit in the integrated circuit, so that the first and second chips can be connected via the input-input bonding element. The unit is tested and used, and the first chip unit can be directly cut into Therefore, compared with the prior art, the cost of packaging and testing can be effectively reduced and the size of the area after chip packaging can be reduced, so the purpose of the present invention can indeed be achieved.

But the above are only three preferred embodiments of the present invention, and the scope of implementation of the present invention cannot be limited with this, that is, all simple equivalent changes and Modifications all still belong to the scope covered by the patent for this model.

CKT1: circuit element CKT2: circuit components CKT3: circuit components CKT4: circuit components CKTn: circuit element D1: grain D2: grain D3: grain D4: grain Dm: grain 11: The first wafer unit 111: semiconductor layer 112: conductive layer 110: Conductive pin 12: Second wafer unit 121: Aperture 13:Joint layer unit 131: output input joint element 10:Wafer 810: grain 820: Substrate 891: metal pull wire 892: Pin 910: grain 920: Substrate 991: solder ball 992: Pin

FIG. 1 is a schematic side view of a conventional flip chip ball grid array package; FIG. 2 is a schematic side view of a conventional wire-bonded solder ball grid array package; 3 is a first preferred embodiment of the present invention, illustrating a schematic side view of a semiconductor packaging structure; Fig. 4 is a schematic side view illustrating the first preferred embodiment, after obtaining a plurality of circuit elements and input-input junction elements through semiconductor manufacturing; Fig. 5 is a schematic diagram illustrating the top view of the first preferred embodiment, after the majority of circuit elements and input-input bonding elements are obtained through semiconductor manufacturing; 6 is a second preferred embodiment of the present invention, illustrating a schematic side view of a semiconductor packaging structure; and FIG. 7 is a third preferred embodiment of the present invention, illustrating a schematic top view of a semiconductor package structure.

CKT1: circuit element

CKT2: circuit components

CKT3: circuit components

CKT4: circuit components

11: The first wafer unit

110: Conductive pin

12: Second wafer unit

121: Aperture

13:Joint layer unit

131: output input joint element

Claims (7)

A semiconductor packaging structure, comprising: at least one first chip unit, including at least one semiconductor layer, and at least one conductive layer; a second chip unit electrically connected to the first chip unit, which includes a plurality of apertures penetrating through the second chip unit; and A bonding layer unit, including a plurality of output and input bonding elements disposed on the bonding layer unit; Wherein, the first chip unit can be electrically connected to the plurality of input-output joint elements through the plurality of apertures. The semiconductor package structure as claimed in claim 1, wherein the first chip unit, the second chip unit and the bonding layer unit are packaged into an integrated circuit module. The semiconductor package structure according to claim 1, wherein the area of the second chip unit is larger than the area of the first chip unit. The semiconductor package structure according to claim 1, wherein the area of the second chip unit is equal to the area of the first chip unit. The semiconductor package structure according to claim 1, wherein the first chip unit and the second chip unit are packaged into an integrated circuit module. The semiconductor package structure according to claim 1, wherein the material of the semiconductor layer is silicon. The semiconductor package structure according to claim 1, wherein the material of the semiconductor layer is gallium arsenide.

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