TWM631056U - Transistor - Google Patents

Abstract

A transistor includes a substrate, a channel, a gate dielectric layer, a gate electrode, a source electrode and a drain electrode. The channel is formed on the surface of the substrate, and has a buffer layer, a first semiconductor layer formed on the buffer layer and a second semiconductor layer formed on the first semiconductor layer; wherein, the buffer layer and the first semiconductor layer are made of a GaN The main semiconductor material is formed, the surface of the first semiconductor layer has a plurality of micro-holes, and the second semiconductor layer fills the micro-holes and is made of GaN, Ga ₂ O ₃ by atomic layer deposition technology and etching treatment in sequence or GaO _x N _y . The gate dielectric layer is formed on the second semiconductor layer; the gate electrode is formed on the gate dielectric layer; the source electrode is formed on one side of the channel and connects the channel; the drain electrode is formed on the other side opposite to the side of the channel and connect the channel.

Description

Transistor

The present invention relates to a transistor, especially a transistor with low leakage current.

The first generation of semiconductor silicon (Si) makes it suitable for power semiconductor devices based on its energy gap of 1.17 eV. However, with the continuous evolution of IC process technology, the continuous thinning and miniaturization of semiconductor devices, and the demand for logic operations of ICs, related technology industries have also successively developed gallium arsenide (GaAs) and indium phosphide (InP) and other second-generation semiconductors, and third-generation semiconductors such as silicon carbide (SiC) and gallium nitride (GaN), until recent years, the industry has also paid attention to gallium oxide (Ga ₂ O ₃ ) with an energy gap of up to 4.9 eV, a fourth-generation semiconductor semiconductor.

For related industries in the technical field, the challenges currently faced in fabricating MOSFETs on sapphire substrates or SOI substrates are the thickness difference and lattice mismatch caused by the GaN buffer layer. (lattice mismatch), surface defects (eg, surface micro-bumps, micro-dimples) and vacancies.

Referring to FIG. 1 and FIG. 2, for example, the invention patent case of the Republic of China No. TWI715311 (hereinafter referred to as the previous case 1) discloses a gold oxide silicon semiconductor field effect transistor (Si MOSFET) with a wide energy gap group III and V drain. 1 and how to make it. In the previous case 1, a GaN drain electrode 12 is selectively grown at the 100-nanometer-scale hole 100 of the (111) crystal plane of a silicon wafer 11 of a SOI substrate 10 by using metal-organic chemical vapor deposition technology (MOCVD). Single crystal hexagonal gallium nitride (h-GaN) can be grown from above the (111) crystal plane of the silicon wafer 11, and its dislocation during the crystallization process can end in the hundred nanometer-scale hole 100 When h-GaN is merged in the middle of the 100-nanometer-scale hole 100, a high-crystallinity cubic gallium nitride (c-GaN) can be obtained. On the one hand, the former case 1 solves the aforementioned problem of lattice mismatch, and on the other hand, the breakdown voltage of the silicon semiconductor high field effect transistor 1 is improved by the GaN drain electrode 12 .

Although the former case 1 can solve the aforementioned lattice mismatch problem; however, the thickness difference caused by MOCVD film formation (eg, the micro-bumps/bumps between the GaN drain electrode 12 and the silicon wafer 11 shown in FIG. 2 Thickness difference) is also the main factor affecting the leakage current and breakdown voltage of the field effect transistor.

It can be seen from the above description that improving the thickness difference problem caused by MOCVD film formation to solve the leakage current problem of the transistor is a subject to be solved by the relevant technical personnel in the technical field of this case.

Therefore, the purpose of the present invention is to provide a transistor which can improve the problem of thickness difference caused by MOCVD film formation and reduce the problem of leakage current.

Therefore, the transistor of the present invention includes a substrate, a channel, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The channel is formed on a surface of the substrate and has a buffer layer, a first semiconductor layer formed on the buffer layer and a second semiconductor layer formed on the first semiconductor layer, wherein the buffer layer and the The first semiconductor layer is composed of a GaN-based semiconductor material, a surface of the first semiconductor layer has a plurality of micro-holes, and the second semiconductor layer fills the micro-holes and sequentially passes through an atomic layer GaN, Ga ₂ O ₃ or GaO _x N _y produced by the deposition technique (atomic layer deposition, ALD) and an etching process. The gate dielectric layer is formed on the second semiconductor layer of the channel. The gate is formed on the gate dielectric layer. The source is formed on one side of the channel and connected to the channel. The drain is formed on the opposite side of the side of the channel and is connected to the channel.

The effect of the present invention lies in that the second semiconductor layer is made of GaN, Ga ₂ O ₃ or GaO _x N _y by atomic layer deposition technology and etching treatment in sequence, which can fill the surface of the first semiconductor layer due to epitaxial growth. The resulting micro-voids can also repair Ga vacancies on the surface of the second semiconductor layer to achieve nanometer-level polishing, thereby improving the leakage current problem.

A manufacturing method of an embodiment of the transistor of the present invention includes the following steps: a step (a), a step (b), a step (c), a step (d), a step (e), a step (f), a step (g), and a step (h).

Referring to FIG. 3 , in step (a), a buffer layer (not shown) and a first semiconductor layer 31 are sequentially epitaxially grown on a surface of a substrate 2 by MOCVD. The buffer layer and the first semiconductor layer 31 are made of a GaN-based semiconductor material, and a surface of the first semiconductor layer 31 has a plurality of MOCVD micro-bumps 311 and a plurality of micro-holes 312 . The substrate 2 suitable for this embodiment of the present invention is a substrate selected from the group consisting of sapphire, silicon, silicon carbide (SiC), and SOI. In this embodiment of the present invention, the substrate 2 is a sapphire substrate, the buffer layer and the first semiconductor layer 31 are made of GaN, and the thicknesses of the buffer layer and the first semiconductor layer 31 are each between 0.1 nm and 50 nm. between nm and 700 μm to 2000 μm, but not limited thereto.

Referring to FIG. 4 , the step (b) is to planarize the first semiconductor layer 31 to remove the micro-bumps 311 on the surface of the first semiconductor layer 31 and leave the micro-holes on the surface of the first semiconductor layer 31 Cave 312. Preferably, the planarization in step (b) of the method for fabricating the transistor of this embodiment of the present invention is to apply a chemical-mechanical polishing (CMP) technique to the first semiconductor layer 31 .

Referring to FIG. 5 , in step (c), a second semiconductor layer 32 is grown on the surface of the first semiconductor layer 31 in step (b) by an ALD technique to fill the micro-cavities 312 . The second semiconductor layer 32 is composed of Ga and at least one element selected from the group consisting of: O and N; wherein, a surface of the second semiconductor layer 32 has a surface that is not fully formed during the implementation of the ALD technology The Ga vacancy 321 and the vacancy of at least one of the aforementioned elements formed by the reaction precursor (precursor) are formed (see FIG. 6 , such as the N vacancy 322 ). In this embodiment of the present invention, the second semiconductor layer 32 is made of GaN. Although the embodiment of the present invention takes the second semiconductor layer 32 made of GaN as an example for description, it is not limited thereto. It should be noted that the second semiconductor layer 32 is used as a channel of the transistor when it is finally fabricated into a transistor; therefore, the second semiconductor layer 32 can also be made of Ga ₂ O ₃ with a larger energy gap than GaN constituted.

Referring to FIG. 6 again, the step (d) is to apply an etching process containing an etchant 8 to the second semiconductor layer 32 of the step (c), so as to repair the vacancy on the surface of the second semiconductor layer 32 (eg, The Ga vacancies 321 and N vacancies 322 in this embodiment are used to planarize the surface of the second semiconductor layer 32 and remove surface defects on the surface of the second semiconductor layer 32 ; wherein the etchant 8 contains halogen element and at least one of the aforementioned elements. The halogen element suitable for the etchant 8 of the present invention is selected from F or Cl. Preferably, the etching treatment in step (d) is selected from a wet etching method or a dry etching method. More preferably, the etching treatment in step (d) is dry etching. In this embodiment of the present invention, the dry etching method implements atomic layer etching (ALE) technology. The etchant 8 suitable for the ALE technique of this step (d) of the present invention is a gas molecule selected from the group consisting of: NF ₃ , and POCl ₃ . In this embodiment of the present invention, the etchant 8 is illustrated by taking NF ₃ gas molecules as an example, but it is not limited thereto.

As shown in FIG. 6 , in detail, the second semiconductor layer 32 of step (d) is placed in an ALE reaction chamber (not shown) for implementation, when the reactant 8 (NF ₃ gas molecules) is introduced into During the ALE reaction chamber, the fluorine atoms in the NF ₃ gas molecules are dissociated into anions (3F ⁻ ), and the anions (3F ⁻ ) are converted into adatoms (that is, Ga vacancies 321 ) on the surface of the second semiconductor layer 32 A nano-scale by-product (GaF ₃ ) 80 is synthesized, and then the nano-scale by-product (GaF ₃ ) 80 is removed from the second semiconductor by argon (Ar, not shown) introduced into the ALE chamber The surface of the layer 32 is desorbed and taken out of the ALE reaction chamber, and the dissociated N can also repair the N vacancy 322 located on the surface of the second semiconductor layer 32 to complete one cycle of ALE. It can be seen from this that the etching process performed in the step (d) of this embodiment of the present invention can achieve nano-level polishing, which can not only flatten the surface of the second semiconductor layer 32 but also remove the second semiconductor layer. Surface defects of layer 32 to improve the problem of shallow impurity. Therefore, after performing the step (d), the second semiconductor layer 32 has an average surface roughness (Ra) of less than 10 nm. In this embodiment of the present invention, the average surface roughness (Ra) of the second semiconductor layer 32 is about 0.31 nm as shown in FIG. 7 and FIG. 8 .

More specifically, each ALE cycle described in this step (d) sequentially includes the following sub-steps: a step (d1), a step (d2), a step (d3), and a step (d4).

This sub-step (d1) is to implement a surface treatment procedure. Further, an oxygen body is introduced into the ALE reaction chamber (not shown) to release the aforementioned oxygen gas through a high voltage to become an oxygen plasma, so that the surface of the second semiconductor layer 32 is oxidized.

This sub-step (d2) is to perform an etchant soaking process. Further, NF _{3 gas molecules are introduced into the ALE reaction chamber to dissociate the aforementioned NF 3 gas} molecules through a high voltage, so that the F atoms are electrolyzed into 3F ^- so that 3F ^- and the Ga on the surface of the second semiconductor layer 32 The nanoscale by-product (GaF ₃ ) 80 was synthesized by vacancy 321 .

This sub-step (d3) is to carry out a desorption procedure. Further, Ar is introduced into the ALE reaction chamber to dissociate the aforementioned Ar into Ar plasma through a high voltage, so that the nanoscale by-product (GaF ₃ ) 80 is desorbed from the surface of the second semiconductor layer 32 .

This sub-step (d4) is to implement a purge procedure. Further, Ar is introduced into the ALE reaction chamber to remove the nanoscale by-product (GaF ₃ ) 80 desorbed from the surface of the second semiconductor layer 32 and take it out of the ALE reaction chamber.

Preferably, an electrode output power, a reaction time and a cycle number during the implementation of the sub-step (d1), the sub-step (d2), and the sub-step (d3) are respectively between 100 W and 300 W. , between 5 seconds and 10 seconds, and between 25 and 100 times.

Referring to FIG. 9 , in step (e), a channel 3 is defined for the buffer layer, the first semiconductor layer 31 and the second semiconductor layer 32 . Specifically, the step (e) is to define the channel 3 through lithography, etching and other procedures. The means of defining the channel 3 is not the technical focus of the present invention, and will not be repeated here. From the detailed description of the ALE described in the step (d) above, it can be known that the ALE can enable the second semiconductor layer 32 to achieve nano-level polishing. Therefore, preferably, the second semiconductor layer 32 of the channel 3 has a thickness of less than 500 nm, and the second semiconductor layer 32 of the channel 3 has an average surface roughness of less than 10 nm. In this embodiment of the present invention, the thickness of the second semiconductor layer 32 is about 100 nm, and as described above, the average surface roughness (Ra) is about 0.31 nm.

Referring to FIG. 10 , the step (f) is to form a gate dielectric layer 4 on the channel 3 .

Referring to FIG. 11 , the step (g) is to form a gate 5 on the gate dielectric layer 4 .

Referring to FIG. 12 , in step (h), a source electrode 6 and a drain electrode 7 are respectively formed on one side of the channel 3 and the other side opposite to the side.

From the detailed description of the manufacturing method of this embodiment of the present invention, it can be known that the transistor produced by the manufacturing method of this embodiment of the present invention is as shown in FIG. The gate dielectric layer 4 , the gate 5 , the source 6 , and the drain 7 .

The channel 3 has the buffer layer (not shown), a first semiconductor layer 31 formed on the buffer layer, and a second semiconductor layer 32 formed on the first semiconductor layer 31 , wherein the buffer layer and the first semiconductor layer 32 are formed on the buffer layer. The semiconductor layer 31 is made of GaN-based semiconductor material, the surface of the first semiconductor layer 31 has the micro-holes 312, the second semiconductor layer 32 fills the micro-holes 312 and is sequentially processed by ALD GaN, or Ga ₂ O ₃ , or GaO _x N _y made with the ALE shown in FIG. 6 .

The gate dielectric layer 4 is formed on the second semiconductor layer 32 of the channel 3 ; the gate 5 is formed on the gate dielectric layer 4 . The source electrode 6 is formed on one side of the channel 3 and is connected to the channel 3 . The drain 7 is formed on the other side opposite to the side of the channel 3 and is connected to the channel 3 .

To sum up, the transistor of the present invention can not only improve the thickness difference problem caused by MOCVD, but also the subsequent implementation of ALD and ALE, etc., can make up for the first problem. The micro-holes 312 on the surface of the semiconductor layer 31 due to MOCVD can solve the problem of leakage current, and the Ga vacancies 321 on the surface of the second semiconductor layer 32 can also be repaired to achieve a nano-level polishing effect, thereby solving the problem of shallow impurities. It can indeed achieve the purpose of this new model.

However, the above are only examples of the present invention, which should not limit the scope of implementation of the present invention. Any simple equivalent changes and modifications made according to the scope of the patent application for this new model and the contents of the patent specification are still within the scope of the present invention. within the scope of this patent.

2: Substrate 3: Channel 31: The first semiconductor layer 311: Micro bump 312: Micropores 32: Second semiconductor layer 321:Ga vacancy 322:N vacancies 4: gate dielectric layer 5: Gate 6: Source 7: Drain 8: Etchant 80: By-products

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: FIG. 1 is a schematic front view illustrating the gold-oxide-silicon field effect transistor with wide energy gap group III and V drain disclosed by the Republic of China Patent No. TWI715311; FIG. 2 is a scanning electron microscope (SEM) image illustrating surface defects of the gold oxide silicon semiconductor field effect transistor of FIG. 1; FIG. 3 is a schematic front view illustrating a step (a) of a manufacturing method of an embodiment of the transistor of the present invention; 4 is a schematic front view illustrating a step (b) of the manufacturing method of this embodiment of the present invention; 5 is a schematic front view illustrating a step (c) of the manufacturing method of this embodiment of the present invention; 6 is a schematic front view illustrating a step (d) of the manufacturing method of this embodiment of the present invention; 7 is an atomic force microscope (AFM) image diagram, illustrating the average surface roughness (Ra) of a second semiconductor layer obtained by step (d) of the manufacturing method of this embodiment of the present invention; 8 is an AFM stereoscopic image diagram illustrating the average surface roughness (Ra) stereoscopic image obtained by step (d) of the manufacturing method of the embodiment of the present invention; 9 is a schematic front view illustrating a step (e) of the manufacturing method of this embodiment of the present invention; 10 is a schematic front view illustrating a step (f) of the manufacturing method of this embodiment of the present invention; 11 is a schematic front view illustrating a step (g) of the manufacturing method of the embodiment of the present invention; and FIG. 12 is a schematic front view illustrating a step (h) of the fabrication method of the embodiment of the present invention and illustrating the final fabricated transistor.

2: Substrate

3: Channel

31: The first semiconductor layer

312: Micropores

32: Second semiconductor layer

4: gate dielectric layer

5: Gate

6: Source

7: Drain

Claims (3)

A transistor, comprising: a substrate; a channel formed on a surface of the substrate and having a buffer layer, a first semiconductor layer formed on the buffer layer and a first semiconductor layer formed on the first semiconductor layer Two semiconductor layers, wherein the buffer layer and the first semiconductor layer are made of a GaN-based semiconductor material, a surface of the first semiconductor layer has a plurality of micro holes, and the second semiconductor layer fills the micro holes the hole is GaN, Ga ₂ O ₃ or GaO _x N _y made by an atomic layer deposition technique and an etching process in sequence; a gate dielectric layer is formed on the second semiconductor layer of the channel; a gate formed on the gate dielectric layer; a source formed on one side of the channel and connected to the channel; and a drain formed on the other side opposite the side of the channel and connected the channel. The transistor of claim 1, wherein the second semiconductor layer of the channel has a thickness of 500 nm or less. The transistor of claim 2, wherein the second semiconductor layer of the channel further has an average surface roughness below 10 nm.

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