TWM627466U - Multi-chip stacked package structure - Google Patents

Abstract

A multi-chip stack packaging structure includes a substrate, a first chip, a first wire, a dummy chip, an adhesive layer, a second chip, a second wire and a packaging structure. The substrate has an upper surface and a lower surface, the first wafer has an active surface and a back surface, and the back surface of the first wafer is disposed on the upper surface of the substrate facing down, and the first wire is electrically connected to the active surface of the first wafer and the upper surface of the substrate, the dummy chip has a front and a back side, the back side is arranged on the upper surface of the substrate, the adhesive layer is arranged on the active surface of the first chip and the front side of the dummy chip, and the second chip is arranged on the adhesive layer, through the adhesive layer The second chip is fixed on the active surface of the first chip and the front surface of the dummy chip, the second wire is electrically connected to the upper surface of the second chip and the substrate, and the package structure is arranged above the substrate to cover the part of the substrate a surface, a first wire, a second wire, and a second wafer.

Description

Multi-die stacked package structure

The present invention provides a chip package structure, in particular a multi-chip stack package structure.

Small-sized IC packaging units are generally constructed on a single matrix substrate in a batch manner. The matrix substrate defines a plurality of packaging areas in advance, and each packaging area is used to construct a packaging unit. After the encapsulation glue process is completed, a singulation process can be performed to divide the package unit aggregate structure constructed on the matrix substrate into individual package units. Package units manufactured in this way include, for example, Thin & Fine Ball Grid Array (TFBGA) package units, Quad Flat No-lead (QFN) package units, and the like.

Currently packaged in multi-chip products, in addition to stacking multi-chips to increase the capacity of the storage function, heterogeneous chips such as encryption chips and wireless communication chips will also be expanded. However, the fixed product size requires stacking of various sizes of chips. The current design also needs to meet the For the limitation of the large chip on the bottom and the small chip on the top, or staggered stacking, but the staggered structure or the stacked structure of different sizes is easy to cause the entire structure to collapse due to the bearing pressure above during wire bonding, so that the process needs to be reworked. or chip damage.

Therefore, how to propose a multi-chip stacked package structure that can effectively improve the shortcomings of the prior art has become an important issue.

In order to solve the above-mentioned requirements, the purpose of the present invention is to provide a multi-chip stacked packaging structure, which can increase the stability of the overall packaging structure through the supporting application of the dummy chips.

According to the above purpose, the present invention mainly proposes a multi-chip stack packaging structure, including: a substrate, a first chip, a first metal wire, a dummy chip, an adhesive layer, a second chip, a second metal wire, and a package body. The substrate has an upper surface and a lower surface, the first wafer has an active surface and a back surface, the back surface of the first wafer is disposed on the upper surface of the substrate, and the first metal wire is electrically connected to the active surface of the first wafer and the substrate The upper surface of the dummy wafer has a front side and a back side, and the back side of the dummy wafer is arranged on the upper surface of the substrate, the adhesive layer is arranged on the active surface of the first wafer and the front side of the dummy wafer, and the second wafer is arranged on the adhesive layer , the second chip is fixed on the active surface of the first chip and the front surface of the dummy chip by the adhesive layer, the second metal wire is electrically connected to the second chip and the upper surface of the substrate, and the package body is arranged above the substrate for A part of the upper surface of the substrate, the first metal wire, the second metal wire and the second chip are covered.

According to the above purpose, the present invention further proposes a multi-chip stack package structure, comprising: a substrate, a first chip, a first metal wire, a second chip, a second metal wire, a dummy chip, an adhesive layer, a third chip, and a third metal Wires and packages. The substrate has an upper surface and a lower surface, the first wafer has an active surface and a back surface, the back surface of the first wafer is disposed on the upper surface of the substrate, and the first metal wire is electrically connected to the active surface of the first wafer and the substrate The upper surface of the third wafer has a top surface and a bottom surface, and the bottom surface of the third wafer is disposed on the upper surface of the substrate, and the third metal wire is electrically connected to the top surface of the third wafer and the upper surface of the substrate. The wafer has a front side and a back side, and the back side of the dummy wafer is arranged on the upper surface of the substrate, the adhesive layer is arranged on the active surface of the first wafer, the top surface of the third wafer and the front side of the dummy wafer, and the second wafer is arranged on the front side of the dummy wafer. On the adhesive layer, the second chip is fixed on the active surface of the first chip, the top surface of the third chip and the front surface of the dummy chip by the adhesive layer, and the second metal wire is electrically connected to the upper surface of the second chip and the substrate, The package body is arranged above the substrate and is used for covering a part of the upper surface of the substrate, the first metal wire, the second metal wire, the third metal wire and the second chip.

According to the above purpose, the present invention further proposes a multi-chip stack packaging structure, which includes: a substrate, a first chip, a first metal wire, a dummy chip, an adhesive layer, a second chip, a second metal wire, and a package body. The substrate has an upper surface and a lower surface, the first wafer has an active surface and a back surface, the back surface of the first wafer is disposed on the upper surface of the substrate, and the first metal wire is electrically connected to the active surface of the first wafer and the substrate The adhesive layer is arranged on the active surface of the first chip, the second chip is arranged on the adhesive layer, the second chip is fixed on the active surface of the first chip by the adhesive layer, and the second metal wire is electrically connected The second chip and the upper surface of the substrate, the dummy chips are respectively arranged on both sides of the first chip and the upper surface of the substrate, the package body is arranged above the substrate, and is used to cover part of the upper surface of the substrate, the dummy chip, the first A metal wire, a second metal wire and a second chip.

The advantages and features of the present invention and the methods for achieving the same will be more readily understood with reference to the more detailed description of the exemplary embodiments and the accompanying drawings. However, the present creations may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. It should be noted that, in the drawings of the present invention, a cross-sectional view is used to show the stacked structure between the chips, so the plurality of electrical connection terminals, metal wires and electrical connection elements on the active surface 201 of the chip in the drawings , all only show one side of the cross-section, not only a single electrical connection terminal, metal wires and electrical connection elements, which will be explained first.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a first embodiment of a multi-chip stacked package structure. As shown in FIG. 1 , the multi-chip stack package structure of the present invention includes a substrate 10 , a first chip 20 , a first metal wire 21 , a dummy chip 50 , an adhesive layer 60 , a second chip 30 , a second metal wire 31 and a package body 70. The substrate 10 has an upper surface 101 and a lower surface 102, the upper surface 101 of the substrate 10 is configured with electrical connection lines (not shown in the figure), and the lower surface 102 of the substrate 10 is configured with electrical connection terminals ( (not shown in the figure), and the lines of the upper surface 101 are electrically connected to the terminals of the lower surface 102 . The first wafer 20 has an active surface 201 and a back surface 202 , the back surface 202 of the first wafer 20 is disposed on the upper surface 101 of the substrate 10 downward, and a plurality of bonding pads 90 are disposed on the active surface 201 of the first wafer 20 . Next, using a wire bonding process, one end of the plurality of first metal wires 21 is electrically connected to the pads 90 on the active surface 201 of the first chip 20 , and the other end of the first metal wires 21 is electrically connected to the substrate 10 Electrical connection lines (not shown in the figure) on the upper surface 101 of the . Then, a dummy wafer 50 is provided, which has a front side 501 and a back side 502, and the back side 502 of the dummy wafer 50 is disposed on the upper surface 101 of the substrate 10 facing downward, wherein the height of the dummy wafer 50 is equivalent to the height of the first wafer 20, The dummy chip 50 can be a silicon chip, however, the material of the dummy chip 50 is not limited in the present invention. Next, an adhesive layer 60 is provided, especially a FOW (Film Over Wire) adhesive that can embed metal components, and the adhesive layer 60 in a colloidal state is covered and disposed on the active surface 201 of the first chip 20 and the dummy chip 50 On the front side 501 of the first metal wire 21 , the adhesive layer 60 in a colloidal state is formed to cover the first metal wire 21 . Then, after the adhesive layer 60 is cured, the second wafer 30 is disposed on the adhesive layer 60 . Next, using a wire bonding process, one end of the plurality of second metal wires 31 is electrically connected to the pads 90 on the second chip 30 , and the other end of the second metal wires 31 is electrically connected to the upper surface 101 of the substrate 10 . the electrical connection circuit (not shown in the figure). Finally, an encapsulant is used to form a package body 70 , wherein the package body 70 is disposed above the substrate 10 and covers part of the upper surface 101 of the substrate 10 , the first metal wires 21 , the second metal wires 31 and the second chip 30. It should be noted that, after the encapsulation process is completed, a plurality of electrical connection elements 80 are formed on the plurality of electrical connection terminals on the lower surface 102 of the substrate 10 , wherein the electrical connection elements 80 may be a kind of The solder ball can be a C4 standard solder ball. Since the formation method and the function of the electrical connection element 80 are the same as those in the prior art, they are not the main technical features of this creation, so they will not be described further.

Next, please continue to refer to FIG. 1 . In another embodiment, the multi-chip stacked package structure of the present invention includes a substrate 10 , a first chip 20 , a first metal wire 21 , a dummy chip 50 , an adhesive layer 60 , and a second chip 30 , the second metal wire 31 and the package body 70 . The substrate 10 has an upper surface 101 and a lower surface 102, the upper surface 101 of the substrate 10 is configured with electrical connection lines (not shown in the figure), and the lower surface 102 of the substrate 10 is configured with electrical connection terminals ( (not shown in the figure), and the lines of the upper surface 101 are electrically connected to the terminals of the lower surface 102 . In addition, the lower surface 102 of the substrate 10 also has a plurality of electrical connection elements 80 , wherein the electrical connection elements 80 on the lower surface 102 of the substrate 10 are solder balls. The first wafer 20 is a functional wafer, which has an active surface 201 and a back surface 202 , and the back surface 202 of the first wafer 20 is disposed on the upper surface 101 of the substrate 10 facing downward, and the active surface 201 of the first wafer 20 is configured with a A plurality of solder pads 90 . Next, using a wire bonding process, one end of the plurality of first metal wires 21 is electrically connected to the pads 90 on the active surface 201 of the first chip 20 , and the other end of the first metal wires 21 is electrically connected to the substrate 10 Electrical connection lines (not shown in the figure) on the upper surface 101 of the . Then, a dummy wafer 50 is provided, which has a front side 501 and a back side 502, and the back side 502 of the dummy wafer 50 is disposed on the upper surface 101 of the substrate 10 facing downward, wherein the height of the dummy wafer 50 is equivalent to the height of the first wafer 20, The dummy chip 50 can be a silicon chip, however, the material of the dummy chip 50 is not limited in the present invention. Next, an adhesive layer 60 is provided, especially a FOW (Film Over Wire) adhesive that can embed metal components, and the adhesive layer 60 formed in a colloidal state is covered and disposed on the active surface 201 of the first wafer 20 and the dummy wafer 50 . On the front side 501 , the first metal wire 21 is covered by the adhesive layer 60 formed in a colloidal state. Then, after the adhesive layer 60 is cured, the second wafer 30 is disposed on the adhesive layer 60 , wherein the second wafer 30 is a semiconductor die. Next, using a wire bonding process, one end of the plurality of second metal wires 31 is electrically connected to the pads 90 on the second chip 30 , and the other end of the second metal wires 31 is electrically connected to the upper surface 101 of the substrate 10 . the electrical connection circuit (not shown in the figure). Finally, an encapsulant is used to form a package body 70 , wherein the package body 70 is disposed above the substrate 10 and covers part of the upper surface 101 of the substrate 10 , the first metal wires 21 , the second metal wires 31 and the second chip 30. It should be noted that, after the encapsulation process is completed, a plurality of electrical connection elements 80 are formed on the plurality of electrical connection terminals on the lower surface 102 of the substrate 10 , wherein the electrical connection elements 80 may be a kind of The solder ball can be a C4 standard solder ball. Since the formation method and the function of the electrical connection element 80 are the same as those in the prior art, they are not the main technical features of this creation, so they will not be described further. In the present invention, the dummy chips 50 are used as supporting applications, and can be arranged arbitrarily to eliminate the restriction of large-sized chips below and small-sized chips above, and increase the stability of the overall multi-chip stacked package structure.

Please refer to FIG. 2 again. FIG. 2 is a schematic diagram of a second embodiment of the multi-chip stacked package structure of the present invention. As shown in FIG. 2 , the multi-chip stack package structure of the present invention includes a substrate 10 , a first chip 20 , a first metal wire 21 , a second chip 30 , a second metal wire 31 , a dummy chip 50 , an adhesive layer 60 , and a third The chip 40 , the third metal wires 41 and the package body 70 . The substrate 10 has an upper surface 101 and a lower surface 102, the upper surface 101 of the substrate 10 is configured with electrical connection lines (not shown in the figure), and the lower surface 102 of the substrate 10 is configured with electrical connection terminals ( (not shown in the figure), and the lines of the upper surface 101 are electrically connected to the terminals of the lower surface 102 . The first wafer 20 has an active surface 201 and a back surface 202 , the back surface 202 of the first wafer 20 is disposed on the upper surface 101 of the substrate 10 downward, and a plurality of bonding pads 90 are disposed on the active surface 201 of the first wafer 20 . The third wafer 40 has a top surface 401 and a bottom surface 402 , and the bottom surface 402 of the third wafer 40 is disposed on the upper surface 101 of the substrate 10 with the bottom surface 402 facing downward, and a plurality of bonding pads 90 are disposed on the top surface 401 of the third wafer 40 . . Next, using a wire bonding process, one end of the plurality of first metal wires 21 is electrically connected to the pads 90 on the active surface 201 of the first chip 20, and one end of the plurality of third metal wires 41 is electrically connected to the third The bonding pads 90 on the top surface 401 of the chip 40 electrically connect the other ends of the first metal wires 21 and the other ends of the third metal wires 41 to electrical connection lines (not shown) on the upper surface 101 of the substrate 10 in the picture). Then, a dummy wafer 50 is provided, which has a front side 501 and a back side 502, and the back side 502 of the dummy wafer 50 is disposed on the upper surface 101 of the substrate 10 facing downward, wherein the height of the dummy wafer 50 is equivalent to the height of the first wafer 20, The dummy chip 50 can be a silicon chip, however, the material of the dummy chip 50 is not limited in the present invention. Next, an adhesive layer 60 is provided, especially a FOW (Film Over Wire) adhesive that can embed metal components, and the adhesive layer 60 formed in a colloidal state is covered and disposed on the active surface 201 of the first wafer 20 and the third wafer 40 On the top surface 401 of the dummy wafer 50 and the front surface 501 of the dummy chip 50 , the first metal wire 21 and the third metal wire 41 are covered by the glue layer 60 in a colloidal state. Then, after the adhesive layer 60 is cured, the second wafer 30 is disposed on the adhesive layer 60 , wherein the second wafer 30 is a semiconductor die. Next, using a wire bonding process, one end of the plurality of second metal wires 31 is electrically connected to the pads 90 on the second chip 30 , and the other end of the second metal wires 31 is electrically connected to the upper surface 101 of the substrate 10 . the electrical connection circuit (not shown in the figure). Finally, an encapsulant is used to form a package body 70 , wherein the package body 70 is disposed above the substrate 10 and covers part of the upper surface 101 of the substrate 10 , the first metal wires 21 , the second metal wires 31 , and the third conductors The metal wires 41 and the second wafer 30 . It should be noted that, after the encapsulation process is completed, a plurality of electrical connection elements 80 are formed on the plurality of electrical connection terminals on the lower surface 102 of the substrate 10 , wherein the electrical connection elements 80 may be a kind of The solder ball can be a C4 standard solder ball. Since the formation method and the function of the electrical connection element 80 are the same as those in the prior art, they are not the main technical features of this creation, so they will not be described further.

Next, please continue to refer to FIG. 2 . In another embodiment, the multi-chip stacked package structure of the present invention includes a substrate 10 , a first chip 20 , a first metal wire 21 , a second chip 30 , a second metal wire 31 , a dummy The chip 50 , the adhesive layer 60 , the third chip 40 , the third metal wire 41 and the package body 70 . The substrate 10 has an upper surface 101 and a lower surface 102, the upper surface 101 of the substrate 10 is configured with electrical connection lines (not shown in the figure), and the lower surface 102 of the substrate 10 is configured with electrical connection terminals ( (not shown in the figure), and the lines of the upper surface 101 are electrically connected to the terminals of the lower surface 102 . In addition, the lower surface 102 of the substrate 10 also has a plurality of electrical connection elements 80, wherein the electrical connection elements 80 on the lower surface 102 of the substrate 10 are solder balls, and the solder balls can be a C4 standard solder ball, Since the formation method and the function of the electrical connection element 80 are the same as those in the prior art, they are not the main technical features of the present invention, so they will not be described further. The first wafer 20 is a functional wafer, which has an active surface 201 and a back surface 202 , and the back surface 202 of the first wafer 20 is disposed on the upper surface 101 of the substrate 10 facing downward, and the active surface 201 of the first wafer 20 is configured with a A plurality of bonding pads 90 , and the third chip 40 has a top surface 401 and a bottom surface 402 , and the bottom surface 402 of the third chip 40 is disposed on the upper surface 101 of the substrate 10 facing downward, while the third chip 40 is disposed on the top surface 401 There are a plurality of bonding pads 90 . It is worth mentioning that the third wafer 40 may be a functional wafer, a semiconductor die or a dummy wafer 50 . Next, using a wire bonding process, one end of the plurality of first metal wires 21 is electrically connected to the pads 90 on the active surface 201 of the first chip 20, and one end of the plurality of third metal wires 41 is electrically connected to the third The bonding pads 90 on the top surface 401 of the chip 40 electrically connect the other ends of the first metal wires 21 and the other ends of the third metal wires 41 to electrical connection lines (not shown) on the upper surface 101 of the substrate 10 in the picture). Then, a dummy wafer 50 is provided, which has a front side 501 and a back side 502, and the back side 502 of the dummy wafer 50 is disposed on the upper surface 101 of the substrate 10 facing downward, wherein the height of the dummy wafer 50 is equivalent to the height of the first wafer 20, The dummy chip 50 can be a silicon chip, however, the material of the dummy chip 50 is not limited in the present invention. Next, an adhesive layer 60 is provided, especially a FOW (Film Over Wire) adhesive that can embed metal components, and the adhesive layer 60 formed in a colloidal state is covered and disposed on the active surface 201 of the first wafer 20 and the third wafer 40 On the top surface 401 of the dummy wafer 50 and the front surface 501 of the dummy chip 50 , the first metal wire 21 and the third metal wire 41 are covered by the glue layer 60 in a colloidal state. Then, after the adhesive layer 60 is cured, the second wafer 30 is disposed on the adhesive layer 60 , wherein the second wafer 30 is a semiconductor die. Next, using a wire bonding process, one end of the plurality of second metal wires 31 is electrically connected to the pads 90 on the second chip 30 , and the other end of the second metal wires 31 is electrically connected to the upper surface 101 of the substrate 10 . the electrical connection circuit (not shown in the figure). Finally, an encapsulant is used to form a package body 70 , wherein the package body 70 is disposed above the substrate 10 and covers part of the upper surface 101 of the substrate 10 , the first metal wires 21 , the second metal wires 31 , and the third conductors The metal wires 41 and the second wafer 30 . In addition, in the present invention, one or more dummy chips 50 can be placed. When the third chip 40 is the dummy chip 50 , the third chip 40 and the dummy chip 50 can be used on both sides above the upper surface 101 of the substrate 10 as Support applications, increase the stability of the overall multi-chip stack package structure, and also avoid chip breakage due to wire bonding in the air.

Please refer to FIG. 3 again. FIG. 3 is a schematic diagram of a third embodiment of the multi-chip stacked package structure of the invention. As shown in FIG. 3 , the multi-chip stack package structure of the present invention includes a substrate 10 , a first chip 20 , a first metal wire 21 , a dummy chip 50 , an adhesive layer 60 , a second chip 30 , a second metal wire 31 and a package body 70. The substrate 10 has an upper surface 101 and a lower surface 102, the upper surface 101 of the substrate 10 is configured with electrical connection lines (not shown in the figure), and the lower surface 102 of the substrate 10 is configured with electrical connection terminals ( (not shown in the figure), and the lines of the upper surface 101 are electrically connected to the terminals of the lower surface 102 . In addition, the lower surface 102 of the substrate 10 also has a plurality of electrical connection elements 80, wherein the electrical connection elements 80 on the lower surface 102 of the substrate 10 are solder balls, and the solder balls can be a C4 standard solder ball, Since the formation method and the function of the electrical connection element 80 are the same as those in the prior art, they are not the main technical features of the present invention, so they will not be described further. The first wafer 20 is a functional wafer, which has an active surface 201 and a back surface 202 , and the back surface 202 of the first wafer 20 is disposed on the upper surface 101 of the substrate 10 facing downward, and the active surface 201 of the first wafer 20 is configured with a A plurality of solder pads 90 . Next, using a wire bonding process, one end of the plurality of first metal wires 21 is electrically connected to the pads 90 on the active surface 201 of the first chip 20 , and the other end of the first metal wires 21 is electrically connected to the substrate 10 Electrical connection lines (not shown in the figure) on the upper surface 101 of the . Next, an adhesive layer 60 is provided, especially a FOW (Film Over Wire) adhesive that can embed metal components, and the adhesive layer 60 to form a colloidal state is covered and disposed on the active surface 201 of the first wafer 20, and the adhesive is allowed to form. The adhesive layer 60 in the state of the state coats the first metal wire 21 . Then, after the adhesive layer 60 is cured, the second wafer 30 is disposed on the adhesive layer 60 , wherein the second wafer 30 is a semiconductor die. Next, using a wire bonding process, one end of the plurality of second metal wires 31 is electrically connected to the pads 90 on the second chip 30 , and the other end of the second metal wires 31 is electrically connected to the upper surface 101 of the substrate 10 . the electrical connection circuit (not shown in the figure). In particular, in the present invention, the dummy chips 50 are respectively arranged on both sides of the first chip 20 and on the upper surface 101 of the substrate 10, when the maximum length of the first chip 20 and the second chip 30 is less than or equal to the package length When half of the time, the dummy wafers 50 are arranged on both sides of the first wafer 20 to balance the mold flow during molding and reduce the possibility of the warped area of the package body. Meanwhile, the height of the dummy chip 50 is equal to the height of the stacking of the first chip 20 , the adhesive layer 60 and the second chip 30 , and the dummy chip 50 may be a silicon chip. However, the material of the dummy chip 50 in the present invention is: is not restricted. Finally, the encapsulant is used to form the package body 70 , wherein the package body 70 is disposed above the substrate 10 and covers part of the upper surface 101 of the substrate 10 , the dummy chip 50 , the first metal wires 21 , and the second metal wires 31 and the second chip 30 to increase the stability of the overall multi-chip stack package structure.

The above descriptions are only the preferred embodiments of the present invention. Any equivalent modifications or changes made in accordance with the spirit of the present invention, the system architecture of the multi-chip stacking package structure proposed in accordance with the same concept should still be covered by the present invention. within the range.

10: Substrate 20: The first wafer 21: The first metal wire 30: Second wafer 31: Second metal wire 40: Third chip 41: The third metal wire 50: Fake Chip 60: Adhesive layer 70: Package body 80: Electrical connection components 90: Solder pad 101: Upper surface 102: Lower surface 201: Active side 202: Back 401: Top surface 402: Underside 501: Front 502: reverse

FIG. 1 is a schematic diagram illustrating a first embodiment of a multi-chip stacked package structure according to the technology disclosed in the present invention. FIG. 2 is a schematic diagram illustrating a second embodiment of a multi-chip stacked package structure according to the technology disclosed in the present invention. FIG. 3 is a schematic diagram illustrating a third embodiment of a multi-chip stacked package structure according to the technology disclosed in the present invention.

10: Substrate

20: The first wafer

21: The first metal wire

30: Second wafer

31: Second metal wire

50: Fake Chip

60: Adhesive layer

70: Package body

80: Electrical connection components

90: Solder pad

101: Upper surface

102: Lower surface

201: Active side

202: Back

501: Front

502: reverse

Claims (7)

A multi-chip stacked package structure, comprising: a substrate having an upper surface and a lower surface; a first chip, having an active surface and a back surface, the back surface of the first chip is disposed on the upper surface of the substrate; a first metal wire electrically connected to the active surface of the first chip and the upper surface of the substrate respectively; a dummy chip with a front side and a back side, the back side of the dummy chip is disposed on the upper surface of the substrate; an adhesive layer disposed on the active surface of the first chip and the front surface of the dummy chip; a second chip, disposed on the adhesive layer, the second chip is fixed on the active surface of the first chip and the front surface of the dummy chip by the adhesive layer; a second metal wire electrically connected to the second chip and the upper surface of the substrate, respectively; and A package body is used for covering part of the upper surface of the substrate, the first metal wire, the second metal wire and the second chip. A multi-die stacked package structure, comprising: a substrate having an upper surface and a lower surface; a first chip, having an active surface and a back surface, the back surface of the first chip is disposed on the upper surface of the substrate; a first metal wire electrically connected to the active surface of the first chip and the upper surface of the substrate respectively; a third wafer having a top surface and a bottom surface, the bottom surface of the third wafer is disposed on the upper surface of the substrate; a third metal wire electrically connected to the top surface of the third chip and the upper surface of the substrate respectively; a dummy chip with a front side and a back side, the back side of the dummy chip is disposed on the upper surface of the substrate; an adhesive layer disposed on the active surface of the first chip, the top surface of the third chip and the front surface of the dummy chip; a second chip, disposed on the adhesive layer, the second chip is fixed on the active surface of the first chip, the top surface of the third chip and the front surface of the dummy chip by the adhesive layer; a second metal wire electrically connected to the second chip and the upper surface of the substrate, respectively; and A package body is used for covering part of the upper surface of the substrate, the first metal wire, the second metal wire, the third metal wire and the second chip. A multi-die stacked package structure, comprising: a substrate having an upper surface and a lower surface; a first chip, having an active surface and a back surface, the back surface of the first chip is disposed on the upper surface of the substrate; a first metal wire electrically connected to the active surface of the first chip and the upper surface of the substrate respectively; an adhesive layer disposed on the active surface of the first chip; a second chip, disposed on the adhesive layer, the second chip is fixed on the active surface of the first chip by the adhesive layer; a second metal wire electrically connected to the second chip and the upper surface of the substrate respectively; a dummy wafer, respectively disposed on both sides of the first wafer and on the upper surface of the substrate; and A package body is used for covering part of the upper surface of the substrate, the dummy chip, the first metal wire, the second metal wire and the second chip. The multi-chip stack package structure of any one of claims 1 to 3, wherein the first chip is a functional chip and the second chip is a semiconductor die. The multi-chip stack package structure of claim 2, wherein the third chip can be a functional chip, a semiconductor bare chip or a dummy chip. The multi-die stacked package structure according to any one of claims 1 to 3, wherein a plurality of electrical connection elements are further provided on the lower surface of the substrate. The multi-chip stacked package structure of claim 6, wherein the electrical connection element is a solder ball.

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