TWM607285U - Schottky junction field-effect transistor with anti-static discharge and anti-latch-up capabilities - Google Patents

Abstract

A Schottky junction field effect transistor includes: a body block including a substrate; a gate electrode; a drain electrode including a drain metal covering the body block; and a source electrode , Spaced apart from the drain by the body block, the source includes a source metal, the source metal covers the body block, wherein at least one of the drain metal and the source metal and The junction between the body blocks forms a parasitic Schottky junction. Through the characteristics of the parasitic Schottky junction, the Schottky junction field effect transistor of this creation has good ESD protection and Latch-up protection.

Description

Schottky junction field-effect transistor with anti-static discharge and anti-latch-up capabilities

This creation is related to a field effect transistor, especially a Schottky junction field effect transistor.

Low-voltage (LV)/high-voltage (HV)/ultra-high-voltage (UHV) process circuits generally have poor resistance to electrostatic discharge (ESD) before component optimization. In addition, the metal oxide half field effect transistor (MOSFET, including LDMOS) of the high voltage/ultra high voltage process has the advantages of high operating voltage and low on-resistance, so it is often used in power management circuits, power electronics, LED lighting, display drivers, High-voltage input/output terminals in circuits such as RF radio frequency circuits. However, for example, the high-voltage/ultra-high voltage n-type or p-type MOSFET components have no ESD resistance enhancement project, and their anti-ESD current capability is not high. Therefore, it can effectively improve the low-voltage/high-voltage/ultra-high voltage n-type or p-type MOSFET discharge large current Ability is very important

Therefore, the purpose of this creation is to provide a Schottky junction field-effect transistor with good ESD resistance and Latch-up reliability.

The technical means used in this creation to solve the problems of the conventional technology is to provide a Schottky junction field effect transistor, which includes: a body block including a substrate; a gate electrode covering the body block; A drain adjacent to the body block, the drain including a drain metal covering the body block; and a source, adjacent to the body block, and with the body block The drains are spaced apart, the source includes a source metal, the source metal covers the body block, and the junction between at least one of the drain metal and the source metal and the body block Form a parasitic Schottky junction.

In an embodiment of the present creation, a Schottky junction field effect transistor is provided. All of the body block is the substrate, and at least one of the drain metal and the source metal is between the substrate The junction forms a parasitic Schottky junction.

In an embodiment of the present creation, a Schottky junction field effect transistor is provided. The body block includes an n-type well disposed on the substrate, and the drain and the source pass through the n-type well. Separately from the substrate, the junction between at least one of the drain metal and the source metal and the n-type well forms a parasitic Schottky junction.

In an embodiment of the present creation, a Schottky junction field effect transistor is provided. The body block includes a double diffusion region. The double diffusion region is sandwiched between the substrate and the drain. The source The pole is adjacent to the substrate, and the junction between the drain and the double diffusion region forms a parasitic Schottky junction and/or the junction between the source and the substrate forms a parasitic Schottky junction.

In an embodiment of the present creation, a Schottky junction field effect transistor is provided. The body block includes an n-type well disposed on the substrate, and the double diffusion region and the source are connected by the n-type well. Type well and spaced from the substrate, the junction between the drain and the double diffusion region forms a parasitic Schottky junction and/or the junction between the source and the n-type well forms a parasitic Schottky Junction.

In an embodiment of the present invention, a Schottky junction field-effect transistor is provided. At least one of the drain and/or the source includes a heavily doped region, and the heavily doped region is adjacent to the parasitic Schottky meets.

In an embodiment of the present invention, a Schottky junction field effect transistor is provided, and the heavily doped region surrounds the parasitic Schottky junction.

In one embodiment of the present creation, a Schottky junction field effect transistor is provided. The Schottky junction field effect transistor is in the form of a square, a hexagon, an octagon, a circle, or an ellipse. layout.

Through the technical means used in the creation of the Schottky junction field-effect transistor, the drain and/or source of the low-voltage, high-voltage, and ultra-high voltage MOSFETs are removed at least part of the heavily doped region, and the heterogeneous junction is equivalently added (Heterojunction)-Modulation engineering of Schottky diodes. Through the characteristics of this parasitic Schottky junction, the MOSFET's ability to protect against ESD and Latch-up can be enhanced.

The following describes the implementation of this creation based on Figures 1 to 13g. This description is not intended to limit the implementation of this creation, but is a kind of embodiment of this creation.

According to Figures 1 to 13g, the drain metal 31 of the drain 3 and the source metal 41 of the source 4 are only schematic diagrams in these figures. There may be a large piece of one, or there may be several, or a number. There are many rows.

As shown in Figure 1, a Schottky junction field effect transistor 100 according to an embodiment of the present creation includes: a body block 1 including a substrate 11; and a gate electrode 2 covering the body block 1; A drain 3, adjacent to the body block 1; and a source 4, adjacent to the body block 1, and separated from the drain 3 by the body block 1.

The Schottky junction field-effect transistor of this creation can be a low-voltage metal oxide half field effect transistor (LV MOSFET), a drain double diffused metal oxide half field effect transistor (DDDMOS), and a drain extension metal oxide half field effect transistor ( DEMOS, non-isolated or isolated), laterally diffused metal oxide semi-transistor (LDMOS) or other high voltage/ultra high voltage metal oxide semi-field effect transistors.

The junction between at least one of the drain metal 31 of the drain 3 and the source metal 41 of the source 4 and the body block 1 forms a parasitic Schottky junction. In each of the embodiments except Figure 10 and Figure 11, the parasitic Schottky junction is formed by the junction between the drain metal 31 and the body block 1 alone, and the source metal 41 and the body block 1 are used separately. There is a heavily doped source region between them without forming a parasitic Schottky junction. Of course, this creation is not limited to this. In other embodiments (such as the embodiments in Figures 10 and 11), the junction between the source metal 41 and the body block 1 may be used alone to form a parasitic Schott On the base junction, there is a heavily drained region between the drain metal 31 and the body block 1 without forming a parasitic Schottky junction; or the drain metal 31 and the source metal 41 are both connected to the body block 1 The indirect junction forms a parasitic Schottky junction.

The drain metal 31 of the drain 3 is a metal contact, covering the body block 1. In an embodiment where the junction between the drain metal 31 and the body block 1 forms a parasitic Schottky junction, the drain metal 31 is in contact with the body block 1, or is between the drain metal 31 and the body block 1. It is the layout that defines the thin oxygen active region (OD) layer 32 (without high doping implants). By adjusting and defining the thin oxygen active region layer 32 or being a heavily doped region, the I/V characteristics between the drain metal 31 and the body block 1 can be adjusted to form a conventional drain parasitic Schottky junction Or equivalent physical properties of heavily doped regions.

Similarly, the source metal 41 of the source 4 is a metal contact, covering the body block 1. In the embodiment where the junction between the source metal 41 and the body block 1 forms a parasitic Schottky junction, the source metal 41 is in contact with the body block 1, or is between the source metal 41 and the body block 1. It is the layout that defines the thin oxygen active zone layer (not shown). By adjusting the definition of the thin oxygen active region layer or the heavily doped region, the I/V characteristics between the source metal 41 and the body block 1 can be adjusted to form a parasitic Schottky junction with the conventional source. The equivalent physical properties of heavily doped regions.

As shown in Figure 1, the Schottky junction field effect transistor 100 of an embodiment of the present creation is a low voltage n-channel metal oxide semi-transistor (LV nMOSFET). Among them, all of the body block 1 is a substrate 11. The junction between the drain metal 31 and/or the source metal 41 and the substrate 11 forms a parasitic Schottky junction. In this embodiment, only the junction between the drain metal 31 and the substrate 11 forms a parasitic Schottky junction. A thin oxygen active region layer 32 (without high doping implantation) is sandwiched between the drain metal 31 and the substrate 11. In other embodiments, the body block 1 may also have an SOI (silicon on insulator) structure.

As shown in FIG. 2, the Schottky junction field effect transistor 100a of another embodiment of the present creation is a low voltage p-channel metal oxide semi-transistor (LV pMOSFET). Among them, the body block 1 includes a substrate 11 and an n-type well 12. The n-type well 12 is provided on the substrate 11. The drain 3 and the source 4 are separated from the substrate 11 by the n-type well 12. The junction between the drain metal 31 and/or the source metal 41 and the n-type well 12 forms a parasitic Schottky junction. In this embodiment, only the junction between the drain metal 31 and the n-type well 12 forms a parasitic Schottky junction. A thin oxygen active region layer 32 (without high doping implantation) is sandwiched between the drain metal 31 and the n-type well 12. In other embodiments, the body block 1 may also have an SOI (silicon on insulator) structure.

As shown in FIG. 3, the Schottky junction field effect transistor 100b of another embodiment of the present invention is an n-type channel drain double diffused metal oxide semiconductor (DDD nMOSFET). Among them, the body block 1 includes a double diffusion zone 13. The double diffusion region 13 is sandwiched between the substrate 11 and the drain 3. The source 4 is adjacent to the substrate 11. The junction between the drain metal 31 and the double diffusion region 13 forms a parasitic Schottky junction and/or the junction between the source metal 41 of the source 4 and the substrate 1 forms a parasitic Schottky junction. In this embodiment, only the junction between the drain 3 and the double diffusion region 13 forms a parasitic Schottky junction. A thin oxygen active region layer 32 (without high doping implantation) is sandwiched between the drain metal 31 and the double diffusion region 13.

As shown in FIG. 4, the Schottky junction field effect transistor 100c of an embodiment of the present invention is a p-channel drain double diffused MOSFET (DDD pMOSFET). Among them, the body block 1 includes an n-type well 12 and a double diffusion zone 13. The n-type well 12 is provided on the substrate 11. The double diffusion region 13 and the source electrode 4 are separated from the substrate 11 by the n-type well 12. The source 4 is adjacent to the n-type well 12. The junction between the drain metal 31 and the double diffusion region 13 forms a parasitic Schottky junction and/or the junction between the source metal 41 and the n-type well 12 forms a parasitic Schottky junction. In this embodiment, only the junction between the drain metal 31 and the double diffusion region 13 forms a parasitic Schottky junction. A thin oxygen active region layer 32 (without high doping implantation) is sandwiched between the drain metal 31 and the double diffusion region 13.

As shown in FIG. 5, the Schottky junction field effect transistor 100d of another embodiment of the present creation is a high-voltage n-type channel laterally diffused metal oxide semiconductor (nLDMOS). The configurations of the H60NW region 15, the H60PW region 16, the high voltage n-type well (HVNW) region 17, the shallow trench isolation (STI) region 18, the SH_P region 19, and the HVPB region 110 are the same as conventional ones. The junction between the drain metal 31 and the high-voltage n-well region 17 forms a parasitic Schottky junction and/or the junction between the source metal 41 and the HVPB region 110 forms a parasitic Schottky junction. In this embodiment, only the junction between the drain metal 31 and the high-voltage n-well region 17 forms a parasitic Schottky junction. A thin oxygen active region layer 32 (without high-doping implantation) is sandwiched between the drain metal 31 and the high-pressure n-type well region 17.

As shown in Figure 6, the Schottky junction field effect transistor 100e of this embodiment is similar to the Schottky junction field effect transistor 100d shown in Figure 5, with the main difference being: the drain of this embodiment 3 includes a heavily doped region 33, which is a defined thin oxygen active region layer 32 adjacent to and surrounding the parasitic Schottky junction (without high doping implants). In other words, in the conventional LDMOS, only a part of the heavily doped regions of the drain is removed and changed to non-heavy doped regions. Of course, the structure of the heavily doped block 33 surrounding the parasitic Schottky junction can also be applied to the source 4, and can also be applied to the drain 3 and/or the source 4 of other types of MOSFET.

As shown in Figure 7, the Schottky junction field effect transistor 100f of another embodiment of the present creation has a circular layout, while in other embodiments, the Schottky junction field effect transistor can be a square. , Hexagonal, octagonal, oval and other forms of layout.

In this embodiment, the Schottky junction field effect transistor 100f is a high-voltage p-channel laterally diffused metal oxide semiconductor (pLDMOS). The configurations of the n-type buried layer (NBL) 111, the H60PW region 16, the high voltage n-type well (HVNW) region 17, the shallow trench isolation (STI) region 18, and the SH_N region 112 are the same as conventional ones. The junction between the drain metal 31 and the H60PW region 16 forms a parasitic Schottky junction and/or the junction between the source metal 41 and the SH_N region 112 forms a parasitic Schottky junction. In this embodiment, only the junction between the drain metal 31 and the H60PW region 16 forms a parasitic Schottky junction. Between the drain metal 31 and the H60PW region 16 is a thin oxygen active region layer 32 (without high doping implants) that defines a layout.

As shown in FIGS. 8 and 9, the Schottky junction field effect transistor 100g of another embodiment of the present invention is an ultra-high voltage n-channel laterally diffused metal oxide semiconductor (UHV nLDMOS). The Schottky junction field effect transistor 100g has a circular layout. Among them, deep p-type well (DPW) region 113, buried highly doped n-type well (BNW) region 114, high-pressure n-type well (HVNW) region 17, n-type epitaxial layer 115, p-type body (PBODY) region 116 And the configuration of polysilicon (poly) 117 is the same as conventional. The junction between the drain metal 31 and the high-voltage n-type well region 17 forms a parasitic Schottky junction and/or the junction between the source metal 41 and the p-type body region 116 forms a parasitic Schottky junction. In this embodiment, only the junction between the drain metal 31 and the high-voltage n-well region 17 forms a parasitic Schottky junction. A thin oxygen active region layer 32 (without high-doping implantation) is sandwiched between the drain metal 31 and the high-pressure n-type well region 17.

As shown in FIGS. 10 and 11, the Schottky junction field effect transistor 100h of another embodiment of the present creation is an ultra-high voltage n-channel laterally diffused metal oxide semiconductor (UHV nLDMOS). The source metal 41 contacts the p-type body region 116 of the body block 1, and a parasitic Schottky diode is formed on the source 4. In this embodiment, only the junction between the source metal 41 and the p-body (PBODY) region 116 forms a parasitic Schottky junction. The Schottky junction field effect transistor 100h has a circular layout. Among them, deep p-type well (DPW) region 113, buried highly doped n-type well (BNW) region 114, high-pressure n-type well (HVNW) region 17, n-type epitaxial layer 115, p-type body (PBODY) region 116 And the configuration of polysilicon (poly) 117 is the same as conventional.

As shown in Figure 12, the Schottky junction field effect transistor 100i of another embodiment of this creation is similar to the Schottky junction field effect transistor 100h shown in Figure 11. The main difference lies in: Yu Ji Pole 3 forms a parasitic Schottky diode. In detail, the drain electrode 3 is divided into three equal width parts from the center of the circle outward (from left to right in the figure). Of course, in other embodiments, the drain electrode 3 can also be divided into three parts with unequal widths from the center of the circle. In this embodiment, the inner ring and the middle ring are heavily doped regions 33, and the outer ring is a heavily doped region and forms a parasitic Schottky junction. The drain metal 31 located in the outer ring contacts the high-voltage n-type well region 17 of the body block 1, and the drain metal 31 located in the outer ring forms a parasitic Schottky diode. Among them, deep p-type well (DPW) region 113, buried highly doped n-type well (BNW) region 114, high-pressure n-type well (HVNW) region 17, n-type epitaxial layer 115, p-type body (PBODY) region 116 And the configuration of polysilicon (poly) 117 is the same as conventional.

As shown in Figures 13a to 13g, the drain electrode 3 is divided into three equally spaced parts from the center of the circle (of course, it can also be divided into three unequal spaced parts), which are the inner circle, the middle circle, and the In the outer circle, by adjusting the position of the parasitic Schottky diode, the arrangement (from the inner circle to the outside) is divided into seven arrangements. The order of figure 13a to figure 13g is: MMM, NMN, MMN, NNM, MNM, NMM and MNN. Among them, N (gray background) is the heavily doped area, and M (white background) is the position where the parasitic Schottky diode is formed. The Schottky junction field effect transistor 100i shown in Figure 12 is the arrangement of NNM (Figure 13d).

The conventional high-voltage p-channel laterally diffused metal oxide semiconductor (pLDMOS) is used as the reference group. After replacing all heavily doped blocks of the drain of the conventional high-voltage p-type channel laterally diffused metal oxide semiconductor (pLDMOS) to form a parasitic Schottky junction, it becomes the Schottky junction as shown in Figure 7 Field effect transistor 100f, and Schottky junction field effect transistor 100f as a control group. The transmission line pulse (TLP) test results of the two are as follows. Compared with the reference group of high-voltage components, the control group's high-voltage component holding voltage V _h (latch-up resistance) increased from 78.61V to 79.92V, and the component's secondary breakdown current I _t2 (ESD resistance) increased from 0.89A to 1.03A: [Table 1] Sample Type V _t1 (V) V _h (V) I _t2 (A) Reference group 78.61 78.61 0.89 Control group 79.92 79.92 1.03

It can be seen from Table 1 that through the formation of the parasitic Schottky junction, the electrostatic discharge resistance (I _t2 ) of the Schottky junction field-effect transistor of this creation increased by 22.5%, and the latch-up resistance (V _h ) increased by 1.67 %. In other words, the Schottky junction field effect transistor of this creation has better anti-static discharge and anti-latch-up capabilities.

In addition, if the Schottky junction field-effect transistor created in this book is paired with a silicon controlled rectifier (SCR) structure, it can strengthen the anti-static discharge ability.

The above descriptions and descriptions are only descriptions of the preferred embodiments of this creation. Those with general knowledge of this technology should make other modifications based on the scope of patent application defined below and the above descriptions, but these modifications should still be made. It is the creative spirit of this creation and within the scope of rights of this creation.

100: Schottky junction field effect transistor 100a: Schottky junction field effect transistor 100b: Schottky junction field effect transistor 100c: Schottky junction field effect transistor 100d: Schottky junction field effect transistor 100e: Schottky junction field effect transistor 100f: Schottky junction field effect transistor 100g: Schottky junction field effect transistor 100h: Schottky junction field effect transistor 100i: Schottky junction field effect transistor 1: Ontology block 11: substrate 110: HVPB area 111: N-type buried layer 112: SH_N area 113: deep p-well area 114: Buried highly doped n-type well region 115: n-type epitaxial layer 116: p-type body area 117: Polysilicon 12: n-type well 13: Double diffusion zone 15: H60NW area 16: H60PW area 17: High pressure n-type well area 18: Shallow trench isolation area 19: SH_P area 2: gate 3: Dip pole 31: Drain metal 32: Define the thin oxygen active zone layer 33: heavily doped block 4: source 41: source metal

[Figure 1] is a cross-sectional view showing a Schottky junction field effect transistor according to an embodiment of this creation; [Figure 2] is a cross-sectional view showing another embodiment of the Schottky junction field-effect transistor according to the present invention; [Figure 3] is a cross-sectional view showing another embodiment of the Schottky junction field-effect transistor according to this creation; [Figure 4] is a cross-sectional view showing another embodiment of the Schottky junction field-effect transistor according to this creation; [Figure 5] is a cross-sectional view showing another embodiment of the Schottky junction field-effect transistor according to the present invention; [Figure 6] is a cross-sectional view showing another embodiment of the Schottky junction field-effect transistor according to this creation; [Figure 7] is a cross-sectional view showing another embodiment of the Schottky junction field-effect transistor according to the present invention; [Figure 8] is a layout diagram showing a Schottky junction field effect transistor according to another embodiment of this creation; [Figure 9] A-A cross-sectional view showing the Schottky junction field-effect transistor in Figure 8; [Figure 10] is a layout diagram showing a Schottky junction field effect transistor according to another embodiment of this creation; [Figure 11] A-A cross-sectional view showing the Schottky junction field-effect transistor in Figure 10; [Figure 12] is a cross-sectional view showing another embodiment of the Schottky junction field effect transistor according to this creation; [Picture 13a] to [Picture 13g] are drawings showing the layout of the drain terminal of the Schottky junction field-effect transistor according to this creation.

100: Schottky junction field effect transistor

1: Ontology block

11: substrate

2: gate

3: Dip pole

31: Drain metal

32: Define the thin oxygen active zone layer

4: source

41: source metal

Claims (8)

A Schottky junction field effect transistor, including: A body block including a substrate; A gate, covering the body block; A drain adjacent to the body block, the drain including a drain metal, the drain metal covering the body block; and A source electrode adjacent to the body block and spaced from the drain electrode by the body block, the source electrode includes a source metal, and the source metal covers the body block, Wherein, the junction between at least one of the drain metal and the source metal and the body block forms a parasitic Schottky junction. For example, the Schottky junction field effect transistor of claim 1, wherein all of the body block is the substrate, and the junction between at least one of the drain metal and the source metal and the substrate forms a parasitic gap Tekey junction. For example, the Schottky junction field effect transistor of claim 1, wherein the body block includes an n-type well disposed on the substrate, and the drain and the source are in phase with the substrate through the n-type well Space, the junction between at least one of the drain metal and the source metal and the n-type well forms a parasitic Schottky junction. For example, the Schottky junction field effect transistor of claim 1, wherein the body block includes a double diffusion region, the double diffusion region is sandwiched between the substrate and the drain, and the source is adjacent to the substrate , The junction between the drain and the double diffusion region forms a parasitic Schottky junction and/or the junction between the source and the substrate forms a parasitic Schottky junction. For example, the Schottky junction field effect transistor of claim 1, wherein the body block includes an n-type well disposed on the substrate, and the double diffusion region and the source are connected to the n-type well through the n-type well The substrates are spaced apart, the junction between the drain and the double diffusion region forms a parasitic Schottky junction and/or the junction between the source and the n-type well forms a parasitic Schottky junction. For example, the Schottky junction field effect transistor of claim 1, wherein at least one of the drain and/or the source includes a heavily doped region, and the heavily doped region is adjacent to the parasitic Schottky junction . For example, the Schottky junction field effect transistor of claim 6, wherein the heavily doped region surrounds the parasitic Schottky junction. For example, the Schottky junction field effect transistor of claim 1, wherein the Schottky junction field effect transistor has a square, hexagonal, octagonal, circular or elliptical layout.

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