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TWM602728U - Packaging structure of cascode gallium nitride field effect transistor - Google Patents

Packaging structure of cascode gallium nitride field effect transistor Download PDF

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Publication number
TWM602728U
TWM602728U TW109208613U TW109208613U TWM602728U TW M602728 U TWM602728 U TW M602728U TW 109208613 U TW109208613 U TW 109208613U TW 109208613 U TW109208613 U TW 109208613U TW M602728 U TWM602728 U TW M602728U
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Taiwan
Prior art keywords
lead frame
effect transistor
field effect
drain
gallium nitride
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TW109208613U
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Chinese (zh)
Inventor
顏宗賢
王興燁
沈峰睿
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鴻鎵科技股份有限公司
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Priority to TW109208613U priority Critical patent/TWM602728U/en
Publication of TWM602728U publication Critical patent/TWM602728U/en

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    • H10W70/60

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  • Junction Field-Effect Transistors (AREA)

Abstract

一種共源共柵氮化鎵場效電晶體的封裝結構,包括有一導線架,此導線架上直接設置有一氮化鎵場效電晶體及一金屬氧化物半導體。氮化鎵場效電晶體包括有一直接設置於導線架上之第一基體,此第一基體之表側具有一第一汲極、一第一閘極及一第一源極,其中第一汲極及第一閘極分別電性連接至導線架。金屬氧化物半導體包括有一直接設於導線架上之第二基體,此第二基體之表側具有一第二汲極、一第二閘極及一第二源極,其中第二汲極與第一源極直接電性連接,且第二閘極及第二源極分別電性連接至導線架。A cascode gallium nitride field effect transistor packaging structure includes a lead frame on which a gallium nitride field effect transistor and a metal oxide semiconductor are directly arranged. The gallium nitride field effect transistor includes a first substrate directly arranged on the lead frame. The surface of the first substrate has a first drain, a first gate, and a first source. The first drain And the first gate are electrically connected to the lead frame respectively. The metal oxide semiconductor includes a second substrate directly arranged on the lead frame. The surface of the second substrate has a second drain, a second gate, and a second source. The second drain and the first The source electrode is directly electrically connected, and the second gate electrode and the second source electrode are respectively electrically connected to the lead frame.

Description

共源共柵氮化鎵場效電晶體的封裝結構Packaging structure of cascode gallium nitride field effect transistor

本創作與半導體電晶體有關,尤指一種共源共柵氮化鎵場效電晶體的封裝結構。This creation is related to semiconductor transistors, especially a cascode gallium nitride field effect transistor package structure.

第2圖所示者為一種共源共柵氮化鎵場效電晶體的習知封裝結構,其包括有一導線架5,且導線架5上設有一垂直式的金屬氧化物半導體7及一氮化鎵場效電晶體6。氮化鎵場效電晶體6設有一汲極61、一閘極62及一源極63,而金屬氧化物半導體7設有一汲極71、一閘極72及一源極73,其中垂直式金屬氧化物半導體7的汲極71位於底面,為了順利與氮化鎵場效電晶體6的源極63電性連接,則須於半導體7的汲極71下方設置一層面積較大的金屬鍍膜81,如此又須更進一步地於導線架5上設置絕緣的陶瓷基板82,以隔開金屬鍍膜81與導線架5。因此,習知共源共柵氮化鎵場效電晶體的結構及製程皆較為複雜,而有成本較高的缺失。Figure 2 shows a conventional cascode GaN field effect transistor package structure, which includes a lead frame 5, and the lead frame 5 is provided with a vertical metal oxide semiconductor 7 and a nitrogen Gallium fluoride field effect transistor 6. The GaN field effect transistor 6 is provided with a drain 61, a gate 62 and a source 63, and the metal oxide semiconductor 7 is provided with a drain 71, a gate 72 and a source 73, of which the vertical metal The drain 71 of the oxide semiconductor 7 is located on the bottom surface. In order to be electrically connected to the source 63 of the gallium nitride field-effect transistor 6, a layer of metal coating 81 with a larger area must be provided under the drain 71 of the semiconductor 7. Therefore, an insulating ceramic substrate 82 must be further provided on the lead frame 5 to separate the metal coating 81 and the lead frame 5. Therefore, the structure and manufacturing process of the conventional cascode gallium nitride field effect transistor are relatively complicated, and there are disadvantages of higher cost.

有鑑於此,如何改進上述問題即為本創作所欲解決之首要課題。In view of this, how to improve the above problems is the primary subject that this creation intends to solve.

本創作之主要目的在於提供一種共源共柵氮化鎵場效電晶體的封裝結構,其使用水平式半導體,使半導體的汲極與氮化鎵電晶體的源極直接電性連接,具有簡化結構之功效。The main purpose of this creation is to provide a cascode GaN field-effect transistor packaging structure, which uses a horizontal semiconductor to directly electrically connect the drain of the semiconductor to the source of the GaN transistor, which is simplified The effect of structure.

為達前述之目的,本創作提供一種共源共柵氮化鎵場效電晶體的封裝結構,其包括有: 一導線架; 一氮化鎵場效電晶體,其包括有一直接設置於該導線架上之第一基體,該第一基體之表側具有一第一汲極、一第一閘極及一第一源極,其中該第一汲極及該第一閘極分別電性連接至該導線架; 一金屬氧化物半導體,其包括有一直接設於該導線架上之第二基體,該第二基體之表側具有一第二汲極、一第二閘極及一第二源極,其中該第二汲極與該第一源極直接電性連接,且該第二閘極及該第二源極分別電性連接至該導線架。 In order to achieve the aforementioned purpose, this creation provides a cascode gallium nitride field-effect transistor package structure, which includes: A lead frame A GaN field effect transistor includes a first substrate directly arranged on the lead frame, the surface of the first substrate has a first drain, a first gate, and a first source, wherein The first drain and the first gate are respectively electrically connected to the lead frame; A metal oxide semiconductor includes a second substrate directly arranged on the lead frame. The surface of the second substrate has a second drain, a second gate and a second source, wherein the second The drain is directly electrically connected to the first source, and the second gate and the second source are respectively electrically connected to the lead frame.

於一實施例中,以一封裝體包覆該導線架、該氮化鎵場效電晶體及該金屬氧化物半導體。In one embodiment, the lead frame, the gallium nitride field effect transistor and the metal oxide semiconductor are covered with a package.

較佳地,該導線架設有一伸出該封裝體外之接腳。Preferably, the lead frame is provided with a pin extending out of the package body.

本創作之上述目的與優點,不難從以下所選用實施例之詳細說明與附圖中獲得深入了解。The above objectives and advantages of this creation are not difficult to gain an in-depth understanding from the detailed description and drawings of the selected embodiments below.

請參閱第1圖,所示者為本創作提供之共源共柵氮化鎵場效電晶體的封裝結構,其包括有一導線架1,該導線架1上直接設置有一氮化鎵場效電晶體2(GaN FET)及一水平式的金屬氧化物半導體3(MOS),其中該氮化鎵場效電晶體2具有一直接結合於該導線架1上的第一基體21,該第一基體21之表側設有一第一汲極22、一第一閘極23及一第一源極24,上述該第一汲極22及該第一閘極23分別電性連接至該導線架1;該金屬氧化物半導體3具有一直接結合於該導線架1上的第二基體31,該第二基體31之表側設有一第二汲極32、一第二閘極33及一第二源極34,上述該第二閘極33及該第二源極34分別電性連接至該導線架1。Please refer to Figure 1. The package structure of the cascode gallium nitride field effect transistor provided by this creation is shown. It includes a lead frame 1 on which a gallium nitride field effect transistor is directly arranged. Crystal 2 (GaN FET) and a horizontal metal oxide semiconductor 3 (MOS), wherein the GaN field effect transistor 2 has a first substrate 21 directly bonded to the lead frame 1. The first substrate A first drain 22, a first gate 23, and a first source 24 are provided on the front side of 21. The first drain 22 and the first gate 23 are electrically connected to the lead frame 1 respectively; The metal oxide semiconductor 3 has a second base body 31 directly bonded to the lead frame 1. A second drain electrode 32, a second gate electrode 33, and a second source electrode 34 are provided on the surface of the second base body 31. The second gate 33 and the second source 34 are electrically connected to the lead frame 1 respectively.

承上,該氮化鎵場效電晶體2之第一源極24係與該金屬氧化物半導體3之第二汲極32直接電性連接,構成共源共柵的形式。接著,以一封裝體4包覆該導線架1、該氮化鎵場效電晶體2及該金屬氧化物半導體3,並自該導線架1延伸出一伸出該封裝體4外之接腳11。In addition, the first source 24 of the GaN field effect transistor 2 is directly electrically connected to the second drain 32 of the metal oxide semiconductor 3 to form a cascode form. Then, a package body 4 is used to cover the lead frame 1, the GaN field effect transistor 2 and the metal oxide semiconductor 3, and a pin 11 extending from the package body 4 is extended from the lead frame 1. .

藉由上述結構,本創作使該氮化鎵場效電晶體2之第一源極24係與該金屬氧化物半導體3之第二汲極32直接電性連接,因而略去習知電晶體中金屬鍍膜及陶瓷基板的結構,達到簡化結構及製程的目的,並進而降低成本。With the above structure, this creation makes the first source 24 of the GaN field-effect transistor 2 and the second drain 32 of the metal oxide semiconductor 3 directly electrically connected, thus omitting the conventional transistor The structure of the metal coating and the ceramic substrate achieves the purpose of simplifying the structure and manufacturing process, and further reducing the cost.

惟以上實施例之揭示僅用以說明本創作,並非用以限制本創作,舉凡等效元件之置換仍應隸屬本創作之範疇。However, the disclosure of the above embodiments is only used to illustrate the creation, not to limit the creation, and the replacement of equivalent components should still belong to the scope of the creation.

綜上所述,可使熟知本領域技術者明瞭本創作確可達成前述目的,實已符合專利法之規定,爰依法提出申請。In summary, those skilled in the art can understand that this creation can indeed achieve the aforementioned purpose, and that it has actually complied with the provisions of the Patent Law, so Yan filed an application in accordance with the law.

1:導線架 11:接腳 2:氮化鎵場效電晶體 21:第一基體 22:第一汲極 23:第一閘極 24:第一源極 3:金屬氧化物半導體 31:第二基體 32:第二汲極 33:第二閘極 34:第二源極 4:封裝體 5:導線架 6:氮化鎵場效電晶體 61:汲極 62:閘極 63:源極 7:金屬氧化物半導體 71:汲極 72:閘極 73:源極 81:金屬鍍膜 82:陶瓷基板 1: Lead frame 11: Pin 2: Gallium nitride field effect transistor 21: The first substrate 22: The first drain 23: The first gate 24: The first source 3: Metal oxide semiconductor 31: The second substrate 32: The second drain 33: The second gate 34: The second source 4: Package body 5: Lead frame 6: GaN field effect transistor 61: Dip pole 62: Gate 63: Source 7: Metal Oxide Semiconductor 71: Dip pole 72: Gate 73: Source 81: Metal coating 82: Ceramic substrate

第1圖為本創作之構造示意圖; 第2圖為習知結構之構造示意圖。 Picture 1 is a schematic diagram of the structure of the creation; Figure 2 is a schematic diagram of the conventional structure.

1:導線架 1: Lead frame

11:接腳 11: Pin

2:氮化鎵場效電晶體 2: GaN field effect transistor

21:第一基體 21: The first substrate

22:第一汲極 22: The first drain

23:第一閘極 23: first gate

24:第一源極 24: first source

3:金屬氧化物半導體 3: metal oxide semiconductor

31:第二基體 31: second substrate

32:第二汲極 32: second drain

33:第二閘極 33: second gate

34:第二源極 34: second source

4:封裝體 4: Package body

Claims (3)

一種共源共柵氮化鎵場效電晶體的封裝結構,其包括有: 一導線架; 一氮化鎵場效電晶體,其包括有一直接設置於該導線架上之第一基體,該第一基體之表側具有一第一汲極、一第一閘極及一第一源極,其中該第一汲極及該第一閘極分別電性連接至該導線架; 一金屬氧化物半導體,其包括有一直接設於該導線架上之第二基體,該第二基體之表側具有一第二汲極、一第二閘極及一第二源極,其中該第二汲極與該第一源極直接電性連接,且該第二閘極及該第二源極分別電性連接至該導線架。 A cascode gallium nitride field effect transistor packaging structure, which includes: A lead frame A GaN field effect transistor includes a first substrate directly arranged on the lead frame, the surface of the first substrate has a first drain, a first gate, and a first source, wherein The first drain and the first gate are respectively electrically connected to the lead frame; A metal oxide semiconductor includes a second substrate directly arranged on the lead frame. The surface of the second substrate has a second drain, a second gate and a second source, wherein the second The drain is directly electrically connected to the first source, and the second gate and the second source are respectively electrically connected to the lead frame. 如請求項1所述之共源共柵氮化鎵場效電晶體的封裝結構,其中,以一封裝體包覆該導線架、該氮化鎵場效電晶體及該金屬氧化物半導體。The package structure of the cascode gallium nitride field effect transistor according to claim 1, wherein the lead frame, the gallium nitride field effect transistor and the metal oxide semiconductor are covered with a package body. 如請求項2所述之共源共柵氮化鎵場效電晶體的封裝結構,其中,該導線架設有一伸出該封裝體外之接腳。The package structure of the cascode gallium nitride field-effect transistor according to claim 2, wherein the lead frame is provided with a pin extending out of the package body.
TW109208613U 2020-07-07 2020-07-07 Packaging structure of cascode gallium nitride field effect transistor TWM602728U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114695334A (en) * 2020-12-29 2022-07-01 新唐科技股份有限公司 Packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114695334A (en) * 2020-12-29 2022-07-01 新唐科技股份有限公司 Packaging structure

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