TWM678663U - Reverse power converter - Google Patents

Abstract

A regressive power converter is disclosed. The regressive power converter includes a transformer, first and second power transistors, first and second current sources, first to fourth transistors, first and second pull-down units, and a switching control circuit. The control terminals of the first to fourth transistors are respectively connected to the switching control circuit. The first current source provides a first driving current under the control of the first transistor, and the second current source provides a second driving current under the control of a third transistor. The base of the first power transistor receives the first driving current and is connected to the first terminal of the second transistor and the first terminal of the first pull-down unit. The second terminal of the second transistor is grounded or connected to the base of the second power transistor. The base of the second power transistor receives the second driving current and is connected to the emitter of the first power transistor, the second terminal of the first pull-down unit, the first terminal of the fourth transistor, and the first terminal of the second pull-down unit. The second terminal of the fourth transistor is grounded.

Description

Reverse-drive power converter

This invention relates to the field of electrical circuits, and in particular to a reversible power converter.

In the field of small and medium power converters, cruise converters dominate the market due to their simple circuitry, high conversion efficiency, and wide input voltage range. Bipolar junction transistors (BJTs), also known as power transistors, have been widely used in the low-power market below 18W in recent years due to their excellent switching characteristics and low price.

With the increasing functionality of mobile devices such as smartphones and tablets, the battery capacity powering these devices has exploded. Consequently, the output power of chargers and adapters supplying these batteries has continuously increased, from the original 5W to 20W, 30W, 45W, 65W, and even higher. Improving overall system efficiency and power density, so that power converters can meet both the miniaturization needs of chargers and adapters and increasingly stringent power efficiency standards, has become a key research focus.

According to an embodiment of the present invention, a regressive power converter includes a transformer, a first power transistor, a second power transistor, a first current source, a second current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a first pull-down unit including a first resistor, a second pull-down unit including a second resistor, and a switching control circuit. The control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor are respectively connected to the switching control circuit. The first current source provides a first driving current under the control of the first transistor, and the second current source provides a second driving current under the control of the third transistor. The first terminal and the first terminal of the first pull-down unit are connected to the base of the first power transistor. The base of the first power transistor also receives the first driving current. The second terminal of the second transistor is grounded or connected to the base of the second power transistor. The emitter of the first power transistor, the second terminal of the first pull-down unit, the first terminal of the fourth transistor, and the first terminal of the second pull-down unit are connected to the base of the second power transistor. The base of the second power transistor also receives the second driving current. The second terminal of the fourth transistor is grounded. The collectors of the first power transistor and the second power transistor are connected to the primary winding of the transformer. The emitter of the second power transistor is grounded through an inductance sensing resistor.

The features and exemplary embodiments of this invention will be described in detail below. Many specific details are presented in the following detailed description to provide a comprehensive understanding of this invention. However, it will be apparent to those skilled in the art that this invention can be implemented without some of these specific details. The description of the embodiments below is merely intended to provide a better understanding of this invention by illustrating examples. This invention is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of this invention. Well-known structures and techniques are not shown in the diagrams and the following description in order to avoid causing unnecessary ambiguity to this invention. Additionally, it should be noted that the term "A and B connected" used here can mean "A and B are directly connected" or "A and B are indirectly connected via one or more other components".

Existing power transistors can only be used in the low-power market, mainly because power transistors are current-driven, requiring sufficient driving current to turn them on. In addition, the high driving losses and slow turn-off speed of power transistors limit their application in the higher output power market.

This invention proposes a regressive power converter that uses a combination of six transistors and two pull-down units to control the power transistor drive, thereby ensuring normal power transistor drive, improving the switching speed of the power transistor, and reducing power transistor losses.

Figure 1A shows an example circuit diagram of a cruise power converter 100A according to an embodiment of the present invention. As shown in Figure 1A, the cruise power converter 100A includes a transformer T, a first power transistor Q1, a second power transistor Q2, a first current source _ISB1 , a second current source _ISB2 , a first transistor D1, a second transistor D2, a third transistor D3, a fourth transistor D4, a first pull-down unit including a first resistor R1, a second pull-down unit including a second resistor R2, and a switching control circuit 130. The control terminals of the first transistor D1, the second transistor D2, the third transistor D3, and the fourth transistor D4 are respectively connected to the switching control circuit 130. The first current source _ISB1 provides a first driving current _IB1 under the control of the first transistor D1, and the second current source _ISB2 provides a second driving current _IB2 under the control of the third transistor D3. The first terminal of the second transistor D2 and the first terminal of the first pull-down unit are connected to the base of the first power transistor Q1. The base of the first power transistor Q1 also receives the first driving current _IB1 . The second terminal of the second transistor D2 is connected to the base of the second power transistor Q2. The emitter of the first power transistor Q1, the second terminal of the first pull-down unit, the first terminal of the fourth transistor D4, and the first terminal of the second pull-down unit are connected to the base of the second power transistor Q2. The base of the second power transistor Q2 also receives the second driving current _IB2 . The second terminal of the fourth transistor D4 is grounded. The collector of the first power transistor Q1 and the collector of the second power transistor Q2 are connected to the primary winding of the transformer T. The emitter of the second power transistor Q2 is grounded through the current sensing resistor Rs.

Figure 1B shows another example circuit diagram of a boost power converter 100B according to an embodiment of the present invention. The difference between the boost power converter 100B shown in Figure 1B and the boost power converter 100A shown in Figure 1A is that the second terminal of the second transistor D2 is grounded, and the connection relationships of other parts are the same as the corresponding parts shown in Figure 1A, which will not be described again here.

In some embodiments, the first pull-down unit may further include a fifth transistor D5 connected in series with the first resistor R1, and the second pull-down unit may further include a sixth transistor D6 connected in series with the second resistor R2. The control terminals of the fifth transistor D5 and the sixth transistor D6 are respectively connected to the switching control circuit 130. Further, the first transistor D1, the second transistor D2, the third transistor D3, the fourth transistor D4, the fifth transistor D5, and the sixth transistor D6 can be implemented as N-type metal oxide semiconductor field-effect transistors (N-MOSFETs).

In some embodiments, the first pull-down unit may include only the first resistor R1 (or the first pull-down unit may be regarded as including the first resistor R1 and the fifth transistor D5 connected in series, and the fifth transistor D5 always remains in the on state), and the second pull-down unit may include only the second resistor R2 (or the second pull-down unit may be regarded as including the second resistor R2 and the sixth transistor D6 connected in series, and the sixth transistor D6 always remains in the on state). In this case, the second power transistor Q2 in one pulse width modulation (PWM) switching cycle includes the following stages: the second power transistor Q2 changes from the off state to the on state; the second power transistor Q2 is in the on state and the sensed voltage of the current sensing resistor Rs is less than the preset voltage value; the second power transistor Q2 is in the on state and the sensed voltage of the current sensing resistor Rs is not less than the preset voltage value; the second power transistor Q2 changes from the on state to the off state; the second power transistor Q2 is in the off state. The states of the other circuit components corresponding to these states are as follows: During the process of the second power transistor Q2 changing from the off state to the on state, and when the second power transistor Q2 is in the on state and the sensed voltage on the current sensing resistor Rs is less than the preset voltage value, the first transistor D1 is in the on state so that the first current source _SB1 provides the first driving current _IB1 , the third transistor D3 is in the off state so that the second current source _SB2 stops providing the second driving current _IB2 , the second transistor D2 and the fourth transistor D4 are in the off state, and the base current of the second power transistor Q2 is provided by the first driving current _IB1 after being amplified by the first power transistor Q1.

When the second power transistor Q2 is in the on state and the sensed voltage on the current sensing resistor Rs is not less than the preset voltage value, the first transistor D1 is in the off state to temporarily stop the first current source _ISB1 from providing the first driving current _IB1 , the third transistor D3 is in the on state to provide the second driving current _{IB2 from the second current source ISB2 ,} the second transistor D2 and the fourth transistor D4 are in the off state, and the base current of the second power transistor Q2 is jointly provided by the second driving current _IB2 and the emitter current of the first power transistor Q1.

During the process of the second power transistor Q2 changing from the on state to the off state, and when the second power transistor Q2 is in the off state, the first transistor D1 is in the off state to temporarily stop the first current source _SB1 from providing the first driving current _IB1 , the third transistor D3 is in the off state to temporarily stop the second current source _SB2 from providing the second driving current _IB2 , and the second transistor D2 and the fourth transistor D4 are in the on state.

Figures 2A and 2B show two examples of operating waveforms for multiple signals in the cruise power converter 100A/100B shown in Figures 1A/1B, where _IS represents the sensed current flowing through the current sensing resistor Rs. The fifth transistor D5 and the sixth transistor D6 operate according to the state of the second power transistor Q2, and the operations of D1-D4 are the same as described above. Specifically, during the process of the second power transistor Q2 changing from the off state to the on state, and when the second power transistor Q2 is in the on state and the sensed voltage across the current sensing resistor Rs is less than a preset voltage value, the fifth transistor D5 and the sixth transistor D6 are in the off state. When the second power transistor Q2 is in the on state and the sensed voltage on the current sensing resistor Rs is not less than the preset voltage value, during the process of the second power transistor Q2 changing from the on state to the off state, and when the second power transistor Q2 is in the off state, the fifth transistor D5 and the sixth transistor D6 are in the on state.

As shown in Figures 1A/1B and 2A/2B, in some embodiments, at the start of a pulse width modulation switching cycle (i.e., at time t1), the first transistor D1 changes from the off state to the on state, and the first driving current _IB1 is conducted to the base of the first power transistor Q1, causing the first power transistor Q1 to change from the off state to the on state. Consequently, the emitter of the first power transistor Q1 injects a larger base current into the second power transistor Q2 (the maximum injectable current of the first power transistor Q1 is β× _IB1 ), causing the second power transistor Q2 to quickly enter the saturation region (i.e., the on state) to reduce turn-on losses. When the second power transistor Q2 is in the conducting state, the sensed current _IS gradually increases, and the sensed voltage Vcs of the current sensing resistor Rs increases accordingly. When the sensed voltage Vcs reaches the preset voltage value (i.e., time t2), the first transistor D1 is turned off, and the third transistor D3, the fifth transistor D5 and the sixth transistor D6 are turned on. The first power transistor Q1 and the second power transistor Q2 are in a weak pull-down state, and at the same time, they are maintained in the conducting state by the charge carriers stored in the base region. When the sensed voltage Vcs rises to the turn-off threshold (i.e., at time t3a), the third transistor D3 turns off, while the second transistor D2 and the fourth transistor D4 turn on simultaneously. The first power transistor Q1 and the second power transistor Q2 change from the on state to the off state. The sensed current _IS decreases after a delay (i.e., at time t3). All these components remain in their current state until the start of the next pulse width modulation switching cycle (i.e., at time t4). Due to the earlier turn-on of the fifth transistor D5 and the sixth transistor D6, the number of base carriers in the first power transistor Q1 and the second power transistor Q2 is reduced, allowing them to be turned off quickly and reducing the turn-off losses of the power transistors.

As shown in Figures 2A and 2B, the time interval t1-t3 can be denoted as Ton; during the time interval t1-t2, the second power transistor Q2 is in the on state, and the base current is provided by the first driving current _IB1 ; the time interval t2-t3 can be denoted as Pre_off, during which the second power transistor Q2 is in a weakly pulled-down on state, and the base current is provided by the second driving current _IB2 ; the time interval t3-t4 can be denoted as Toff, during which the second power transistor Q2 is in the off state, and the base current is 0.

In some embodiments, the resistance values of the first resistor R1 and the second resistor R2 are relatively large, typically ranging from hundreds to thousands of ohms, such as 600 ohms or 1200 ohms. The preset voltage value corresponding to the current sensing resistor Rs is located in the range of 70%-90% of the maximum value of the sensed voltage Vcs, for example, the preset voltage value is set to 75% of the maximum value of the sensed voltage Vcs. In some embodiments, since the second power transistor Q2 needs to quickly enter the saturation region during the Ton time period, a larger base current is required, while the second power transistor Q2 is preparing to turn off during the Pre_off time period, requiring a smaller base current, the base current provided by the first driving current _IB1 to the second power transistor Q2 is much larger than the base current provided by the second driving current _IB2 to the second power transistor Q2.

The difference between Figures 2A and 2B lies in the magnitude of the first driving current _IB1 during the Ton time interval. In Figure 2A, the first driving current _IB1 is a constant current, while in Figure 2B, the first driving current _IB1 includes both high-pulse and ramp-up currents. The first driving current _IB1 can also be a current that varies in a positive correlation with the sensed current _IS flowing through the current-sensing resistor Rs, and its magnitude only needs to be sufficient to provide the base current of the second power transistor Q2. In some embodiments, as shown in Figure 2B, to accelerate the turn-on speed of the second power transistor Q2, the first driving current _IB1 can take a larger value at the beginning of the pulse modulation switching cycle, and then vary according to its positive correlation with the sensed current _IS .

In the regressive power converter 100A/100B shown in Figures 1A/1B, although the first current source _ISB1 and the first transistor D1 are shown as directly connected, in actual implementation, the first current source _ISB1 does not necessarily have to be directly connected to the first transistor D1. It is sufficient that the first current source _ISB1 can provide the first driving current _IB1 or temporarily stop providing the first driving current _IB1 under the control of the first transistor D1. Similarly, although the second current source _ISB2 and the third transistor D3 are shown as directly connected, in actual implementation, the second current source ISB2 does not necessarily have to be directly connected to the third transistor D3. It is sufficient that the second current source _ISB2 can provide the second driving current _IB2 or temporarily stop providing the second driving current _IB2 under the control of the third transistor D3. _B2 is sufficient.

In other words, the circuit portions of the cruise power converter 100A/100B shown in Figures 1A/1B related to the first/second current sources _ISB1 / _ISB2 and the first/third transistors D1/D3 can also be implemented in other forms, wherein the first driving current _IB1 for the first power transistor Q1 and the second power transistor Q2 is provided by the first current source _ISB1 under the control of the first transistor D1, and the second driving current _IB2 for the second power transistor Q2 is provided by the second current source _ISB2 under the control of the third transistor D3.

Figure 3A shows a schematic diagram of an example alternative implementation of the circuit portion related to the first/second current sources _ISB1 / _ISB2 and the first/third transistors D1/D3. As shown in Figure 3A, the first/second driving currents _IB1 / _IB2 are provided by the first/second current sources _SB1 / _SB2 under the control of the first/third transistors D1/D3. Specifically: when the first/third transistors D1/D3 are in the ON state, all the current from the first/second current sources _SB1 / _SB2 flows through them and is used as the first/second driving currents _IB1 / _IB2 ; when the first/third transistors D1/D3 are in the OFF state, no current from the first/second current sources _SB1 / _SB2 flows through them, and the first/second driving currents _IB1 / _IB2 are zero. In this case, the area of the first/third transistors D1/D3 is relatively large.

Figure 3B shows a schematic diagram of another example alternative implementation of the circuit portion related to the first/second current sources _ISB1 / _ISB2 and the first/third transistors D1/D3. As shown in Figure 3B, the first/second current sources _ISB1 / _ISB2 are implemented as mirror current sources. The reference current source _ISBN (N=1,2) used for the mirror current source is either included in the mirror current source or not included in the mirror current source under the control of the first/third transistors D1/D3. Specifically: when the first/third transistors D1/D3 are in the on state, the current of the reference current source _ISBN is generated through the mirror as the mirror current of the first/second driving currents _IB1 / _ISB2 . The current of the reference current source _ISBN is only 1/n of the first driving current _IB1 , where n is a positive number; when the first/third transistors D1/D3 are in the off state, the reference current source ISBN... The current of _SBN is not mirrored, and the first/second driving currents _IB1 / _IB2 are zero. In this case, the current flowing through the first transistor D1 is relatively small, and the area of the first transistor D1 is greatly reduced compared to the case shown in Figure 3A.

Figure 3C shows a schematic diagram of yet another example alternative implementation of the circuit portion relating to the first/second current sources _ISB1 / _ISB2 and the first/third transistors D1/D3. As shown in Figure 3C, the first/second current sources _ISB1 / _ISB2 are implemented as mirror current sources, and the first/third transistors D1/D3 are used for switching control of the mirror current sources. When the first/third transistors D1/D3 are in the on state, the current of the reference current source _ISBN used for the first/second current sources _ISB1 / _ISB2 is generated by the mirror as the mirror current of the first/second driving currents _IB1 / _ISB2 . The current of the reference current source _ISBN is only 1/n of the first driving current _IB1 . When the first/third transistors D1/D3 are in the off state, the current of the reference current source _ISBN is not mirrored. In this case, the current flowing through the first/third transistor D1/D3 is 1/n of the first driving current _IB1 , and the area of the first/third transistor D1/D3 is greatly reduced compared to the case shown in Figure 3A.

Figure 4A shows an example block diagram of the control chip U1A in the drift power converter 100A shown in Figure 1A. Figure 4B shows an example block diagram of the control chip U1B in the drift power converter 100B shown in Figure 1B. For simplicity, control chips U1A and U1B will be referred to as chip U1 from now on. As shown in Figures 4A/4B, the first transistor D1, the second transistor D2, the third transistor D3, the fourth transistor D4, the first pull-down unit, the second pull-down unit, and the switching control circuit 130 are packaged in the same control chip U1. Furthermore, the control chip U1 may also include: a chip power supply circuit 104: connected to the power supply terminal (VDD) pin of the control chip U1, including three parts: undervoltage lockout (UVLO), overvoltage protection (OVP), and reference voltage and reference current (Vref & Iref), used to provide the operating voltage, reference voltage Vref, and reference current Iref to the internal circuit of the chip. When the voltage at the VDD pin exceeds the UVLO voltage, the internal circuit of the chip starts to work. When the voltage at the VDD pin exceeds the OVP threshold, the internal circuit of the chip enters an automatic recovery protection state to prevent damage to the control chip U1.

Feedback control circuit 106: Connected to the feedback (FB) pin of control chip U1, constant voltage (CV) control circuit 108, and logic control circuit 116, including a sampler, operational amplifier (EA), voltage drop compensation, and output overvoltage/undervoltage protection (OVP/Undervoltage Protection, UVP). The sampler generates an output voltage sampling signal based on the output voltage feedback signal received from the auxiliary winding of transformer T, which characterizes the system output voltage on the secondary winding of transformer T, and provides the output voltage sampling signal to the operational amplifier. The operational amplifier generates an error amplification signal based on the output voltage sampling signal and the reference voltage Vref, and provides the error amplification signal to the constant voltage (CV) control circuit 108 and the voltage drop compensation section. The voltage drop compensation section generates a voltage drop compensation signal based on the error amplification signal (this loop is positive feedback). The output OVP and UVP sections generate OVP and UVP signals based on the output voltage feedback signal, and provide the OVP and UVP signals to the logic control circuit 116.

CV control circuit 108: Connected to the CS pin of control chip U1 and the feedback control circuit 106, used to control the output voltage constantness of the primary-side feedback-based turbocharger 100A/100B. Constant Current (CC) control circuit 110: Connected to the FB pin of control chip U1 and the logic control circuit 116, used to control the output current constantness of the primary-side feedback-based turbocharger 100A/100B, and can adjust the magnitude of the output current of the primary-side feedback-based turbocharger 100A/100B by using the current sensing resistor Rs. The current sensing and control circuit 112 is connected to the current sensor (CS) pin of the control chip U1 and the logic control circuit 116. It includes two parts: leading edge blanking (LEB) and overcurrent protection (OCP) comparator, used to implement overcurrent protection for the primary-side feedback-based feedforward switching power converter 100A/100B. The oscillator (OSC) circuit 114 generates a high-frequency zigzag wave signal and provides it to the logic control circuit 116, which then uses it to generate a square wave signal with an adjustable duty cycle. Logic control circuit 116: Used to perform logical analysis on the input signals from various circuit modules and output logical control signals to the switch control circuit 102. Protection circuit 118: Used to automatically restore the control chip U1 to the protection state when abnormal fault information is detected, so as to avoid damage to the control chip U1.

It should be noted that the switching control circuit 130 generates six control signals based on the logic control signals provided by the logic control circuit 116, which are used to control the conduction and cutoff of the first transistor D1 to the sixth transistor D6. The first transistor D1 to the sixth transistor D6 are turned on and off under the control of the switching control circuit 130, thereby forming the first and second driving currents _IB1 and _IB2 . As shown in Figures 1A/1B and 4A/4B, the sensing terminal of the control chip U1 receives the sensing voltage Vcs of the current sensing resistor Rs, the power supply terminal of the control chip U1 receives the voltage provided by the auxiliary winding of the transformer T, and the feedback terminal of the control chip U1 receives the corresponding voltage of the auxiliary winding of the transformer T (i.e., the output voltage feedback signal that characterizes the system output voltage on the secondary winding of the transformer T, which can be a voltage division of the voltage provided by the auxiliary winding). In some embodiments, the first power transistor Q1 and the second power transistor Q2 can be two independent power transistors, or they can be formed in the same chip package, or they can be an integrated Darlington transistor structure; the control chip U1 can be formed in a three-chip package with the first power transistor Q1 and the second power transistor Q2.

Figure 5 shows an example package schematic of the first power transistor Q1 and the second power transistor Q2 of the cruise power converter 100A/100B shown in Figures 1A/1B. As shown in Figure 5, the first power transistor Q1 and the second power transistor Q2 can be included in the same single-base island chip package (wherein the collector of the first power transistor Q1 and the collector of the second power transistor Q2 are connected), and the detailed pin information of the single-base island chip package is as follows: Pin 1 is a first current pin, used to receive a first drive current _IB1 , connected to the base region of the first power transistor Q1; Pin 2 is a second current pin, used to receive a second drive current _IB2 , connected to the emitter region of the first power transistor Q1 and the base region of the second power transistor Q2; The 3/4 pin is the emitter pin, which is connected to the emitter region of the second power transistor Q2. In order to increase the heat dissipation area and reduce the temperature, multiple wire bonding and multi-pin packaging can be used. For example, two pins can be connected by two sets of wire bonding respectively. The specific number of wires in each set of wire bonding can be determined according to the emitter current of the second power transistor Q2. Pins 5-8 are collector pins, connected to the collector regions of the first power transistor Q1 and the second power transistor Q2. For heat dissipation and convenient printed circuit board layout, a multi-pin package is used. The collector regions of the first power transistor Q1 and the second power transistor Q2 are located on the back of the transistors. Therefore, the first power transistor Q1 and the second power transistor Q2 can be connected to the chip island using conductive adhesive without wire bonding, resulting in minimal impedance.

Figure 6 shows an example package schematic of the first power transistor Q1, the second power transistor Q2, and the control chip U1A/U1B of the cruise power converter 100A/100B shown in Figures 1A/1B. As shown in Figure 6, the first power transistor Q1 and the second power transistor Q2 are packaged in a planar configuration, while the control chip U1 and the second power transistor Q2 are packaged in a stacked configuration. The specific package form can be adjusted according to the number and shape of the base islands and is not limited to an 8-pin package. The detailed pin information of the example package shown in Figure 6 is as follows: Pins 1, 2, and 3 are control pins for controlling chip U1 and are connected to the internal pads of control chip U1; Pin 4 is the emitter pin and is connected to the emitter region of the second power transistor Q2. In order to increase the heat dissipation area and reduce the temperature, multiple wire bonding can be used to reduce the wire bonding impedance. The specific number of wires can be determined according to the area of the emitter region of the second power transistor Q2. Pins 5-8 are collector pins, connected to the collector regions of the first and second power transistors Q1 and Q2. For heat dissipation and ease of printed circuit board layout, a multi-pin package is used. The collector regions of the first and second power transistors Q1 and Q2 are located on the back of the transistors and are connected to the base island using conductive adhesive, eliminating the need for wire bonding and minimizing impedance. The example package shown in Figure 6 can add extra pins without increasing system pin costs, resulting in a simpler system circuit, fewer peripheral components, and lower system cost.

Figure 7 shows another example package schematic of the first power transistor Q1 and the second power transistor Q2 of the cruise power converter 100A/100B shown in Figures 1A/1B. As shown in Figure 7, the first power transistor Q1 and the second power transistor Q2 can be included in the same single-base island chip package in the form of an integrated Darlington power transistor, and the detailed pin information of the single-base island chip package is as follows: Pin 1 is a first current pin, used to receive a first driving current _IB1 , and connected to the first base region of the integrated Darlington power transistor, that is, the base region of the first power transistor Q1; Pin 2 is a second current pin, used to receive a second driving current _IB2 , and connected to the second base region of the integrated Darlington power transistor, that is, the emitter region of the first power transistor Q1 and the base region of the second power transistor Q2; Pins 3 and 4 are emitter pins, connected to the emitter region of the second power transistor Q2. To increase the heat dissipation area and reduce the temperature, a multi-wire, multi-pin package can be used, for example, by connecting the two pins through two sets of wire bonding. The specific number of wires in each set of wire bonding needs to be determined according to the emitter current of the second power transistor Q2. Pins 5 to 8 are collector pins, connected to the collector region of the integrated Darlington power transistor. For heat dissipation and PCB layout convenience, a multi-pin package (such as pins 5-8) is used. The collector regions of the first power transistor Q1 and the second power transistor Q2 are located on the back of the transistor and are connected to the base island using conductive adhesive, without the need for wire bonding, resulting in minimal impedance.

The base of the integrated Darlington composite transistor in the example package shown in Figure 7 is an internal lead of the package, which does not add extra leads, does not increase the system lead cost, and the whole system circuit is simple, with few peripheral components and low system cost.

Figures 8A and 8B respectively show two example package schematics of the first power transistor Q1 and the second power transistor Q2, as well as the control chip U1A/U1B of the cruise power converter 100A/100B shown in Figures 1A/1B. As shown in Figures 8A and 8B, the first power transistor Q1 and the second power transistor Q2 are packaged as integrated Darlington power transistors. The control chip U1 and the integrated Darlington power transistors are included in the same chip package. The control chip U1 and the integrated Darlington power transistors can be in an overlay or flat configuration, and the number and shape of the base islands can be adjusted as needed.

As shown in Figure 8A, the integrated Darlington power transistor and control chip U1 are included in a single-base island wafer package in an overlay configuration; as shown in Figure 8B, the integrated Darlington power transistor and control chip U1 are included in a dual-base island wafer package in a planar configuration. The detailed pin information for the chip packages in Figures 8A and 8B is as follows: Pins 1, 2, and 3 control the chip U1; Pin 4 is the emitter pin. To increase the heat dissipation area and reduce the temperature, multiple wire bonding can be used to reduce the wire bonding impedance. The specific number of wires needs to be determined according to the emitter current; Pins 5-8 are connected to the collector region of the integrated Darlington composite transistor. For heat dissipation and convenient printed circuit board layout, a multi-pin package is used. For example, pins 5-8, the collector regions of the first power transistor Q1 and the second power transistor Q2 are located on the back of the transistor and are connected to the base island using conductive adhesive. No wire bonding is required, resulting in minimal impedance. In summary, in the feedback power converter according to this embodiment, four transistors and two pull-down units are used to drive the power transistors, reducing the drive current loss of the power transistors and improving the turn-on speed of the power transistors. Furthermore, by setting a pre-shutdown drive current before the power transistor transitions from the on state to the off state, the number of carriers in the base region during the on state is reduced, allowing for rapid extraction of the remaining few carriers in the base region of the power transistor during turn-off. This improves the turn-off speed, reduces turn-off losses, and thus expands the application range of power transistors in medium-power systems.

This invention can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in a particular embodiment can be modified without departing from the basic spirit of this invention. Therefore, the present embodiments are to be regarded as exemplary rather than limiting in all respects, the scope of this invention is defined by the appended claims rather than the foregoing description, and all changes falling within the meaning and equivalents of the claims are thus included within the scope of this invention.

1, 2, 3, 4, 5, 6, 7, 8, CS, VDD, FB: Pins 100A, 100B: Feedback power converter 102, 130: Switching control circuit 104: Chip power supply circuit 106: Feedback control circuit 108: Constant voltage (CV) control circuit 110: Constant current (CC) control circuit 112: Power sensing control circuit 114: Oscillator (OSC) circuit 116: Logic control circuit 118: Protection circuit D1: First transistor D2: Second transistor D3: Third transistor D4: Fourth transistor D5: Fifth transistor D6: Sixth transistor EA: Operational amplifier GND: Chip reference ground I _B1 : First drive current I _B2 : Second drive current Ic: BJT Class C current Iref: Reference current _IS : Sensing current _ISB1 : First power supply current _ISB2 : Second power supply current _ISBN : Reference power supply current Q1: First power transistor Q2: Second power transistor R1: First resistor R2: Second resistor Rs: Current sensing resistor T: Transformer t1, t2, t3, t3a, t4: Time intervals t1-t3, t1-t2, t2-t3, t3-t4, Ton, Pre_off, Toff: Time period U1: Chip U1A, U1B: Control chip Vcs: Sensing voltage Vo: Output voltage Vref: Reference voltage

The invention can be better understood from the following description of specific embodiments in conjunction with the accompanying drawings, in which: Figure 1A shows an example circuit diagram of a drift power converter according to an embodiment of the invention. Figure 1B shows another example circuit diagram of a drift power converter according to an embodiment of the invention. Figure 2A shows example operating waveforms of multiple signals of the drift power converter shown in Figures 1A/1B. Figure 2B shows another example operating waveform of multiple signals of the drift power converter shown in Figures 1A/1B. Figure 3A shows a schematic diagram of an example alternative implementation of the circuit portion related to the first/second current source and the first/third transistor. Figure 3B shows a schematic diagram of another example alternative implementation of the circuit portion related to the first/second current source and the first/third transistor. Figure 3C shows a schematic diagram of another example alternative implementation of the circuit portion related to the first/second current source and the first/third transistor. Figure 4A shows an example block diagram of the control chip in the drift converter shown in Figure 1A. Figure 4B shows an example block diagram of the control chip in the drift converter shown in Figure 1B. Figure 5 shows an example package schematic diagram of the first and second power transistors of the drift converter shown in Figures 1A/1B. Figure 6 shows an example package schematic diagram of the first and second power transistors and the control chip of the drift converter shown in Figures 1A/1B. Figure 7 shows another example package schematic diagram of the first and second power transistors of the drift converter shown in Figures 1A/1B. Figures 8A and 8B show two example package schematics of the first and second power transistors and the control chip of the cruise power converter shown in Figures 1A/1B, respectively.

100A: Reverse-speed power converter

130: Switch control circuit

CS, VDD, FB: leading edge

D1: First transistor

D2: Second transistor

D3: Third transistor

D4: Fourth transistor

D5: Fifth transistor

D6: Sixth transistor

GND: Chip Reference Location

I _B1 : First driving current

I _B2 : Second drive current

IC: BJT Class C Current

I _S : Induction Current

Q1: First power transistor

Q2: Second power transistor

R1: First resistor

R2: Second resistor

Rs: Resistance measurement using electrical flux

T: Transformer

U1A: Control chip

Vo: Output voltage

Claims (14)

A reflux power converter is characterized by comprising a transformer, a first power transistor, a second power transistor, a first current source, a second current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a first pull-down unit including a first resistor, a second pull-down unit including a second resistor, and a switching control circuit, wherein: the control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor are respectively connected to the switching control circuit; the first current source provides a first driving current under the control of the first transistor; and the second current source provides a second driving current under the control of the third transistor. The first terminal of the second transistor and the first terminal of the first pull-down unit are connected to the base of the first power transistor. The base of the first power transistor also receives the first driving current. The second terminal of the second transistor is grounded or connected to the base of the second power transistor. The emitter of the first power transistor, the second terminal of the first pull-down unit, the first terminal of the fourth transistor, and the first terminal of the second pull-down unit are connected to the base of the second power transistor. The base of the second power transistor also receives the second driving current. The second terminal of the fourth transistor is grounded. The collectors of the first power transistor and the second power transistor are connected to the primary winding of the transformer. The emitter of the second power transistor is grounded through an inductance sensing resistor. The regressive power converter as claimed in claim 1, wherein, during the process of the second power transistor changing from an off state to an on state, and when the second power transistor is in the on state and the sensed voltage on the current sensing resistor is less than a preset voltage value, the first transistor is in the on state to provide the first driving current from the first current source, the third transistor is in the off state to temporarily stop the second current source from providing the second driving current, the second transistor and the fourth transistor are in the off state, and the base current of the second power transistor is provided by the first driving current amplified by the first power transistor. The regressive power converter as claimed in claim 1, wherein, when the second power transistor is in the ON state and the sensed voltage on the current sensing resistor is not less than a preset voltage value, the first transistor is in the OFF state to temporarily stop the first current source from providing the first driving current, the third transistor is in the ON state to provide the second driving current from the second current source, the second transistor and the fourth transistor are in the OFF state, and the base current of the second power transistor is provided by the second driving current and the emitter current of the first power transistor. The regressive power converter as claimed in claim 1, wherein during the process of the second power transistor changing from an on state to an off state, and when the second power transistor is in the off state, the first transistor is in the off state to temporarily stop the first current source from providing the first driving current, the third transistor is in the off state to temporarily stop the second current source from providing the second driving current, and the second transistor and the fourth transistor are in the on state. The regressive power converter as described in claim 1, wherein the first pull-down unit further includes a fifth transistor connected in series with the first resistor, and the second pull-down unit further includes a sixth transistor connected in series with the second resistor, wherein the control terminals of the fifth transistor and the sixth transistor are respectively connected to the switching control circuit. The regressive power converter as described in claim 5, wherein, during the process of the second power transistor changing from an off state to an on state, and when the second power transistor is in the on state and the sensed voltage on the current sensing resistor is less than a preset voltage value, the first transistor is in the on state to provide the first driving current from the first current source, the third transistor is in the off state to temporarily stop the second current source from providing the second driving current, and the second, fourth, fifth, and sixth transistors are in the off state, with the base current of the second power transistor provided by the first driving current. The regressive power converter as described in claim 5, wherein, when the second power transistor is in the ON state and the sensed voltage on the current sensing resistor is not less than a preset voltage value, the first transistor is in the OFF state to temporarily stop the first current source from providing the first driving current, the third transistor is in the ON state to provide the second driving current from the second current source, the second transistor and the fourth transistor are in the OFF state, the fifth transistor and the sixth transistor are in the ON state, and the base current of the second power transistor is provided by the second driving current. The regressive power converter as claimed in claim 5, wherein during the process of the second power transistor changing from an on state to an off state, and when the second power transistor is in the off state, the first transistor is in the off state to temporarily stop the first current source from providing the first driving current, the third transistor is in the off state to temporarily stop the second current source from providing the second driving current, and the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are in the on state. The regressive power converter as claimed in claim 5, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are implemented as N-type metal oxide semiconductor field-effect transistors. The regressive power converter as claimed in claim 1, wherein a first end of the first transistor is connected to the output terminal of the first current source, and a second end of the first transistor is connected to the base of the first power transistor; a first end of the third transistor is connected to the output terminal of the second current source, and a second end of the third transistor is connected to the base of the second power transistor. The regressive power converter as claimed in claim 1, wherein the first current source is implemented as a mirror current source outputting the first driving current, the first transistor is used to implement switching control of the first current source; the second current source is implemented as a mirror current source outputting the second driving current, and the third transistor is used to implement switching control of the second current source. The regressive power converter as claimed in claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the first pull-down unit, the second pull-down unit, and the switching control circuit are packaged in the same control chip. The feedback power converter as described in claim 12, wherein the feedback terminal of the control chip receives the voltage corresponding to the auxiliary winding of the transformer. The regressive power converter as claimed in claim 13, wherein the first power transistor and the second power transistor are in a planar package, and the control chip and the second power transistor are in an overlay package.