TWM675365U - Light emitting driver circuit with multiple output functions - Google Patents

Abstract

A light emitting driver circuit includes an anti-noise control circuit, a charging circuit, an output transistor, a pull-down circuit and an output circuit. The anti-noise control circuit adjusts the voltage level of an output node thereof to have a low voltage level or a high voltage level according to first and second stage transmission signals and the voltage level of a pre-charged node. The charging circuit is controlled by the first stage transmission signal to charge the pre-charged node according to a first voltage. The output transistor has a first terminal, a second terminal providing the second stage transmission signal, and a control terminal coupled to the pre-charged node. The pull-down circuit determines whether to pull down the voltage level of the pre-charged node and the second terminal of the output transistor according to the voltage level of the output node. The output circuit generates, in accordance with the first voltage and the voltage level of the pre-charged node, a light-emitting driving signal in which the width of the pulse and the number of pulses change with the voltage level of the pre-charged node.

Description

Light-emitting driver circuit with multiple output functions

The present invention relates to a driver, in particular to a light-emitting driver circuit with multiple output functions for a gate drive unit of a self-luminous display.

With advancements in display technology, self-luminous displays, such as organic light-emitting diode (OLED) displays, micro-LED displays, and micro-OLED displays, have become the target of next-generation display technology development due to their advantages such as high brightness, high contrast, and fast response time.

Conventional self-luminous displays primarily comprise a display panel, a source driver, and a gate driver. The display panel includes multiple pixel circuits and multiple light-emitting elements (i.e., sub-pixels). The source driver provides multiple display data signals to the pixel circuits via multiple source lines. The gate driver comprises multiple gate driver units, each of which includes a shift register and a light-emitting driver circuit. The shift register is used to provide a gate drive signal (or scan signal) to the corresponding pixel circuits to control the corresponding display data signals to be written into the corresponding pixel circuits. The light-emitting driver circuit is used to provide a light-emitting drive signal to the corresponding pixel circuits to control the conduction of each light-emitting control element in the corresponding pixel circuit, so that the corresponding light-emitting element is driven by voltage to emit light.

However, different light-emitting elements require different luminescence times, and the transistors used to provide a cascade signal in the light-emitting driver circuit will degrade over time. In addition, when the light-emitting frequency of the light-emitting element is too low (for example, below 30Hz or 60Hz), it will cause the human eye to easily perceive a flickering sensation when viewing the display, resulting in a flickering screen phenomenon.

Therefore, it is crucial to provide a light-emitting driving circuit that can generate a light-emitting driving signal with adjustable pulse width and pulse quantity, while preventing the transistor providing the cascade signal from degrading during long-term operation.

In view of this, the present invention provides a novel light-emitting driver circuit with multiple output functions, which can effectively solve the above-mentioned problems.

The novel light-emitting driver circuit with multiple output functions is suitable for a gate driver unit of a self-luminous display. The light-emitting driver circuit includes: an anti-noise control circuit, which receives a first cascade signal and a second cascade signal, has an output node, and is coupled to a pre-charge node. The anti-noise control circuit controls the output of the first cascade signal, the second cascade signal, and the pre-charge node according to the voltage of the first cascade signal, the second cascade signal, and the pre-charge node. voltage level, adjusting the voltage level of the output node to have a low voltage level or a high voltage level; a charging circuit, receiving a first voltage and the first cascade signal, coupled to the pre-charge node, and controlled by the first cascade signal to charge the pre-charge node according to the first voltage; an output transistor, having a first end receiving a clock signal, a first end coupled to the anti-noise control circuit and The second cascade signal is provided to the second terminal of the anti-noise control circuit and a control terminal coupled to the pre-charge node; a pull-down circuit is coupled to the pre-charge node, the output node of the anti-noise control circuit and the second terminal of the output transistor, and determines whether to respectively increase the voltage level of the second terminal of the output transistor and the voltage level of the pre-charge node according to the voltage level of the output node. The self-luminous display comprises a first circuit configured to pull the first voltage down to a second voltage and a third voltage; and an output circuit configured to receive the first voltage and be coupled to the pre-charge node. The output circuit generates a light-emitting driving signal according to the first voltage and the voltage level of the pre-charge node and outputs the signal to a plurality of light-emitting control elements in the self-luminous display. The pulse width and the number of pulses of the light-emitting driving signal vary with the voltage level of the pre-charge node.

In one embodiment, the light-emitting driver circuit as described above, wherein: when the output node of the anti-noise control circuit switches from having the low voltage level to having the high voltage level, the pull-down circuit pulls down the voltage level of the second end of the output transistor to the second voltage and the voltage level of the pre-charge node to the third voltage according to the voltage level of the output node; and the first voltage is a high voltage, the second voltage and the third voltage are each a low voltage, and the second voltage is greater than the third voltage.

In one embodiment, in the aforementioned light-emitting driving circuit, when the anti-noise control circuit causes the output node to have the low voltage level based on the first cascade signal, the second cascade signal, and the voltage level of the pre-charge node, the light-emitting driving signal has a high level; and when the anti-noise control circuit causes the output node to have the high voltage level based on the first cascade signal, the second cascade signal, and the voltage level of the pre-charge node, the light-emitting driving signal has a low level.

In one embodiment, the aforementioned light-emitting driver circuit further includes: a capacitor coupled between the pre-charge node and the second terminal of the output transistor.

In one embodiment, the light-emitting driver circuit as described above, wherein the anti-noise control circuit includes: a first transistor having a first end receiving the first voltage, a second end, and a control end coupled to the first end; a second transistor having a first end receiving the first voltage, a second end coupled to the output node, and a control end coupled to the second end of the first transistor; a third transistor having a first end coupled to the second end of the first transistor, a second end receiving the second voltage, and a control end receiving the second cascade signal; a fourth transistor having a first end coupled to the second end of the first transistor, a second end receiving the second voltage, and a control end receiving the first cascade signal; and a fifth transistor having a first end coupled to the output node, a second end receiving the third voltage, and a control end coupled to the pre-charge node.

In one embodiment, the light-emitting driver circuit as described above, wherein the charging circuit includes: a sixth transistor having a first end receiving the first voltage, a second end coupled to the pre-charge node, and a control end receiving the first cascade signal.

In one embodiment, the light-emitting driver circuit as described above, wherein the pull-down circuit includes: a seventh transistor having a first end coupled to the pre-charge node, a second end, and a control end coupled to the output node of the anti-noise control circuit; an eighth transistor having a first end coupled to the second end of the seventh transistor, a second end receiving the third voltage, and a control end coupled to the control end of the seventh transistor; a ninth transistor having a first end coupled to the second end of the output transistor, a second end receiving the second voltage, and a control end coupled to the control end of the seventh transistor; and a tenth transistor having a first end coupled to the pre-charge node, a second end receiving the first cascade signal, and a control end receiving a third cascade signal.

In one embodiment, the light-emitting driving circuit as described above, wherein the output circuit includes: a first inverter, receiving the first voltage and coupled to the pre-charge node, and generating an inverter signal based on the first voltage and the voltage level of the pre-charge node; and a second inverter, receiving the first voltage and coupled to the first inverter to receive the inverter signal, and generating the light-emitting driving signal based on the first voltage and the inverter signal.

In one embodiment, the light-emitting driving circuit as described above, wherein the first inverter includes: an eleventh transistor having a first end providing the inverter signal, a second end receiving the second voltage, and a control end coupled to the pre-charge node; and a twelfth transistor having a first end receiving the first voltage, a second end coupled to the first end of the eleventh transistor, and a control end coupled to its own first end.

In one embodiment, the light-emitting driving circuit as described above, wherein the second inverter includes: a thirteenth transistor having a first end, a second end receiving the second voltage, and a control end coupled to the first inverter to receive the inverter signal; a fourteenth transistor having a first end coupled to the thirteenth transistor and providing the first end of the light-emitting driving signal, a second end receiving the second voltage, and a control end coupled to the thirteenth transistor. a control terminal coupled to the control terminal of the thirteenth transistor; a fifteenth transistor having a first terminal receiving the first voltage, a second terminal, and a control terminal coupled to the first terminal; a sixteenth transistor having a first terminal receiving the first voltage, a second terminal coupled to the first terminal of the fourteenth transistor, and a control terminal coupled to the second terminal of the fifteenth transistor; and a capacitor coupled between the first terminal of the thirteenth transistor and the second terminal of the fifteenth transistor.

The effectiveness of this novel device lies in: pulling down the voltage level of the pre-charge node to the third voltage, and pulling down the voltage level of the second end of the output transistor to the second voltage, so that the gate-source voltage difference of the output transistor is a small negative bias. This can release and discharge electrons accumulated in defects in the output transistor interface, thereby restoring the life of the output transistor or ensuring that the output transistor is properly turned off, preventing the output transistor from leaking due to inadvertent turning on, improving the performance degradation of the output transistor under long-term operation, and enhancing the reliability of the light-emitting driver circuit.

The present invention will be described in detail through the following embodiments and the accompanying drawings to help those skilled in the art understand the purpose, features and efficacy of the present invention. It should be noted that in the following description and the scope of the patent application, the terms "including" and "comprising" are used in an open manner and should not be interpreted as closed terms such as "consisting of..." In addition, the term "coupled" is intended to indicate indirect or direct coupling. Therefore, if one device is coupled to another device, the connection can be through direct coupling or through indirect coupling via other devices and connections. In addition, in the content described in the present invention, terms such as "first", "second" and "third" are used to distinguish between components/signals, rather than to limit the components/signals themselves or to indicate a specific order of components/signals.

Referring to FIG1 , a schematic diagram of a self-luminous display 1 including a light-emitting driver circuit 6 with multiple output functions according to the present invention is shown. Examples of self-luminous display 1 include, but are not limited to, organic light-emitting diode (OLED) displays, micro-LED displays, and micro-OLED displays. Self-luminous display 1 includes a display panel 2, a source driver device 3, a gate driver device 4, and other necessary components.

The display panel 2 includes a plurality of pixel circuits 21 and a plurality of light-emitting diodes 22 (i.e., sub-pixels). The pixel circuits 21 of the display panel 2 are arranged in a matrix to form a pixel array, but are not limited to this. As is generally known to those skilled in the art, each pixel circuit 21 includes a plurality of semiconductor switching elements and at least one storage capacitor, wherein the semiconductor switching elements may be thin-film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSFETs). For example, the architecture of each pixel circuit 21 is 6T1C, 7T1C, 7T2C, 8T1C, or 8T2C.

Referring further to FIG. 2 , a circuit diagram of each pixel circuit 21 shown in FIG. 1 is provided as an example, but is not limited thereto. Pixel circuit 21 includes a drive transistor 211, a display data write transistor 212, a storage capacitor C1, and a light-emitting control transistor 213. Each of the drive transistor 211, the display data write transistor 212, and the light-emitting control transistor 213 can be a TFT element or a MOSFET element. Specifically, the drive transistor 211 has a first terminal, a second terminal coupled to the anode of the light-emitting diode 22, and a control terminal (or gate terminal) coupled to the first terminal of the storage capacitor C1. The display data write transistor 212 has a first terminal for receiving a display data signal Vdata, a second terminal coupled to the control terminal of the drive transistor 211, and a control terminal for receiving a gate drive signal G[n]. The light-emitting control transistor 213 has a first terminal for receiving a supply voltage VDD, a second terminal coupled to the first terminal of the drive transistor 211, and a control terminal for receiving a light-emitting drive signal EM[n].

The source driving device 3 is coupled to a plurality of source lines (or data lines) 23 of the display panel 2 , and provides a plurality of display data signals Vdata to each of the pixel circuits 21 via the source lines 23 .

The gate driver device 4 is coupled to a plurality of gate lines (or scan lines) 24 of the display panel 2. The gate driver device 4 can scan the gate lines 24 of the display panel 2 and is implemented in a gate driver on array (GOA) design. The gate driver device 4 includes a plurality of gate driver units 5. Each of the gate driver units 5 can generate a gate drive signal (or scan signal) in a column-sequential manner to drive at least one gate line connected to each pixel row. Each of the gate drive units 5 includes a shift register (not shown) and a light-emitting driver circuit 6 according to the present invention. The shift registers can be divided into a first-stage shift register, a second-stage shift register, ..., and an N-stage shift register according to the driving sequence. The shift register (or n-stage shift register, where n and N are positive integers) is used to provide a gate drive signal G[n] to the corresponding pixel circuits 21 via one of the gate lines, thereby controlling the corresponding display data signals Vdata to be written into the corresponding pixel circuits 21. Furthermore, the shift register provides a carry signal (or a replica signal) that serves as a frame start signal (STV) for the next-stage (i.e., the n+1th) shift register to initiate scanning of the corresponding gate line. The novel light-emitting driver circuit 6 (or the nth-stage light-emitting driver circuit) provides a light-emitting driver signal EM[n] to the corresponding pixel circuits 21 to control the conduction of the light-emitting control transistor 213 (i.e., the light-emitting control element) in each corresponding pixel circuit 21, causing each corresponding light-emitting diode 22 to emit light due to voltage drive. It should be noted that eight clock signals are used in the timing operation of the gate driver device 4. These clock signals have a 25% overlap, and the waveform distribution of the light-emitting drive signals generated by the light-emitting drive circuits 6 in the gate driver units 5 is a gradient distribution. Furthermore, the detailed circuit configuration and operation of each shift register are well known to those skilled in the art and will not be detailed here for the sake of brevity.

For details, refer to Figures 3 and 4. Figure 3 illustrates an embodiment of the novel light-emitting driver circuit 6 with multiple output functions. Figure 4 is a circuit diagram illustrating an anti-noise control circuit, a charging circuit, a pull-down circuit, and an output circuit of the embodiment. The light-emitting driver circuit 6 is suitable for the gate driver unit 5 of the self-luminous display 1. For ease of explanation, this embodiment uses the n-th stage light-emitting driver circuit (6) in the n-th stage gate driver unit (5) as an example. The detailed circuit configuration and operation of the first to (n-1)th light-emitting driver circuits, and the (n+1)th to Nth light-emitting driver circuits are similar to those of the nth light-emitting driver circuit and are not described here for brevity.

The light-emitting driving circuit 6 includes an anti-noise control circuit 61, a charging circuit 62, an output transistor 63, a capacitor 64, a pull-down circuit 65, and an output circuit 66.

The anti-noise control circuit 61 receives a first cascade signal Carry[n-4] (or the (n-4)th stage cascade signal) and a second cascade signal Carry[n] (or the nth stage cascade signal), and has an output node N1 coupled to a pre-charge node A. The anti-noise control circuit 61 adjusts the voltage level of the output node N1 to a low voltage level or a high voltage level based on the voltage levels of the first cascade signal Carry[n-4], the second cascade signal Carry[n], and the pre-charge node A. Specifically, when the anti-noise control circuit 61 causes the output node N1 to have a low voltage level based on the first cascade signal Carry[n-4], the second cascade signal Carry[n], and the voltage level of the pre-charge node A, the anti-noise control circuit 61 controls the output circuit 66 to not perform anti-noise operation, resulting in the emission drive signal EM[n] having a high level. When the anti-noise control circuit 61 causes the output node N1 to have a high voltage level based on the first cascade signal Carry[n-4], the second cascade signal Carry[n], and the voltage level of the pre-charge node A, the anti-noise control circuit 61 controls the output circuit 66 to perform anti-noise operation, resulting in the emission drive signal EM[n] having a low level. It should be noted that the first cascade signal Carry[n-4] is provided by the (n-4)th shift register of the (n-4)th gate driver unit, where n is a positive integer greater than 4. If the (n-4)th gate driver unit is the first-stage gate driver unit, the first cascade signal Carry[n-4] is generated by the first-stage shift register based on a vertical start signal STV (scanning pulse) provided by a timing control device (not shown) in the self-luminous display 1. In this embodiment, the anti-noise control circuit 61 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

The first transistor T1 has a first end receiving a first voltage VGH, a second end, and a control end coupled to the first end thereof. The second transistor T2 has a first end receiving the first voltage VGH, a second end coupled to the output node N1, and a control end coupled to the second end of the first transistor T1. The third transistor T3 has a first end coupled to the second end of the first transistor T1, a second end receiving a second voltage VGL, and a control end receiving the second cascade signal Carry[n]. The fourth transistor T4 has a first end coupled to the second end of the first transistor T1, a second end receiving the second voltage VGL, and a control end receiving the first cascade signal Carry[n-4]. The fifth transistor T5 has a first end coupled to the output node N1, a second end receiving a third voltage VGLL, and a control end coupled to the pre-charge node A. In this embodiment, the first voltage VGH is a high voltage, and the second voltage VGL and the third voltage VGLL are each a low voltage. The first voltage VGH (e.g., 15V) is greater than the second voltage VGL (e.g., -12V), and the second voltage VGL is greater than the third voltage VGLL (e.g., -18V), but the present invention is not limited thereto.

The charging circuit 62 receives a first voltage VGH and a first cascade signal Carry[n-4], is coupled to the pre-charge node A, and is controlled by the first cascade signal Carry[n-4] to charge the pre-charge node A according to the first voltage VGH. In this embodiment, the charging circuit 62 includes a sixth transistor T6. The sixth transistor T6 has a first terminal receiving the first voltage VGH, a second terminal coupled to the pre-charge node A, and a control terminal receiving the first cascade signal Carry[n-4].

The output transistor 63 has a first end for receiving a clock signal CLK[n], a second end coupled to the third transistor T3 of the anti-noise control circuit 61 and providing a second cascade signal Carry[n] to the control end of the third transistor T3, and a control end coupled to the pre-charge node A.

The capacitor 64 is coupled between the pre-charge node A and the second terminal of the output transistor 63 .

The pull-down circuit 65 is coupled to the pre-charge node A, the output node N1 of the anti-noise control circuit 61, and the second terminal of the output transistor 63. The pull-down circuit 65 determines whether to pull down the voltage level of the second terminal of the output transistor 63 and the voltage level of the pre-charge node A to the second voltage VGL and the third voltage VGLL, respectively, based on the voltage level of the output node N1. When the output node N1 of the anti-noise control circuit 61 switches from a low voltage level to a high voltage level, the pull-down circuit 65 pulls down the voltage level of the second terminal of the output transistor 63 to the second voltage VGL and the voltage level of the pre-charge node A to the third voltage VGLL, based on the voltage level of the output node N1. In this embodiment, the pull-down circuit 65 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.

The seventh transistor T7 has a first end coupled to the pre-charge node A, a second end, and a control end coupled to the output node N1 of the anti-noise control circuit 61. The eighth transistor T8 has a first end coupled to the second end of the seventh transistor T7, a second end receiving the third voltage VGLL, and a control end coupled to the control end of the seventh transistor T7. The ninth transistor T9 has a first end coupled to the second end of the output transistor 63, a second end receiving the second voltage VGL, and a control end coupled to the control end of the seventh transistor T7. The tenth transistor T10 has a first end coupled to the pre-charge node A, a second end receiving the first cascade signal Carry[n-4], and a control end receiving a third cascade signal Carry[n+4] (or the (n+4)th stage cascade signal). The third cascade signal Carry[n+4] is provided by the (n+4)th stage shift register of the (n+4)th stage gate driver unit.

The output circuit 66 receives the first voltage VGH and is coupled to the pre-charge node A. Based on the first voltage VGH and the voltage level of the pre-charge node A, it generates an emission drive signal EM[n] and outputs it to each corresponding emission control transistor 213 (i.e., a plurality of emission control elements) in the display panel 2. The pulse width and number of the emission drive signal EM[n] vary with the voltage level of the pre-charge node A. In this embodiment, the output circuit 66 includes a first inverter 661 and a second inverter 662.

The first inverter 661 receives the first voltage VGH and is coupled to the pre-charge node A. It generates an inverter signal Is based on the first voltage VGH and the voltage level of the pre-charge node A. In this embodiment, the first inverter 661 includes an eleventh transistor T11 and a twelfth transistor T12. The eleventh transistor T11 has a first terminal for providing the inverter signal Is, a second terminal for receiving the second voltage VGL, and a control terminal coupled to the pre-charge node A. The twelfth transistor T12 has a first terminal for receiving the first voltage VGH, a second terminal coupled to the first terminal of the eleventh transistor T11, and a control terminal coupled to its own first terminal.

The second inverter 662 receives the first voltage VGH and is coupled to the first inverter 661 to receive the inverting signal Is. The second inverter 662 generates the light-emitting driving signal EM[n] based on the first voltage VGH and the inverting signal Is. In this embodiment, the second inverter 662 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a capacitor C2.

The thirteenth transistor T13 has a first terminal, a second terminal receiving the second voltage VGL, and a control terminal coupled to the first inverter 661 to receive the inverting signal Is. The fourteenth transistor T14 has a first terminal coupled to the first terminal of the thirteenth transistor T13 and providing the light-emitting drive signal EM[n], a second terminal receiving the second voltage VGL, and a control terminal coupled to the control terminal of the thirteenth transistor T13. The fifteenth transistor T15 has a first terminal receiving the first voltage VGH, a second terminal, and a control terminal coupled to its first terminal. The sixteenth transistor T16 has a first terminal receiving the first voltage VGH, a second terminal coupled to the first terminal of the fourteenth transistor T14, and a control terminal coupled to the second terminal of the fifteenth transistor T15. The capacitor C2 is coupled between the first terminal of the thirteenth transistor T13 and the second terminal of the fifteenth transistor T15.

It should be noted that each of the first to sixteenth transistors T1 to T16 (T1-T16) and the output transistor 63 is an N-type metal oxide semiconductor field effect transistor, wherein the drain, source, and gate are the first end, second end, and control end of each of the first to sixteenth transistors T1 to T16 (T1-T16) and the output transistor 63, respectively.

The following describes the operation of the light-emitting driver circuit 6 during each driving period. FIG5 shows waveforms of the clock signal CLK[n], the first cascade signal Carry[n-4], the second cascade signal Carry[n], the third cascade signal Carry[n+4], and the light-emitting driver signal EM[n] of the light-emitting driver circuit 6 of the embodiment shown in FIG4 . Each of the clock signal CLK[n], the first cascade signal Carry[n-4], the second cascade signal Carry[n], and the third cascade signal Carry[n+4] is implemented as an alternating current (AC) signal and has a high level of 15V and a low level of -12V. 4 and 5 , the driving period of this embodiment may include a pre-charge period t1, a bootstrap period t2, a pulse width modulation period t3, and a potential pull-down period t4.

During the pre-charge period t1, the output transistor 63, the first transistor T1, the fourth transistor T4 to the sixth transistor T6 (T4-T6), the eleventh transistor T11, the twelfth transistor T12, the fifteenth transistor T15, and the sixteenth transistor T16 are turned on; the second transistor T2, the third transistor T3, the seventh transistor T7 to the tenth transistor T10 (T7-T10), the thirteenth transistor T13, and the fourteenth transistor T14 are not turned on.

Specifically, during the pre-charge period t1, since the first cascade signal Carry[n-4] is high, the fourth transistor T4 and the sixth transistor T6 are turned on. At this time, the first voltage VGH is written to the pre-charge node A via the sixth transistor T6 to charge it, causing the voltage level of the pre-charge node A to be high. This, in turn, turns on the fifth transistor T5 and the eleventh transistor T11. Since the fifth transistor T5 is turned on, the voltage level of node B is pulled down to the third voltage VGLL. Furthermore, since the fourth transistor T4 is turned on, the voltage level of node D is pulled down to the second voltage VGL, rendering the second transistor T2 non-conductive. At this point, the voltage level of the output node N1 is at the low voltage level. Since the voltage level of the output node N1 is at the low voltage level, the seventh to ninth transistors T7 to T9 (T7-T9) are not conducting, so that the pre-charge node A remains at a high level, and thus the eleventh transistor T11 remains conducting. Since the eleventh transistor T11 is turned on, the voltage level of the node C is pulled down to the second voltage VGL, causing the thirteenth transistor T13 and the fourteenth transistor T14, which serve as anti-noise elements, to be turned off (i.e., the anti-noise control circuit 61 controls the output circuit 66 to not perform an anti-noise operation). At this time, the sixteenth transistor T16 is turned on, causing the first voltage VGH to be written through the sixteenth transistor T16. Therefore, during the pre-charge period t1, the light-emitting driving circuit 6 begins to output the light-emitting driving signal EM[n] having a high level.

During the self-start period t2, the output transistor 63, the first transistor T1, the third transistor T3, the fifth transistor T5, the eleventh transistor T11, the twelfth transistor T12, the fifteenth transistor T15, and the sixteenth transistor T16 are turned on; the second transistor T2, the fourth transistor T4, the sixth transistor T6 to the tenth transistor T10 (T6-T10), the thirteenth transistor T13, and the fourteenth transistor T14 are not turned on.

Specifically, during the self-lift period t2, the first cascade signal Carry[n-4] switches to a low level, rendering the sixth transistor T6 non-conductive. At this point, the self-lift effect of capacitor 64 raises the voltage level of pre-charged node A to a level higher than the first voltage VGH, causing output transistor 63 to remain conductive. At this point, clock signal CLK[n] switches to a high level, and clock signal CLK[n] is written into output transistor 63. Therefore, the second terminal of output transistor 63 begins to output the second cascade signal Carry[n] at a high level. Since the second cascade signal Carry[n] is at a high level, the third transistor T3 is turned on, causing the voltage level at node D to be continuously pulled down to the second voltage VGL. As a result, the second transistor T2 is continuously turned off. Moreover, since the fifth transistor T5 is continuously turned on, the voltage level at node B is continuously pulled down to the third voltage VGLL. Consequently, the voltage level at the output node N1 continues to have this low voltage level. Since the voltage level of the output node N1 continues to have the low voltage level, the seventh to ninth transistors T7 to T9 (T7-T9) continue to be non-conductive, causing the pre-charge node A to continue to be maintained at a high level, so that the eleventh transistor T11 continues to be conductive. As a result, the thirteenth transistor T13 and the fourteenth transistor T14 continue to be non-conductive (i.e., the anti-noise control circuit 61 continues to control the output circuit 66 not to perform the anti-noise operation). At this time, the sixteenth transistor T16 continues to be conductive, so that the first voltage VGH continues to be written through the sixteenth transistor T16. Therefore, during the self-lifting period t2, the light-emitting driving circuit 6 continues to output the light-emitting driving signal EM[n] having a high level.

During the pulse width modulation period t3, the output transistor 63, the first transistor T1, the fourth transistor T4 to the sixth transistor T6 (T4-T6), the tenth transistor T10 to the twelfth transistor T12 (T10-T12), the fifteenth transistor T15, and the sixteenth transistor T16 are turned on; the second transistor T2, the third transistor T3, the seventh transistor T7 to the ninth transistor T9 (T7-T9), the thirteenth transistor T13, and the fourteenth transistor T14 are not turned on.

Specifically, during pulse width modulation period t3, since the first cascade signal Carry[n-4] and the third cascade signal Carry[n+4] switch to a high level, the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are turned on, and the first voltage VGH is written into the pre-charge node A via the sixth transistor T6. Furthermore, the first cascade signal Carry[n-4] is written into the pre-charge node A via the tenth transistor T10. At this time, since the high level (15V) of the first cascade signal Carry[n-4] is the same as the first voltage VGH (15V), the voltage level of the pre-charge node A returns from a higher potential than the first voltage VGH to the first voltage VGH. Since the fourth transistor T4 is turned on, the voltage level at node D is continuously pulled down to the second voltage VGL, causing the second transistor T2 to remain non-conductive. Furthermore, since the fifth transistor T5 remains on, the voltage level at node B is continuously pulled down to the third voltage VGLL, causing the voltage level at output node N1 to remain at a low voltage. Since the voltage level at output node N1 remains at a low voltage, the seventh through ninth transistors T7 through T9 (T7-T9) remain non-conductive, causing pre-charge node A to remain at a high voltage. Consequently, the output transistor 63 and the eleventh transistor T11 remain conductive. At this time, since the clock signal CLK[n] switches to a low level, the second end of the output transistor 63 outputs the second cascade signal Carry[n] having a low level. Furthermore, since the eleventh transistor T11 remains on, the thirteenth transistor T13 and the fourteenth transistor T14 remain off (i.e., the anti-noise control circuit 61 continues to control the output circuit 66 to not perform an anti-noise operation), and the sixteenth transistor T16 remains on, causing the first voltage VGH to continue to be written through the sixteenth transistor T16. Therefore, during the pulse width modulation period t3, the light-emitting driver circuit 6 continues to output the light-emitting driver signal EM[n] having a high level.

During the pull-down period t4, the output transistor 63, the first transistor T1, the second transistor T2, the seventh transistor T7 to the tenth transistor T10 (T7-T10), and the twelfth transistor T12 to the sixteenth transistor T16 (T12-T16) are turned on; the third transistor T3 to the sixth transistor T6 (T3-T6) and the eleventh transistor T11 are not turned on.

Specifically, during the pull-down period t4, the clock signal CLK[n] switches to a low level, causing the voltage level of the second cascade signal Carry[n] to be pulled down. Simultaneously, since the first cascade signal Carry[n-4] is at a low level, the third cascade signal Carry[n+4] switches to a high level, turning on the tenth transistor T10. The voltage level of the pre-charge node A is gradually pulled down to a low level (-12V) through the tenth transistor T10. Furthermore, since the first cascade signal Carry[n-4] is at a low level and the second cascade signal Carry[n] and the voltage level of the pre-charge node A are pulled down to a low level, the third to fifth transistors T3 to T5 (T3-T5) are non-conductive, causing the voltage levels of nodes B and D to be raised to the first voltage VGH. Consequently, the voltage level of the output node N1 switches from having the low voltage level to having the high voltage level. Furthermore, the seventh to ninth transistors T7 to T9 (T7-T9) switch from being non-conductive to being conductive, causing the second cascade signal Carry[n] and the voltage level of the pre-charge node A to remain at a low level. Because the voltage level of pre-charge node A is low, the eleventh transistor T11 is non-conductive, causing the voltage level of node C to be charged to the first voltage VGH. This causes the thirteenth transistor T13 and the fourteenth transistor T14 to be conductive (i.e., the anti-noise control circuit 61 controls the output circuit 66 to perform an anti-noise operation), thereby pulling the level of the emission drive signal EM[n] down to the second voltage VGL. Therefore, during the pull-down period t4, the emission drive circuit 6 outputs the emission drive signal EM[n] at a low level.

Furthermore, during the period from the potential pull-down period t4 to the next pre-charge period t1 (i.e., as shown in time period t10 in FIG5 ), since the output node N1 of the anti-noise control circuit 61 has a high voltage level, the seventh transistor T7 to the ninth transistor T9 (T7-T9) are turned on, causing the voltage level of the second end of the output transistor 63 to be pulled down to the second voltage VGL. , and the voltage level of the pre-charge node A (i.e., the control terminal of the output transistor 63) is pulled down to the third voltage VGLL (at this time, the thirteenth transistor T13 and the fourteenth transistor T14 continue to be turned on, and the anti-noise control circuit 61 continues to control the output circuit 66 to perform anti-noise operation, so that the sixteenth transistor T16 will not leak or turn on randomly). In this case, when the output transistor 63 is made of amorphous silicon (a-Si), when the voltage level of the control terminal of the output transistor 63 is pulled down to the third voltage VGLL (-18V), and the voltage level of the second terminal of the output transistor 63 is pulled down to the second voltage VGL (-12V), the gate-source voltage difference of the output transistor 63 is a negative bias voltage (-18-(-12)=-6V), which can cause the interface defect of the output transistor 63. The electrons accumulated in the trap are released and discharged. When the output transistor 63 is switched on next time, there are no extra electrons to make it difficult for the carrier channel to form. The corresponding electrical performance of the output transistor 63 is that its critical voltage (Vth) drifts to the left (i.e., Vth shifts to the negative direction). This can restore the life of the output transistor 63 (extend the life) and prevent the performance of the output transistor 63 from being degraded and shortened under long-term operation. In addition, when the output transistor 63 is a depletion-mode transistor made of indium gallium zinc oxide (IGZO), the output transistor 63 is depleted. When a gate bias is applied to the output transistor 63 (the channel is conductive when no gate bias is applied), the voltage level of the control terminal of the output transistor 63 is pulled down to the third voltage VGLL (-18V), and the voltage level of the second terminal of the output transistor 63 is pulled down to the second voltage VGL (-12V). This design ensures that the gate-source voltage difference of the output transistor 63 is a small negative bias (-18-(-12)=-6V). This ensures that the output transistor 63 can still be properly turned off even when the critical voltage Vth is less than zero (e.g., -2V). This prevents the output transistor 63 from being turned on and leaking. This improves the performance degradation of the output transistor 63 during long-term operation, thereby enhancing the reliability of the light-emitting driver circuit 6.

In addition, as can be seen from the above, in the operation sequence of the light-emitting driver circuit 6, by switching between the self-starting period t2 and the pulse width modulation period t3 after the pre-charging period t1, the voltage level of the pre-charging node A is kept at a high level. In this way, the light-emitting driver circuit 6 can continuously output a high-level light-emitting driver signal EM[n]. When the voltage level of the pre-charging node A changes from a high level to a low level, the light-emitting driver circuit 6 can continuously output a high-level light-emitting driver signal EM[n]. The light-emitting driver circuit 6 outputs a low-level light-emitting driver signal EM[n]. In other words, by adjusting the number of times the self-starting period t2 and the pulse width modulation period t3 are alternately operated, the width of each pulse in the light-emitting driver signal EM[n] can be changed. This allows the light-emitting driver circuit 6 to achieve a pulse width adjustable function for the light-emitting driver signal EM[n], thereby meeting the different light-emitting time requirements of different light-emitting elements. In other words, researchers can determine the number of pulses in the first-stage cascade signal Carry[n-4] corresponding to the self-carrying period t2 and the pulse width modulation period t3 based on the pulse width required by the luminescence drive signal EM[n], allowing the luminescence drive circuit 6 to achieve the function of adjusting the pulse width of the generated luminescence drive signal EM[n]. Furthermore, by adjusting the number of pre-charging operations t1 performed by the light-emitting driver circuit 6 during a display frame, the number of pulses of the light-emitting driver signal EM[n] during the display frame can be adjusted, thereby enabling the light-emitting driver circuit 6 to achieve a function of adjusting the number of pulses of the light-emitting driver signal EM[n] generated. Furthermore, as the number of pulses increases, the light-emitting driver signal EM[n] can exhibit a better suppression effect on the flickering phenomenon of the display, thereby improving the flicker perception.

It should be noted that the number of operations during the pre-charge period t1 is related to the number of periods during which the first cascade signal Carry[n-4] switches between a high level and a low level in a display frame. For example, Figure 5 shows a waveform diagram corresponding to a display frame. The first cascade signal Carry[n-4] switches between a high level and a low level during two periods t11 and t12 in the display frame. Therefore, the number of operations during the pre-charge period t1 is two, and the number of pulses of the luminescence drive signal EM[n] during the display frame is two, but this is not limited to this. In this embodiment, the first cascade signal Carry[n-4] is generated by the first stage shift register according to the vertical start signal STV provided by the timing control device (not shown) in the self-luminous display 1. The number of time periods during which the first cascade signal Carry[n-4] switches between the high level and the low level depends on the number of vertical start signal STV in one display period. Pulse. That is, by adjusting the number of pulses of the vertical start signal STV in a frame display cycle, the number of time periods (e.g., periods t11 and t12) during which the first cascade signal Carry[n-4] switches between high and low levels in a frame display cycle can be adjusted. This, in turn, adjusts the number of operations during the pre-charge period t1, thereby changing the number of pulses of the luminous drive signal EM[n]. In other words, researchers can determine the number of pulses of the vertical start signal STV based on the number of pulses required by the light-emitting drive signal EM[n] to change the number of time periods during which the first cascade signal Carry[n-4] switches between high and low levels during a frame display cycle, allowing the light-emitting drive circuit 6 to achieve the function of adjusting the number of pulses of the light-emitting drive signal EM[n].

In summary, the above provides a light-emitting driver circuit 6 with multiple output functions that can generate a light-emitting driver signal EM[n] with adjustable pulse width and pulse number, and prevents the output transistor 63 providing the second cascade signal Carry[n] from degrading during long-term operation.

This invention has been disclosed above using preferred embodiments. However, those skilled in the art should understand that these embodiments are intended only to illustrate the invention and should not be construed as limiting its scope. It should be noted that any equivalent variations and substitutions to these embodiments are intended to be encompassed by this invention. Therefore, the scope of protection for this invention shall be determined by the scope of the patent application.

1: Self-luminous display 2: Display panel 3: Source driver 4: Gate driver 5: Gate driver unit 6: Luminescent driver circuit 21: Pixel circuit 22: LED 23: Source line 24: Gate line 61: Anti-noise control circuit 62: Charging circuit 63: Output transistor 64: Capacitor 65: Pull-down circuit 66: Output circuit 211: Driver transistor 212: Display data write transistor 213: Luminescent control transistor 661: First inverter 662: Second inverter A: Precharge node B: Node C: Node C1: Storage capacitor C2: Capacitor Carry[n-4]: First cascade signal Carry[n]: Second cascade signal Carry[n+4]: Third cascade signal CLK[n]: Clock signal D: Node EM[n]: Emission drive signal G[n]: Gate control signal Is: Inverter signal N1: Output node STV: Vertical start signal T1~T16: First to sixteenth transistors t1: Precharge period t2: Self-lift period t3: Pulse width modulation period t4: Pull-down period t10, t11, t12: Time period Vdata: Display data signal VDD: Supply voltage VGH: First voltage VGL: Second voltage VGLL: Third voltage

Figure 1 is a block diagram illustrating a self-luminous display including a light-emitting driver circuit according to the present invention. Figure 2 is a circuit diagram illustrating a pixel circuit shown in Figure 1. Figure 3 is a circuit block diagram illustrating an embodiment of the light-emitting driver circuit according to the present invention. Figure 4 is a circuit diagram illustrating an anti-noise control circuit, a charging circuit, a pull-down circuit, and an output circuit according to the embodiment. Figure 5 is a waveform diagram illustrating a clock signal, first through third cascade signals, and a light-emitting driver signal according to the embodiment of Figure 4.

6: Luminescent drive circuit

61: Anti-noise control circuit

62: Charging circuit

63: Output transistor

64: Capacitor

65: Pull-down circuit

66: Output circuit

A: Pre-charged node

Carry[n-4]: First cascade signal

Carry[n]: Second cascade signal

CLK[n]: clock signal

EM[n]: luminous drive signal

N1: Output node

VGH: First voltage

Claims (10)

A light-emitting driver circuit with multiple output functions is suitable for use in a gate driver unit of a self-luminous display. The light-emitting driver circuit includes: an anti-noise control circuit that receives a first cascade signal and a second cascade signal, has an output node, and is coupled to a pre-charge node. The anti-noise control circuit adjusts the voltage level of the output node to a low voltage level or a high voltage level based on the first cascade signal, the second cascade signal, and the voltage level of the pre-charge node; a charging circuit that receives a first voltage and the first cascade signal, is coupled to the pre-charge node, and is controlled by the first cascade signal to charge the pre-charge node according to the first voltage; an output transistor having a first terminal for receiving a clock signal, a second terminal coupled to the anti-noise control circuit and providing the second cascade signal to the anti-noise control circuit, and a control terminal coupled to the pre-charge node; a pull-down circuit coupled to the pre-charge node, the output node of the anti-noise control circuit, and the second terminal of the output transistor, and determining whether to pull down the voltage level of the second terminal of the output transistor and the voltage level of the pre-charge node to a second voltage and a third voltage, respectively, based on the voltage level of the output node; and An output circuit receives the first voltage and is coupled to the pre-charge node. Based on the first voltage and the voltage level of the pre-charge node, the output circuit generates a light-emitting driving signal and outputs the signal to a plurality of light-emitting control elements in the self-luminous display. The pulse width and number of the light-emitting driving signal vary with the voltage level of the pre-charge node. A light-emitting driver circuit as described in claim 1, wherein: when the output node of the anti-noise control circuit switches from having the low voltage level to having the high voltage level, the pull-down circuit pulls down the voltage level of the second end of the output transistor to the second voltage and pulls down the voltage level of the pre-charge node to the third voltage according to the voltage level of the output node; and the first voltage is a high voltage, the second voltage and the third voltage are each a low voltage, and the second voltage is greater than the third voltage. The light-emitting driving circuit as described in claim 1, wherein when the anti-noise control circuit causes the output node to have the low voltage level based on the first cascade signal, the second cascade signal and the voltage level of the pre-charge node, the light-emitting driving signal has a high level; when the anti-noise control circuit causes the output node to have the high voltage level based on the first cascade signal, the second cascade signal and the voltage level of the pre-charge node, the light-emitting driving signal has a low level. The light-emitting driving circuit as described in claim 1 further includes: a capacitor coupled between the pre-charge node and the second end of the output transistor. A light-emitting driver circuit as described in claim 1, wherein the anti-noise control circuit includes: a first transistor having a first end receiving the first voltage, a second end, and a control end coupled to the first end thereof; a second transistor having a first end receiving the first voltage, a second end coupled to the output node, and a control end coupled to the second end of the first transistor; a third transistor having a first end coupled to the second end of the first transistor, a second end receiving the second voltage, and a control end receiving the second cascade signal; a fourth transistor having a first end coupled to the second end of the first transistor, a second end receiving the second voltage, and a control end receiving the first cascade signal; and a fifth transistor having a first end coupled to the output node, a second end receiving the third voltage, and a control end coupled to the pre-charge node. The light-emitting driving circuit as described in claim 1, wherein the charging circuit includes: a sixth transistor having a first end receiving the first voltage, a second end coupled to the pre-charge node, and a control end receiving the first cascade signal. A light-emitting driver circuit as described in claim 1, wherein the pull-down circuit includes: a seventh transistor having a first end coupled to the pre-charge node, a second end, and a control end coupled to the output node of the anti-noise control circuit; an eighth transistor having a first end coupled to the second end of the seventh transistor, a second end receiving the third voltage, and a control end coupled to the control end of the seventh transistor; a ninth transistor having a first end coupled to the second end of the output transistor, a second end receiving the second voltage, and a control end coupled to the control end of the seventh transistor; and a tenth transistor having a first end coupled to the pre-charge node, a second end receiving the first cascade signal, and a control end receiving a third cascade signal. The light-emitting driving circuit as described in claim 1, wherein the output circuit includes: a first inverter, which receives the first voltage and is coupled to the pre-charge node, and generates an inverter signal based on the first voltage and the voltage level of the pre-charge node; and a second inverter, which receives the first voltage and is coupled to the first inverter to receive the inverter signal, and generates the light-emitting driving signal based on the first voltage and the inverter signal. A light-emitting driver circuit as described in claim 8, wherein the first inverter includes: an eleventh transistor having a first end providing the inverter signal, a second end receiving the second voltage, and a control end coupled to the pre-charge node; and a twelfth transistor having a first end receiving the first voltage, a second end coupled to the first end of the eleventh transistor, and a control end coupled to its own first end. The light-emitting driving circuit as described in claim 8, wherein the second inverter includes: a thirteenth transistor having a first end, a second end receiving the second voltage, and a control end coupled to the first inverter to receive the inverter signal; a fourteenth transistor having a first end coupled to the first end of the thirteenth transistor and providing the light-emitting driving signal, a second end receiving the second voltage, and a control end coupled to the control end of the thirteenth transistor; a fifteenth transistor having a first end receiving the first voltage, a second end, and a control end coupled to its own first end; a sixteenth transistor having a first end receiving the first voltage, a second end coupled to the first end of the fourteenth transistor, and a control end coupled to the second end of the fifteenth transistor; and A capacitor is coupled between the first terminal of the thirteenth transistor and the second terminal of the fifteenth transistor.