TWM663864U - Chip package and substrate thereof - Google Patents

Abstract

A chip package includes a substrate, a chip and a heat spreader. The substrate includes a carrier, a circuit layer and a solder resist layer. The circuit layer is provided on the carrier and includes circuit lines each having an inner lead, a first conductive section and a second conductive section. The solder resist layer covers the circuit layer and includes a first opening, at least one second opening and a covering portion located between the first and second openings. The first opening exposes the inner lead, the covering portion covers the first conductive section, and the second opening exposes the second conductive section. The chip is electrically connected to the inner lead, and the heat spreader is attached to the second conductive section visible from the second opening by an electrically insulative adhesive to improve heat dissipation performance and flexibility of the chip package.

Description

Package structure and substrate

This invention relates to a packaging structure and a substrate thereof, in particular to a packaging structure and a substrate thereof that increase thermal conductivity and flexibility by contacting a circuit layer of a substrate with a heat sink.

As the computing speed of integrated circuits increases, the temperature of the chip will rise. In order to reduce the temperature of the chip, a heat sink is installed on the chip to dissipate heat. However, due to the miniaturization of chips, the efficiency of the heat sink cannot keep up with the speed of chip temperature rise, resulting in chip damage or affecting the computing speed.

The main purpose of this invention is to provide a packaging structure, in which a substrate and a chip are covered with a heat sink, and the heat sink is attached to a circuit layer exposed by a solder mask to increase the heat dissipation performance of the packaging structure.

A packaging structure of the invention includes a substrate, a chip and a heat sink. The substrate has a carrier, a circuit layer and a solder mask. The circuit layer is arranged on the carrier. The circuit layer includes a plurality of circuits. The circuit has an inner pin, a first conductive section, a second conductive section and an outer pin. The first conductive section is located between the inner pin and the second conductive section, and the second conductive section is located between the first conductive section and the outer pin. The solder mask covers the circuit layer. The solder mask has a first opening. , a first shielding portion and at least one second opening, the first shielding portion is between the first opening and the second opening, the first opening exposes the inner lead, the first shielding portion covers the first conductive section, the second opening exposes the second conductive section, the chip is disposed on the substrate and electrically connected to the inner lead, the heat sink covers the substrate and the chip, the heat sink has a heat dissipation layer and an insulating adhesive layer, the heat dissipation layer is attached to the second conductive section exposed by the second opening with the insulating adhesive layer.

A substrate of a packaging structure of the present invention comprises a carrier, a circuit layer and a solder mask layer. The circuit layer is arranged on the carrier. The circuit layer comprises a plurality of circuits. The circuit has an inner pin, a first conductive section, a second conductive section and an outer pin. The first conductive section is located between the inner pin and the second conductive section, and the second conductive section is located between the first conductive section and the outer pin. The solder mask layer covers the circuit layer. The solder mask has a first opening, a first shielding portion and at least one second opening, the first shielding portion is between the first opening and the second opening, the first opening exposes the inner lead for electrically connecting a chip, the first shielding portion covers the first conductive section, and the second opening exposes the second conductive section for a heat sink layer to be attached to the second conductive section exposed by the second opening with an insulating adhesive layer.

The heat dissipation layer is attached to the second conductive section exposed by the second opening by the insulating adhesive layer, so that the heat generated by the chip during operation can be transferred from the second conductive section to the heat sink attached to the second conductive section, thereby increasing the heat dissipation performance of the packaging structure.

Please refer to Figures 1 and 2 for an embodiment of the present invention, and please refer to Figures 3 and 4 for different embodiments of the present invention. A packaging structure 100 of the present invention includes a substrate 110, a chip 120 and a heat sink 130. The substrate 110 has a carrier 111, a circuit layer 112 and a solder mask 113. The material of the carrier 111 can be selected from polyimide (PI) or other flexible materials, but is not limited to this. The circuit layer 112 is disposed on the carrier 111, the solder mask 113 covers the circuit layer 112, the chip 120 is disposed on the substrate 110 and electrically connected to the circuit layer 112, and the heat sink 130 covers the substrate 110 and the chip 120.

Please refer to Figures 1 and 2. The circuit layer 112 includes a plurality of circuits L. Each of the circuits L has an inner pin L1, a first conductive segment L2, a second conductive segment L3 and an outer pin L4. The first conductive segment L2 is located between the inner pin L1 and the second conductive segment L3. The second conductive segment L3 is located between the first conductive segment L2 and the outer pin L4. In this embodiment, each of the circuits L further has a third conductive segment L5. The third conductive segment L5 is located between the second conductive segment L3 and the outer pin L4.

Please refer to Figures 1 and 2, the solder mask 113 has a first opening 113a, a first shielding portion 113b and at least one second opening 113c, the first shielding portion 113b is located between the first opening 113a and the second opening 113c, in this embodiment, the first shielding portion 113b surrounds the first opening 113a, and the second opening 113c surrounds the first opening 113a and the first shielding portion 113b, please refer to Figure 4, in different embodiments of the present invention, the second opening 113c is located on one side of the first opening 113a, or, when the solder mask 113 has a plurality of second openings 113c, the second openings 113c may not be connected to each other and may be arranged on different sides of the first opening 113a.

Please refer to Figures 1 and 2. The first opening 113a reveals the inner lead L1, the first shielding portion 113b covers the first conductive section L2, and the second opening 113c reveals the second conductive section L3. In this embodiment, the solder mask 113 has a second shielding portion 133d. The second opening 113c is located between the first shielding portion 113b and the second shielding portion 133d. The second shielding portion 133d covers the third conductive section L5 and reveals the outer lead L4. The outer lead L4 is used to be electrically connected to an external electronic component (not shown in the figure, such as a panel, etc.).

Referring to FIGS. 1 and 2 , the chip 120 is disposed in the first opening 113a and electrically connected to the inner lead L1. Preferably, a filler 140 is filled between the chip 120 and the substrate 110. The heat sink 130 has a heat sink layer 131 and an insulating adhesive layer 132. The heat sink layer 131 is attached to the second conductive section L3 exposed by the second opening 113c by the insulating adhesive layer 132, so that the heat generated by the chip 120 during operation can be transferred from the inner lead L1, the first conductive section L2 and the second conductive section L3 to the conductive section L3 attached to the second conductive section L3. The heat sink 130 of the connecting section L3 is used to increase the area of the heat sink 130 contacting the heat source (such as the chip 120 and the circuit layer 112), thereby increasing the thermal conductivity of the packaging structure 100. In this embodiment, the heat sink 131 is attached to the first shielding portion 113b and the second shielding portion 133d by the insulating adhesive layer 132 to prevent the edges of the first shielding portion 113b or the second shielding portion 133d located on both sides of the second opening 113c from rising, thereby causing the solder mask 113 to peel off the carrier 111 or the circuit layer 112.

Please refer to Figures 1, 3 and 4. The area of the second opening 113c is smaller than the area of the heat sink 130 covering the second opening 113c, so that the heat sink 130 can fully cover the second opening 113c. Since the heat dissipation layer 131 is attached to the first shielding portion 113b and the second shielding portion 133d by the insulating adhesive layer 132, moisture can be prevented from entering the second opening 113c. Please refer to Figures 1, 3 and 4. The difference lies in the opening area and shape of the second opening 113c, which can be changed according to the heat dissipation requirements. The shape of the second opening 113c can be selected from rectangles, triangles, trapezoids and other shapes.

Please refer to Figures 1 and 2. In this embodiment, along an axial direction Y, there is a first thickness D1 between the first conductive segment L2 and the heat dissipation layer 131, and there is a second thickness D2 between the second conductive segment L3 and the heat dissipation layer 131. The second thickness D2 is less than the first thickness D1. When the packaging structure 100 is used in curved electronic products (such as panels, etc.), the flexibility of the packaging structure 100 can be increased by the second thickness D2 being less than the first thickness D1, so as to reduce the shear stress between the chip 120 and the inner pin L1, so as to prevent the chip 120 from detaching from the inner pin L1 and causing a short circuit.

Please refer to FIGS. 1 and 2 . In this embodiment, the heat dissipation layer 131 is attached to the exposed surface of the chip 120 and the filling material 140 by the insulating adhesive layer 132 . Alternatively, in different embodiments, the heat dissipation layer 131 directly contacts the exposed surface of the chip 120 .

The scope of protection of this creation shall be determined by the scope of the patent application attached hereto. Any changes and modifications made by anyone familiar with this technology without departing from the spirit and scope of this creation shall fall within the scope of protection of this creation.

100: packaging structure 110: substrate 111: carrier 112: circuit layer 113: solder mask 113a: first opening 113b: first shielding part 113c: second opening 133d: second shielding part 120: chip 130: heat sink 131: heat sink layer 132: insulating adhesive layer 140: filling material D1: first thickness D2: second thickness L: circuit L1: inner lead L2: first conductive section L3: second conductive section L4: outer lead L5: third conductive section Y: axial direction

Figure 1: A schematic top view of the packaging structure of the present invention. Figure 2: A cross-sectional view of the packaging structure of the present invention. Figure 3: A schematic top view of the packaging structure of another embodiment of the present invention. Figure 4: A schematic top view of the packaging structure of another embodiment of the present invention.

100:Packaging structure

110: Substrate

111: Carrier

113: Solder mask

113a: First opening

113b: First shielding part

113c: Second opening

133d: Second shielding part

120: Chip

130: Heat sink

131: Heat dissipation layer

132: Insulating adhesive layer

140: Filling material

D1: First thickness

D2: Second thickness

L1: Inner pin

L2: First conductor section

L3: Second conducting section

L4: external pins

L5: The third conducting section

Y: Axis

Claims (12)

A packaging structure, comprising: A substrate, having a carrier, a circuit layer and a solder mask, the circuit layer being arranged on the carrier, the circuit layer comprising a plurality of circuits, each of the circuits having an inner pin, a first conductive section, a second conductive section and an outer pin, the first conductive section being located between the inner pin and the second conductive section, the second conductive section being located between the first conductive section and the outer pin, the solder mask covering the circuit layer, the solder mask having a first opening, a first shielding portion and at least one second opening, the first shielding portion being located between the first opening and the second opening, the first opening revealing the inner pin, the first shielding portion covering the first conductive section, and the second opening revealing the second conductive section; A chip is disposed on the substrate and electrically connected to the inner pin; and a heat sink covers the substrate and the chip, the heat sink has a heat sink layer and an insulating adhesive layer, and the heat sink layer is attached to the second conductive section exposed by the second opening with the insulating adhesive layer. In the packaging structure of claim 1, the area of the second opening is smaller than the area of the heat sink covering the second opening, so that the heat sink completely covers the second opening. As in the packaging structure of claim 1, each of the circuits has a third conductive segment, the third conductive segment is located between the second conductive segment and the external lead, the solder mask has a second shielding portion, the second opening is located between the first shielding portion and the second shielding portion, the second shielding portion covers the third conductive segment and exposes the external lead. As in the packaging structure of claim 3, the heat dissipation layer is attached to the first shielding portion and the second shielding portion by the insulating adhesive layer. In the packaging structure of any one of claims 1 to 4, there is a first thickness between the first conductive section and the heat dissipation layer, and there is a second thickness between the second conductive section and the heat dissipation layer, and the second thickness is smaller than the first thickness. A packaging structure as claimed in claim 5, wherein the second opening surrounds the first opening and the first shielding portion. A packaging structure as claimed in claim 6, wherein the first shielding portion surrounds the first opening. A substrate of a package structure, comprising: a carrier; a circuit layer, disposed on the carrier, the circuit layer comprising a plurality of circuits, each of the circuits having an inner pin, a first conductive section, a second conductive section and an outer pin, the first conductive section being located between the inner pin and the second conductive section, the second conductive section being located between the first conductive section and the outer pin; and A solder mask covers the circuit layer. The solder mask has a first opening, a first shielding portion and at least one second opening. The first shielding portion is between the first opening and the second opening. The first opening exposes the inner pin for electrically connecting a chip. The first shielding portion covers the first conductive section. The second opening exposes the second conductive section for a heat sink to be attached to the second conductive section exposed by the second opening with an insulating adhesive layer. A substrate with a packaging structure as in claim 8, wherein each of the circuits has a third conductive segment, the third conductive segment is located between the second conductive segment and the external lead, the solder mask has a second shielding portion, the second opening is located between the first shielding portion and the second shielding portion, the second shielding portion covers the third conductive segment and exposes the external lead. A substrate with a packaging structure as claimed in claim 9, wherein the first shielding portion and the second shielding portion are used for the heat dissipation layer to be attached with the insulating adhesive layer. A substrate for a package structure as in any one of claims 8 to 10, wherein the second opening surrounds the first opening and the first shielding portion. A substrate of a packaging structure as claimed in claim 11, wherein the first shielding portion surrounds the first opening.