TWM662610U - Metal oxide semiconductor chip device - Google Patents

Abstract

The present invention provides a metal oxide semiconductor chip device, which includes a semiconductor substrate, wherein a first source structure and a second source structure are arranged in a pair on a first side of the semiconductor substrate. A drain structure is arranged on a second side of the semiconductor substrate relative to the first source structure and the second source structure. A first channel structure is arranged therebetween and separates the first source structure and the semiconductor substrate, and a second channel structure is arranged therebetween and separates the second source structure and the semiconductor substrate. A gate structure is arranged on the first side of the semiconductor substrate. The first channel structure and the second channel structure are arranged in a mirror image, and at least one wide region and at least one narrow region are formed between the first channel structure and the second channel structure according to different spacings therebetween.

Description

Metal oxide semiconductor chip device

This invention relates to a metal oxide semiconductor chip device, and more particularly to a metal oxide semiconductor chip device having a channel design for increasing current density and reducing on-resistance.

In the field of power electronics, power devices responsible for switching control are the key to performance. Silicon materials have long dominated this field, but with the increasing power density, switching speed (frequency), and power consumption requirements in applications, the design of silicon material device performance is getting closer and closer to its theoretical limit. Therefore, most people in the industry start from materials and look for new semiconductor materials that can replace silicon. Based on this, two wide-bandgap semiconductor materials (also known as third-generation semiconductors), silicon carbide and gallium nitride, have gradually come into people's view, and silicon carbide, with its many characteristics, has incomparable advantages in power semiconductor devices.

Specifically in automotive applications, replacing silicon devices with silicon carbide in electric drive inverters can reduce the energy efficiency loss of the driver by 80% at the device level. According to estimates, the use of silicon carbide power devices in electric vehicle inverters can reduce the power consumption of the entire vehicle by 5%-10%. Taking all factors into consideration, although the cost of the inverter module will increase, the battery cost, heat dissipation cost, and space usage cost will be significantly reduced. In addition to inverters, silicon carbide power devices can also be used in many aspects of electric vehicle on-board chargers (OBCs), power conversion systems (DC/DC), and so on.

However, the improvement of materials has not yet achieved further breakthroughs in the market. The effective current density and chip size reduction of the metal oxide semiconductor chip device with a general in-line channel in the existing technology have reached the limit. Since the effective current density cannot be increased, the cost-effectiveness is low.

The main purpose of this invention is to provide a metal oxide semiconductor chip device, which includes a semiconductor substrate, on which a first source structure and a second source structure, a first channel structure and a second channel structure, and a gate structure are arranged. The first source structure and the second source structure are arranged in pairs on the first side of the semiconductor substrate. The drain structure is arranged on the second side of the semiconductor substrate relative to the first source structure and the second source structure. The first channel structure and the second channel structure, the first channel structure is arranged between and separates the first source structure and the semiconductor substrate, and the second channel structure is arranged between and separates the second source structure and the semiconductor substrate. The gate structure is disposed on the first side of the semiconductor substrate and contacts the first channel structure, the first source structure, the second channel structure, and the second source structure. The first channel structure and the second channel structure are configured in a mirror image, and the first channel structure and the second channel structure form at least one wide area and at least one narrow area according to their different spacings.

Furthermore, the semiconductor substrate includes an n+ base and an n epitaxial layer in sequence from the second side to the first side.

Furthermore, the first source structure includes a first n+ well region and a first metal silicide layer disposed on the first n+ well region; the second source structure includes a second n+ well region and a second metal silicide layer disposed on the second n+ well region.

Furthermore, the metal oxide semiconductor chip device further includes an electrode structure having two ends respectively connected across the first metal silicide layer of the first source structure and the second metal silicide layer of the second source structure.

Furthermore, the first channel structure includes a first p channel region disposed on a side of the first n+ well region close to the second n+ well region, and a first p+ doped region disposed on a side of the first n+ well region away from the second n+ well region; the second channel structure includes a second p channel region disposed on a side of the second n+ well region close to the first n+ well region, and a second p+ doped region disposed on a side of the second n+ well region away from the first n+ well region.

Furthermore, the gate structure includes an insulating layer disposed on the first side of the semiconductor substrate, and a conductive layer disposed on the insulating layer.

Furthermore, the insulating layer contacts the surface of the first side of the semiconductor substrate, and contacts the first n+ well region, the first p channel region, the n epitaxial layer, the second p channel region, and the second n+ well region from one end to the other end.

Furthermore, the first channel structure and the second channel structure are saw-tooth structures that are mirror images of each other.

Furthermore, the first channel structure and the second channel structure are wavy structures that are mirror images of each other.

Furthermore, the first channel structure and the second channel structure are comb-shaped structures that are mirror images of each other.

Therefore, compared with the prior art, the present invention can increase the effective cross-sectional area of the channel and effectively improve the current density under the same chip size. Furthermore, in addition to increasing the effective cross-sectional area of the channel, the cross-sectional area of the junction field region (JFET region) can also be increased, further improving the effective cross-sectional area and current density.

In order to make the technical content of this creation more detailed and complete, the implementation mode and specific embodiments of this creation are explained below. However, the following description is not the only form of implementing or using the specific embodiments of this creation. If a person with ordinary knowledge in this field can easily understand the necessary technical content of this creation through the following description, and can change and modify this creation in various ways to adapt to different purposes and conditions without violating its spirit and scope, then the implementation mode also falls within the scope of the patent application of this creation.

In the description of this creation, "a", "an" and "the" may also be interpreted as plural, unless the context otherwise states. In addition, in this specification and the attached patent application, unless otherwise stated, "disposed on something" may be regarded as directly or indirectly contacting the surface of something by affixing or other forms, and the definition of the surface shall be determined based on the context/paragraph meaning of the specification and the common knowledge in the field to which this specification belongs.

In the description of this work, unless the context otherwise states, "include", "including", "have" or "contain" are inclusive or open and do not exclude other unspecified elements or method steps.

In the description of this invention, the terms such as "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" etc. used to indicate the orientation or position relationship are based on the orientation or position relationship shown in the attached figure. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation of this invention. It should be noted that for the convenience of explanation, although this application uses a structural decomposition schematic diagram to represent the structural features, it does not mean that the product can actually be disassembled. Please be aware of this.

The metal oxide semiconductor chip device of this creation can be used in high-frequency and high-voltage products, such as inverters, rectifiers, electric vehicles, plug-in hybrid electric vehicles (PHEV), charging stations, smart grids, energy storage equipment, or rail transit and other high-frequency and high-power related electronic products. The scope of use of such devices is not limited in this creation.

The main materials of the metal oxide semiconductor chip device used in this creation can include but are not limited to silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ₂ O ₃ ), Diamond power semiconductor material (Diamond C) or other similar materials are not limited in this creation. The device type of the metal oxide semiconductor chip device used in this invention can be, for example, vertical diffusion metal oxide semiconductor (VDMOS), metal oxide semiconductor field effect transistor (MOSFET), insulated gate bipolar transistor ( IGBT) or other such devices are not limited in this creation. The gate structure design used in this invention may be, for example, but not limited to planar or trench type, and is not limited in this invention.

The following is a detailed description of one of the embodiments of the present invention. Please refer to "Figure 1" and "Figure 2" together, which are the appearance and partial cross-sectional schematic diagrams and structural decomposition schematic diagrams of the metal oxide semiconductor chip device in the present invention, as shown in the figure: This embodiment provides a metal oxide semiconductor chip device 100, which mainly includes a semiconductor substrate 10, a first source structure 21 and a second source structure 22 disposed on the semiconductor substrate 10, a first channel structure 31 and a second channel structure 32 disposed on the semiconductor substrate 10, and a drain structure 40 and a gate structure 50.

The first source structure 21 and the second source structure 22 are arranged in pairs on the first side P1 of the semiconductor substrate 10, and the drain structure 40 is arranged on the second side P2 of the semiconductor substrate 10 relative to the first source structure 21 and the second source structure 22. The first side P1 and the second side P2 mentioned here refer to the surface corresponding to the upper direction in Figure 1 (first side P1) and the surface corresponding to the lower direction in Figure 1 (second side P2), respectively. The directional expressions are only for the purpose of clearly explaining the content of this invention. It is understandable that when the device changes the placement direction, the directional relationship will change accordingly, and the change of these directions is not limited in this invention.

The first channel structure 31 is disposed between the first source structure 21 and the semiconductor substrate 10, thereby separating the first source structure 21 and the semiconductor substrate 10 so that the first source structure 21 forms a well structure; the second channel structure 32 is disposed between the second source structure 22 and the semiconductor substrate 10, thereby separating the second source structure 22 and the semiconductor substrate 10 so that the second source structure 22 forms a well structure. The gate structure is disposed on the first side P1 of the semiconductor substrate 10 and contacts the first channel structure 31, the first source structure 21, the second channel structure 32, and the second source structure 22. When an external electric field is applied to the gate, an electron layer (or hole layer) can be formed on the first channel structure 31 and the second channel structure 32, thereby allowing the first source structure 21 to conduct to the drain structure 40 through the semiconductor substrate 10, and allowing the second source structure 22 to conduct to the drain structure 40 through the semiconductor substrate 10.

In this embodiment, the region between the first channel structure 31 and the second channel structure 32 on the semiconductor substrate 10 is a junction field region 11 (JFET region). The junction field region 11 (JFET region) mentioned here does not mean that the metal oxide semiconductor chip device used in this invention is a JFET, but means that the first channel structure 31 and the second channel structure 32 on both sides of the semiconductor substrate 10 form a symmetrical structure, and the semiconductor substrate 10 is sandwiched between the first channel structure 31 and the second channel structure 32 to form a region similar to JFET characteristics.

Next, please refer to "Figure 3" which is a top view schematic diagram of the channel shape of the first embodiment of the metal oxide semiconductor chip device in the present invention, as shown in the figure: the first channel structure 31 and the second channel structure 32 in the present invention are configured in a mirror image. The mirror direction mentioned here refers to the top view direction as shown in Figure 2, and the first channel structure 31 and the second channel structure 32 are configured in a mirror shape to each other (not in the cross-sectional direction, as shown in Figure 1). At least one wide area UW and at least one narrow area NW are formed between the first channel structure 31 and the second channel structure 32 according to their different spacings; in one embodiment, the longest distance of the wide area UW is 2.1 μm ~ 2.3 μm, for example, it can be but not limited to 2.10 μm, 2.11 μm, 2.12 μm, 2.1 3μm, 2.14μm, 2.15μm, 2.16μm, 2.17μm, 2.18μm, 2.19μm, 2.20μm, 2.21μm, 2.22μm, 2.23μm, 2.24μm, 2.25μm, 2.26μm, 2.27μm, 2.28μm, 2. 29 μm or 2.30 μm are not limited in this invention; in one embodiment, the shortest distance of the narrow width area NW is 1.1 μm~1.3 μm, which may be but is not limited to 1.10 μm, 1.11 μm, 1.12 μm, 1.13 μm, 1.14 μm, 1.15 μm, 1.16 μm. m, 1.17μm, 1.18μm, 1.19μm, 1.20μm, 1.21μm, 1.22μm, 1.23μm, 1.24μm, 1.25μm, 1.26μm, 1.27μm, 1.28μm, 1.29μm, or 1.30μm are not limited in this creation. The narrow region NW is configured so that when an external electric field is applied, a clamp is formed at the position of the narrow region NW, while the current (I _SD ) from the source to the drain can pass through the wide region UW. In order to form the above configuration, the actual widths of the wide region UW and the narrow region NW will be related to the doping concentrations of the first p-channel region 311 in the first channel structure 31 and the second p-channel region 321 in the second channel structure 32. Therefore, the distance between the wide region UW and the narrow region NW is not limited in the present invention, and it should be determined by whether its configuration will allow the current in the wide region UW to pass through and the narrow region NW to be clamped when an external electric field is applied. In addition, it should be specially explained here that the area where the first channel structure 31 and the second channel structure 32 form the wide region UW and the narrow region NW mainly refers to the area on both sides of the junction field region 11 (JFET region), and the shapes of the remaining structures of the first channel structure 31 and the second channel structure 32 are not limited in this creation.

Although only the first channel structure 31 and the second channel structure 32 are described here as non-equidistant straight line mirror structures, in accordance with the design of the first channel structure 31 and the second channel structure 32, the first source structure 21 and the second source structure 22 and/or the conductive layer (such as metal silicide layer) thereon are also arranged in accordance with the shape of the first channel structure 31 and the second channel structure 32; similarly, the gate structure 50 can also be arranged in accordance with the shape of the first channel structure 31 and the second channel structure 32 to form areas of varying widths, which is not limited in this invention.

Please refer to FIG. 1 again. In the following embodiments, the structural features of the present invention are described using an npn structure. In one embodiment, the semiconductor substrate 10 includes an n+ substrate 12 and an n epitaxial layer 13 from the second side to the first side; the first source structure 21 includes a first n+ well region 211 and a first metal silicide layer 212 disposed on the first n+ well region 211; the second source structure 22 includes a second n+ well region 221 and a second metal silicide layer 212 disposed on the second n+ well region 221. Layer 222; in one embodiment, the metal oxide semiconductor chip device 100 further includes an electrode structure 23, which is respectively connected to the first metal silicide layer 212 of the first source structure 21 and the second metal silicide layer 222 of the second source structure 22 at both ends; the electrode structure 23 forms an empty groove 231 at the middle position so that the electrode structure 23 does not contact the gate structure 50. In one embodiment, the material of the electrode structure 23 can be aluminum or other conductive materials, which is not limited in this invention. It should be particularly noted that although the npn structure is adopted in this embodiment, it can also be configured as a pnp structure in practice, and the changes of these embodiments are not limited in this invention.

In one embodiment, the first channel structure 31 includes a first p-channel region 311 disposed on a side of the first n+ well region 211 close to the second n+ well region 221 (i.e., close to the junction field region 11), and a first p+ doped region 312 disposed on a side of the first n+ well region 211 far from the second n+ well region (i.e., far from the junction field region 11). The first p-channel region 311 and the first p+ doped region 312 surround the bottom side of the first n+ well region 211. The second channel structure 32 includes a first p-channel region 311 disposed on a side of the first n+ well region 211 close to the second n+ well region 211. 1 (i.e., close to the junction field region 11), and a second p+ doped region 322 disposed on a side of the second n+ well region 221 away from the first n+ well region 211 (i.e., away from the junction field region 11). The second p-channel region 321 and the second p+ doped region 322 surround the bottom side of the second n+ well region 221. The gate structure 50 includes an insulating layer 51 disposed on the first side P1 of the semiconductor substrate 10 (i.e., the upper surface of the junction field region 11), and a conductive layer 52 disposed on the insulating layer 51. According to the above configuration, the insulating layer 51 contacts the surface of the first side P1 of the semiconductor substrate 10, and contacts the first n+ well region 211, the first p channel region 311, the n epitaxial layer 13 (including the junction field region 11), the second p channel region 321, and the second n+ well region 221 from one end to the other end (from left to right in FIG. 1).

In one embodiment, the first p-channel region 311 is L-shaped and extends from the first n+ well region 211 to between the first n+ well region 211 and the junction field region 11, and contacts the insulating layer 51 of the gate structure 50 at the top side; the second p-channel region 321 is L-shaped and extends from the second n+ well region 221 to between the second n+ well region 221 and the junction field region 11, and contacts the insulating layer 51 of the gate structure 50 at the top side. In one embodiment, the width of the first p-channel region 311 and the second p-channel region 321 is 0.35 μm ~ 0.45 μm; the “width” of the first p-channel region 311 and the second p-channel region 321 mentioned here only refers to the area where channels can be generated on the first p-channel region 311 and the second p-channel region 321 , that is, the width mark MW in FIG. 1 1 and the area of the width mark MW2; the width may be, for example, but is not limited to 0.35 μm, 0.36 μm, 0.37 μm, 0.38 μm, 0.39 μm, 0.40 μm, 0.41 μm, 0.42 μm, 0.43 μm, 0.44 μm, or 0.45 μm, which is not limited in this creation.

Regarding the different embodiments of the channel structure in this invention, please refer to "Figure 2" to "Figure 6" together, which are top-view schematic diagrams of the channel shapes of the first to fifth embodiments of the metal oxide semiconductor chip device in this invention, as shown in the figure: Regarding Figures 2 to 6, for the convenience of explanation, it should be noted that the figures are simplified to only represent the shape of the channel, and are not used to limit the actual appearance of the metal oxide semiconductor chip device 100 in this invention, which is described in advance.

In one embodiment, the first channel structure 31 and the second channel structure 32 may be, but are not limited to, zigzag structures that are mirror images of each other (as shown in FIG. 2 ); in another embodiment, the first channel structure 31A and the second channel structure 32A may be, but are not limited to, wavy structures that are mirror images of each other (such as As shown in Figure 3), the wavy structure in the figure is in the form of a chain wave, with its sharp end facing inward; in another embodiment, the first channel structure 31B and the second channel structure 32B may be but not It is limited to wave-like structures that are mirror images of each other (as shown in Figure 4). The wave-like structure in the figure is a chain wave. The difference from the embodiment in Figure 3 is that the sharp end faces outward; in another embodiment, the first channel structure 31C and the second channel structure 32C can be, but are not limited to, wavy structures that are mirror images of each other ( As shown in Figure 5), the wavy structure of this embodiment is in the form of a sinusoidal wave; in one embodiment, The first channel structure 31D and the second channel structure 32D can be, but are not limited to, square wave structures that are mirror images of each other (as shown in Figure 6); however, the description of the above shapes is only used to illustrate several examples in this creation. Specific embodiments, simple changes in the shape should also fall within the scope of protection intended by this invention.

In summary, compared with the conventional technology, this invention can increase the effective cross-sectional area of the channel and effectively improve the current density under the same chip size. Furthermore, in addition to increasing the effective cross-sectional area of the channel, the cross-sectional area of the junction field region (JFET region) can also be increased, further improving the effective cross-sectional area and current density.

The above is a detailed description of the present invention. However, what is described above is only one of the better embodiments of the present invention and should not be used to limit the scope of implementation of the present invention. In other words, all equivalent changes and modifications made within the scope of the patent application for the present invention should still fall within the scope of the patent coverage of the present invention.

100: Metal oxide semiconductor chip device

10: Semiconductor substrate

11: Knot type field area

12:n+base

13:n epitaxial layer

21: First source structure

211: First n+ well area

212: First metal silicide layer

22: Second source structure

221: Second n+ well area

222: Second metal silicide layer

23: Electrode structure

231: Empty slot

31: First channel structure

311: first p channel region

312: First p+ doped region

32: Second channel structure

321: Second p channel region

322: Second p+ doped region

40: Drain structure

50: Gate structure

51: Insulation layer

52: Conductive layer

P1: First side

P2: Second side

UW: Wideband

NW: Narrow Width

31A: First channel structure

32A: Second channel structure

31B: First channel structure

32B: Second channel structure

31C: First channel structure

32C: Second channel structure

31D: First channel structure

32D: Second channel structure

MW1: Width marker

MW2: Width Marker

FIG1 is a schematic diagram of the appearance and partial cross-section of the metal oxide semiconductor chip device in this invention.

FIG. 2 is a schematic diagram showing the structural decomposition of the first embodiment of the metal oxide semiconductor chip device in the present invention.

FIG3 is a top view schematic diagram of the channel shape of the first embodiment of the metal oxide semiconductor chip device in the present invention.

FIG. 4 is a top view schematic diagram of the channel shape of the second embodiment of the metal oxide semiconductor chip device in the present invention.

FIG5 is a top view schematic diagram of the channel shape of the third embodiment of the metal oxide semiconductor chip device in the present invention.

Fig. 6 is a top view schematic diagram of the channel shape of the fourth embodiment of the metal oxide semiconductor chip device in the present invention.

FIG. 7 is a top view schematic diagram of the channel shape of the fifth embodiment of the metal oxide semiconductor chip device in the present invention.

100: Metal oxide semiconductor chip device

10: Semiconductor substrate

11: Knot type field area

12:n+base

13:n epitaxial layer

21: First source structure

211: The first n+ well area

212: First metal silicide layer

22: Second source structure

221: Second n+ well area

222: Second metal silicide layer

23: Electrode structure

231: Empty slot

31: First channel structure

311: First p channel region

312: The first p+ doped region

32: Second channel structure

321: Second p channel area

322: Second p+ doped region

40: Drain structure

50: Gate structure

51: Insulation layer

52: Conductive layer

P1: First side

P2: Second side

Claims (10)

A metal oxide semiconductor chip device includes: a semiconductor substrate; a first source structure and a second source structure, which are arranged in pairs on a first side of the semiconductor substrate; a drain structure, which is arranged on a second side of the semiconductor substrate opposite to the first source structure and the second source structure; a first channel structure and a second channel structure, wherein the first channel structure is arranged between and separates the first source structure and the semiconductor substrate, and the second channel structure The second source structure and the semiconductor substrate are arranged therebetween and separated; and a gate structure is arranged on the first side of the semiconductor substrate and contacts the first channel structure, the first source structure, the second channel structure, and the second source structure; wherein the first channel structure and the second channel structure are arranged in a mirror image, and the first channel structure and the second channel structure form at least one wide area and at least one narrow area according to their different spacings. A metal oxide semiconductor chip device as described in claim 1, wherein the semiconductor substrate includes an n+ base and an n epitaxial layer in sequence from the second side to the first side. A metal oxide semiconductor chip device as described in claim 2, wherein the first source structure includes a first n+ well region and a first metal silicide layer disposed on the first n+ well region; the second source structure includes a second n+ well region and a second metal silicide layer disposed on the second n+ well region. The metal oxide semiconductor chip device as described in claim 3 further includes an electrode structure having two ends respectively connected across the first metal silicide layer of the first source structure and the second metal silicide layer of the second source structure. A metal oxide semiconductor chip device as described in any one of claim 3 or 4, wherein the first channel structure includes a first p channel region disposed on a side of the first n+ well region close to the second n+ well region, and a first p+ doped region disposed on a side of the first n+ well region away from the second n+ well region; the second channel structure includes a second p channel region disposed on a side of the second n+ well region close to the first n+ well region, and a second p+ doped region disposed on a side of the second n+ well region away from the first n+ well region. A metal oxide semiconductor chip device as described in claim 5, wherein the gate structure includes an insulating layer disposed on the first side of the semiconductor substrate, and a conductive layer disposed on the insulating layer. A metal oxide semiconductor chip device as described in claim 6, wherein the insulating layer contacts the surface of the first side of the semiconductor substrate, and contacts the first n+ well region, the first p channel region, the n epitaxial layer, the second p channel region, and the second n+ well region from one end to the other. A metal oxide semiconductor chip device as described in claim 1, wherein the first channel structure and the second channel structure are saw-tooth structures that are mirror images of each other. A metal oxide semiconductor chip device as described in claim 1, wherein the first channel structure and the second channel structure are wavy structures that are mirror images of each other. A metal oxide semiconductor chip device as described in claim 1, wherein the first channel structure and the second channel structure are comb structures that are mirror images of each other.

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