TWM654134U - Power supply circuit - Google Patents

Abstract

A power supply circuit includes a clock buffer, a charge pump, a control circuit and a clamp circuit. The clock buffer is configured to generate an adjusted clock signal according to a clock signal and a level control signal. The clock signal includes a preset level. The charge pump is coupled to the clock buffer, and is configured to generate an output signal according to the adjusted clock signal and a system voltage. The control circuit is coupled to the charge pump, and is configured to generate a charge pump control signal according to the output signal. The clamp circuit is coupled between the control circuit and clock buffer, and is configured to receive the charge pump control signal and the system voltage. The clamp circuit is configured to output the level control signal according to the charge pump control signal. In response to the level of the level control signal, the adjusted clock signal includes an adjusted level.

Description

Power supply circuit

The present disclosure relates to a power supply circuit. Specifically, the present disclosure relates to a power supply circuit applied to a charge pump.

Existing charge pump control circuits all use amplifiers (comparators) to convert the feedback analog control signal into a digital control signal to control the output voltage of the charge pump. However, the digital control signal only has high and low levels, that is, the control circuit only has two states: on and off. When the response time in the control circuit is long, the output voltage of the charge pump will be too high or too low. Furthermore, the use of amplifiers in the control circuit will increase the area and power consumption of the control circuit.

Therefore, in view of the fact that the prior art still has many defects, there is a need for a novel power supply circuit to improve the above problems.

One aspect of the present disclosure relates to a power supply circuit. The power supply circuit includes a clock buffer, a charge pump, a control circuit, and a voltage clamp circuit. The clock buffer is used to generate an adjusted clock signal according to a clock signal and a level control signal. The clock signal has a preset level. The charge pump is coupled to the clock buffer and is used to generate an output signal according to the adjusted clock signal and a system voltage. The control circuit is coupled to the charge pump and is used to generate a charge pump control signal according to the output signal. The voltage clamp circuit is coupled between the control circuit and the clock buffer and is used to receive the system voltage and the charge pump control signal. The voltage clamp circuit generates an output level control signal according to the charge pump control signal. The regulated clock signal has an regulated level in response to the level of the level control signal.

In view of the above-mentioned shortcomings and deficiencies of the prior art, the present disclosure provides a power supply circuit. By designing the power supply circuit of the present disclosure, it is not necessary to use an amplifier to compare voltages to output a digital control signal. In addition, the power supply circuit can significantly reduce the component area and power consumption, thereby reducing the complexity of the circuit layout.

The following will clearly illustrate the spirit of the present disclosure with diagrams and detailed descriptions. After understanding the embodiments of the present disclosure, any person with ordinary knowledge in the relevant technical field can make changes and modifications based on the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure.

The terms used herein are only for describing specific embodiments and are not intended to be limiting of the present disclosure. Singular forms such as "a", "this", "here", "this" and "the" as used herein also include plural forms.

The terms “include”, “including”, “have”, “contain”, etc. used in this document are open terms, meaning including but not limited to.

The terms used herein generally have the ordinary meanings of each term used in the art, in the context of the present disclosure, and in the specific context, unless otherwise specified. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the present disclosure.

Certain terms are used in the specification and patent application to refer to specific components. However, a person with ordinary knowledge in the art should understand that the same component may be referred to by different terms. The specification and patent application do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The term "including" mentioned in the specification and patent application is an open term and should be interpreted as "including but not limited to". In addition, "coupling" includes any direct and indirect connection means. Therefore, if the text describes a first component connected to a second component, it means that the first component can be directly connected to the second component through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal-connected to the second component through other components or connection means.

FIG. 1 is a circuit block diagram of a power supply circuit 100 according to some embodiments of the present disclosure. In some embodiments, referring to FIG. 1, the power supply circuit 100 includes a clock buffer 110, a charge pump 120, a control circuit 130, and a voltage clamp circuit 140. The charge pump 120 is coupled to the clock buffer 110. The control circuit 130 is coupled to the charge pump 120. The voltage clamp circuit 140 is coupled between the control circuit 130 and the clock buffer 110.

In some embodiments, the clock buffer 110 is used to generate an adjusted clock signal CLK_IN to the charge pump 120 according to the clock signal CLK and the level control signal VDD_CLK. When the voltage level of the level control signal VDD_CLK is lower, the voltage level of the adjusted clock signal CLK_IN output by the clock buffer 110 is lower. Conversely, when the voltage level of the level control signal VDD_CLK is higher, the voltage level of the adjusted clock signal CLK_IN output by the clock buffer 110 is higher.

In some embodiments, the charge pump 120 can be used to generate an output voltage (e.g., an output signal HV) that is greater than an input voltage (e.g., a system voltage VDD). For example, assuming that the system high voltage of an electronic device is 1.5V, and the voltage requirement of a specific high-voltage circuit in the electronic device is 9V, the charge pump 120 can be used to convert the system high voltage 1.5V to generate an output signal with a voltage as high as 9V, thereby driving the above-mentioned specific high-voltage circuit. This is known to those skilled in the art and will not be elaborated here for simplicity.

In one example, an amplifier (or comparator) is provided in the control circuit of an existing charge pump to generate a feedback control signal of the charge pump according to the output voltage of the charge pump, thereby increasing or decreasing the output voltage of the charge pump. However, if the feedback control signal is converted into a digital control signal through an amplifier, the digital control signal will only have a high level and a low level, that is, the control circuit will only have two states, on and off, resulting in a prolonged feedback response time of the control circuit. When the feedback response time of the control circuit is prolonged, the output voltage of the charge pump will be either too high or too low. This disclosure will describe how to improve the above problem in the subsequent content.

In some embodiments, the purpose of setting the control circuit 130 is to detect whether the output voltage of the output signal HV of the charge pump 120 exceeds a preset voltage range, and to compare whether the voltage of the output signal HV is equal to the bias voltage of the current generated inside the control circuit 130. When the voltage level of the output signal HV is not equal to the bias voltage of the current generated inside the control circuit 130, the control circuit 130 activates the feedback mechanism to control the voltage clamp circuit 140 to change the voltage level of the adjusted clock signal CLK_IN output by the clock buffer 110, thereby changing the level of the output signal HV of the charge pump 120. The details of how the control circuit 130 and the voltage clamp circuit 140 determine the voltage level of the regulated clock signal CLK_IN will be further explained in the following paragraphs.

To make the operation of the power supply circuit 100 of Figure 1 of the present disclosure easier to understand, please refer to Figures 2 to 4A together. Figure 2 is a flow chart of a dynamic voltage adjustment method 200 according to some embodiments of the present disclosure. Figure 3 is a signal timing chart of the power supply circuit 100 of Figure 1 according to some embodiments of the present disclosure. Figure 4A is a circuit block chart of the power supply circuit 100A according to some embodiments of the present disclosure. The power supply circuit 100A of Figure 4A corresponds to the power supply circuit 100 of Figure 1. The power supply circuit 100A includes a clock buffer 110A, a charge pump 120A, a control circuit 130A, and a voltage clamp circuit 140A. The connection method and operation of the clock buffer 110A, the charge pump 120A, the control circuit 130A and the voltage clamp circuit 140A are similar to the corresponding components in the power supply circuit 100 of FIG. 1 . For the sake of brevity, only the differences are described below.

In some embodiments, the control circuit 130A includes a diode (e.g., the Zener diode Z1 shown in the figure, but the present disclosure is not limited thereto), a transistor T1, and a constant current source S1. The voltage clamp circuit 140A includes a transistor T2. The cathode end of the Zener diode Z1 is coupled to the charge pump 120A and is used to output a voltage regulation signal according to the output signal HV. It should be noted that when a reverse voltage is applied to the Zener diode Z1, a constant voltage will be maintained within a specific range, and the transistor T1, the constant current source S1, and the transistor T2 of the voltage clamp circuit 140A will be protected from surge current and static electricity.

Next, please count from the top and right of the diagram as the first end. The first end of transistor T1 is coupled to the anode end of Zener diode Z1. The second end of transistor T1 is coupled to node N1 and constant current source S1. The control end of transistor T1 is turned on in response to system voltage VDD. Reference current I _HV passes through transistor T1 to generate a voltage level at node N1.

In some embodiments, transistor T1 can be implemented by N-type metal-oxide-semiconductor field-effect transistor (P-type Metal-Oxide-Semiconductor Field-Effect Transistor, NMOS), and transistor T2 can be implemented by P-type metal-oxide-semiconductor field-effect transistor (PMOS). However, the present disclosure is not limited to this. For example, according to different designs of the charge pump control signal CP_C, transistor T2 can also be implemented by NMOS.

In some embodiments, a capacitor C1 is included between the control circuit 130A and the voltage clamp circuit 140A. The capacitor C1 is coupled to the node N1 of the control circuit 130A and the transistor T2 of the voltage clamp circuit 140A. The capacitor C1 is charged or discharged to provide a charge pump control signal CP_C of different levels.

In step 210, referring to FIGS. 2 to 4A, the clock buffer 110A receives the clock signal CLK and generates an adjusted clock signal CLK_IN according to the clock signal CLK and the level control signal VDD_CLK.

In step 220, the charge pump 120A is used to generate an output signal HV according to the regulated clock signal CLK_IN and the system voltage VDD. The relationship between the output signal HV, the regulated clock signal CLK_IN and the system voltage VDD is shown in equation 1.

Formula 1: .

In Formula 1, K and M are both positive integers. It should be noted that in some embodiments, the charge pump 120A may be a Dickson charge pump and include multiple stages of diode/capacitor units (e.g., diode/capacitor units SG1-SGn), one side of each capacitor is boosted by a clock signal (e.g., adjusted clock signal CLK_IN), and the voltage is accumulated through the combination of capacitors and diodes to gradually achieve a voltage doubling effect. The values of K and M are designed according to the number and requirements of the multiple stages of diode/capacitor units (e.g., diode/capacitor units SG1-SGn) of the charge pump 120A.

In step 230, please refer to FIG. 2 to FIG. 4A. For example, transistor T2 can be a PMOS (but the present disclosure is not limited thereto), and the drain level of transistor T2 is the system voltage VDD, the gate level is the charge pump control signal CP_C, and the source level is the level control signal VDD_CLK. When the charge pump control signal CP_C is less than the difference between the system voltage VDD and the critical voltage of transistor T2, transistor T2 is turned on and has an on-resistance. When the charge pump control signal CP_C is smaller, the degree of conduction of transistor T2 is greater (equivalent to the smaller on-resistance of transistor T2), making the voltage of level control signal VDD_CLK higher; conversely, when the charge pump control signal CP_C is larger, the degree of conduction of transistor T2 is smaller (equivalent to the larger on-resistance of transistor T2), making the voltage of level control signal VDD_CLK lower. On-resistance refers to the resistive behavior between the drain and source when the transistor is in the on state, and on-resistance refers to the resistance generated by the resistive behavior.

In detail, when the voltage level of the output signal HV decreases, the level control signal VDD_CLK increases, so the pulse amplitude of the adjusted clock signal CLK_IN generated by the clock buffer 110A is higher than the clock signal CLK, so that the charge pump 120A pulls up the level of the output signal HV; when the voltage level of the output signal HV increases, the level control signal VDD_CLK decreases, so the pulse amplitude of the adjusted clock signal CLK_IN generated by the clock buffer 110A is lower than the clock signal CLK, so that the charge pump 120A pulls down the level of the output signal HV, thereby achieving the effect of adjusting the output signal HV. As the level of the output signal HV generated by the charge pump 120A increases, the reference current I _HV increases. The constant current source S1 is used to output the reference current I _REF , and the control circuit 130A is used to generate the reference current I _HV according to the output signal HV, and generate the charge pump control signal CP_C according to the reference current I _HV and the reference current I _REF . When the reference current I _HV increases to be greater than the reference current I _REF , a shunt is generated from the node N1 to flow to the voltage clamp circuit 140A to charge the capacitor C1, so that the level of the charge pump control signal CP_C gradually increases, and the transistor T2 of the voltage clamp circuit 140A gradually closes in response to the voltage level of the charge pump control signal CP_C.

While the on-resistance of transistor T2 gradually increases, transistor T2 is still in the on state, and the current path between the drain terminal and the source terminal of transistor T2 gradually shrinks along with the charge pump control signal CP_C, but is not completely in the off state. In addition, as the level of the output signal HV generated by the charge pump 120A decreases, the reference current I _HV decreases accordingly. When the reference current I _HV decreases to be lower than the reference current I _REF , the capacitor C1 discharges to the node N1, causing the level of the charge pump control signal CP_C to gradually decrease. At this time, the transistor T2 of the voltage clamp circuit 140A responds to the voltage level of the charge pump control signal CP_C and makes the current path between the drain and source of the transistor T2 more conductive. In other words, the conduction resistance of the transistor T2 gradually decreases, and the current path between the drain and source of the transistor T2 gradually expands along with the charge pump control signal CP_C.

Please refer to FIG. 4B, which is a schematic diagram of the clock buffer 110A in the power supply circuit 100A of FIG. 4A. As shown in FIG. 4B, the clock buffer 110A includes an inverter V1 and an inverter V2. Please refer to FIG. 3 again, the inverter V1 and the inverter V2 are used to convert the clock signal CLK into the adjusted clock signal CLK_IN according to the level of the level control signal VDD_CLK. The amplitude of the adjusted clock signal CLK_IN is controlled by the level control signal VDD_CLK.

In step 240, following the above step 230, in stage I1 in FIG. 3, when the transistor T2 of the voltage clamp circuit 140A is gradually turned off, the voltage level of the level control signal VDD_CLK gradually decreases. The clock buffer 110A responds to the voltage level of the level control signal VDD_CLK, and the multiple pulses of the adjusted clock signal CLK_IN also gradually decrease as shown in stage I1 of FIG. 3, thereby determining the level change amount of the output signal HV in stage I1. As shown in FIG. 3, the level change amount of the output signal HV changes more drastically in the first stage of stage I1, and gradually slows down in stage I2.

The level of the output signal HV actually oscillates between the upper and lower limits of the preset voltage range as shown in Figure 3, and the pulses of the charge pump control signal CP_C, the level control signal VDD_CLK and the adjusted clock signal CLK_IN all respond to the synchronous change of the level of the output signal HV. For example, the level of the output signal HV can be 9 volts (V) or 10V, and the preset voltage range can be between ±5% and ±10% of the above level. The value of the preset voltage range can be designed according to actual needs and is not limited to the above example.

FIG. 5 is a circuit block diagram of a power supply circuit 100B according to some embodiments of the present disclosure. The power supply circuit 100B of FIG. 5 corresponds to the power supply circuit 100 of FIG. 1. The power supply circuit 100B includes a clock buffer 110B, a charge pump 120B, a control circuit 130B, and a voltage clamp circuit 140B. The voltage clamp circuit 140B includes a variable resistor R1. The variable resistor R1 is coupled between the system voltage VDD and the clock buffer 110B, and is controlled by the charge pump control signal CP_C. The connection method and operation of the clock buffer 110B, the charge pump 120B, and the control circuit 130B are similar to the corresponding components in the power supply circuit 100 of FIG. 1 and the power supply circuit 100A of FIG. 4A .

In some embodiments, the control circuit 130B includes a constant current source S1 and a variable current source S2. The variable current source S2 is coupled to the charge pump 120B and used to convert the output signal HV into a reference current I _HV , wherein the current value of the reference current I _HV is positively correlated with the voltage level of the output signal HV. The constant current source S1 is coupled to the variable current source S2 and used to output a reference current I _REF . In this embodiment, when the charge pump control signal CP_C is smaller, the voltage of the level control signal VDD_CLK is higher; conversely, when the charge pump control signal CP_C is larger, the voltage of the level control signal VDD_CLK is lower.

Specifically, when the voltage level of the output signal HV decreases, the level control signal VDD_CLK increases. Therefore, the pulse amplitude of the adjusted clock signal CLK_IN generated by the clock buffer 110B is higher than the clock signal CLK, so that the charge pump 120B raises the level of the output signal HV. When the voltage level of the output signal HV increases, the level of the charge pump control signal CP_C increases, causing the level of the level control signal VDD_CLK to decrease. Therefore, the pulse amplitude of the adjusted clock signal CLK_IN generated by the clock buffer 110B is lower than that of the clock signal CLK, so that the charge pump 120B pulls down the level of the output signal HV, thereby achieving the effect of adjusting the output signal HV.

As the level of the output signal HV generated by the charge pump 120B increases, the variable current source S2 is controlled by the output signal HV, so the output reference current I _HV increases. When the reference current I _HV is greater than the reference current I _REF , a current is generated from the node N1 to flow to the voltage clamp circuit 140B, and the capacitor C1 is charged, so that the level of the charge pump control signal CP_C gradually increases. In response to the increase in the level of the charge pump control signal CP_C, the resistance value of the variable resistor R1 of the voltage clamp circuit 140B gradually increases, resulting in a decrease in the level of the level control signal VDD_CLK. In addition, as the level of the output signal HV generated by the charge pump 120B decreases, the variable current source S2 is controlled by the output signal HV, so the output reference current I _HV decreases. When the reference current I _HV is lower than the reference current I _REF , the capacitor C1 discharges to the node N1, causing the level of the charge pump control signal CP_C to gradually decrease, and the resistance value of the variable resistor R1 of the voltage clamp circuit 140B gradually decreases, resulting in an increase in the level control signal VDD_CLK.

FIG. 6 is a circuit block diagram of a power supply circuit 100C according to some embodiments of the present disclosure. The power supply circuit 100C of FIG. 6 corresponds to the power supply circuit 100 of FIG. 1. The power supply circuit 100C includes a clock buffer 110C, a charge pump 120C, a control circuit 130C, and a voltage clamp circuit 140C. The control circuit 130C includes a voltage clamp circuit 141C. The connection and operation of the clock buffer 110C, the charge pump 120C, the control circuit 130C, and the voltage clamp circuit 140C are similar to the corresponding elements in the power supply circuit 100 of FIG. 1 , the power supply circuit 100A of FIG. 4A , and the power supply circuit 100B of FIG. 5 .

In some embodiments, different from the control circuit 130A and the control circuit 130B, the control circuit 130C includes a variable resistor R2 and a constant current source S1. The variable resistor R2 is coupled to the charge pump 120C and used to convert the output signal HV into a reference current _IHV . The constant current source S1 is coupled to the voltage clamp circuit 141C and used to generate a bias voltage at the node N1 according to the reference current _IHV and the impedance of the constant current source S1. The voltage clamp circuit 141C includes a variable resistor R2, and the variable resistor R2 is controlled by the output signal HV. The function of the variable resistor R2 is similar to that of the variable resistor R1. The larger the output signal HV is, the smaller the resistance value of the variable resistor R2 will be, so that the voltage clamp circuit 141C outputs a larger reference current I _HV . Accordingly, the voltage clamp circuit 140C can adjust the voltage level of the charge pump control signal CP_C according to the level of the output signal HV, thereby affecting the voltage level of the level control signal VDD_CLK. The operating principles of the clock buffer 110C and the charge pump 120C are the same as those of the corresponding components in the aforementioned embodiments, and will not be repeated.

FIG. 7 is a circuit block diagram of a power supply circuit 100D according to some embodiments of the present disclosure. The power supply circuit 100D of FIG. 7 corresponds to the power supply circuit 100 of FIG. 1. The power supply circuit 100D includes a clock buffer 110D, a charge pump 120D, a control circuit 130D, and a voltage clamp circuit 140D. The connection method and operation method of the clock buffer 110D and the charge pump 120D are similar to the corresponding clock buffer 110A and the charge pump 120A in FIG. 4A, respectively. For the sake of brevity, the relevant details are not repeated. In addition, the connection method and operation method of the control circuit 130D are similar to the control circuit 130A in FIG. 4A. The connection method and operation of the voltage clamp circuit 140D are similar to those of the voltage clamp circuit 140B in FIG. 5 or the voltage clamp circuit 140C in FIG. 6 . The details of the control circuit 130D and the voltage clamp circuit 140D can be found in FIGS. 4A to 6 , and will not be described in detail.

FIG. 8 is a circuit block diagram of a power supply circuit 100E according to some embodiments of the present disclosure. The power supply circuit 100E of FIG. 8 corresponds to the power supply circuit 100 of FIG. 1. The power supply circuit 100E includes a clock buffer 110E, a charge pump 120E, a control circuit 130E, and a voltage clamp circuit 140E. The connection method and operation method of the clock buffer 110E, the charge pump 120E, and the control circuit 130E are similar to the corresponding clock buffer 110A, the charge pump 120A, and the control circuit 130A in FIG. 4A, respectively. For the sake of brevity, only the details of the voltage clamp circuit 140E are described below.

In some embodiments, the voltage clamp circuit 140E includes a variable current source S3. The variable current source S3 is coupled to the node N1 of the control circuit 130E and is used to receive the system voltage VDD and the charge pump control signal CP_C, so as to output the level control signal VDD_CLK according to the level of the charge pump control signal CP_C. In this embodiment, when the charge pump control signal CP_C is smaller, the voltage of the level control signal VDD_CLK is higher; conversely, when the charge pump control signal CP_C is larger, the voltage of the level control signal VDD_CLK is lower.

In detail, as the level of the output signal HV generated by the charge pump 120E increases, the reference current I _HV increases. When the reference current I _HV is greater than the reference current I _REF , a shunt is generated from the node N1 to the voltage clamp circuit 140E, and the capacitor C1 is charged, so that the level of the charge pump control signal CP_C gradually increases, and the variable current source S3 of the voltage clamp circuit 140E responds to the voltage level of the charge pump control signal CP_C and reduces the output current I _C . In addition, as the level of the output signal HV generated by the charge pump 120E decreases, the reference current I _HV also decreases. When the reference current I _HV is lower than the reference current I _REF , the capacitor C1 discharges the node N1, causing the level of the charge pump control signal CP_C to gradually decrease. In response to the increase in the voltage level of the charge pump control signal CP_C, the variable current source S3 of the voltage clamp circuit 140E outputs a lower current _IC , that is, outputs a lower level control signal VDD_CLK to the clock buffer 110E. Since the level control signal VDD_CLK is generated according to the current _IC and the internal resistance of the clock buffer 110E, the larger the current _IC is, the larger the voltage of the level control signal VDD_CLK is, and vice versa.

FIG. 9 is a circuit block diagram of a power supply circuit 100F according to some embodiments of the present disclosure. The power supply circuit 100F of FIG. 9 corresponds to the power supply circuit 100 of FIG. 1. The power supply circuit 100F includes a clock buffer 110F, a charge pump 120F, a control circuit 130F, and a voltage clamp circuit 140F. The connection and operation of the clock buffer 110F, the charge pump 120F, and the voltage clamp circuit 140F are similar to the corresponding clock buffer 110A, the charge pump 120A, and the voltage clamp circuit 140A in FIG. 4A , respectively. For the sake of brevity, only the details of the control circuit 130F are described below.

In some embodiments, the control circuit 130F includes a Zener diode Z1, a transistor T1, and a current mirror circuit 131F. The current mirror circuit 131F is coupled to the transistor T1, and is used to replicate the reference current I _REF of the constant current source S1 to output it to the second end of the transistor T1. In some embodiments, the current mirror circuit 131F includes transistors T3 to T4. Transistor T3 is coupled to the node N1. The drain terminal of transistor T3 is coupled to the source terminal of transistor T1 and the ground terminal. The first end of the constant current source S1 is coupled to the system voltage VDD. The second end of the constant current source S1 is coupled to the drain terminal of the transistor T4. The source terminal of the transistor T4 is coupled to the ground terminal. The drain terminal and the gate terminal of transistor T4 are electrically connected to each other and connected to the gate terminal of transistor T3. It should be noted that the characteristic of the current mirror is that the output current of the current mirror can remain constant regardless of the load conditions. The current mirror circuit 131F is an analog circuit, but the content of this disclosure is not limited to this.

In some embodiments, the level control signal VDD_CLK and the output signal HV are both analog signals, but the present disclosure is not limited thereto. In addition, although in the above embodiments of the present disclosure, the level control signal VDD_CLK is inversely proportional to the charge pump control signal CP_C as a means to stabilize the output signal HV, in some derivative variations of the present disclosure, the level control signal VDD_CLK can be designed to be proportional to the charge pump control signal CP_C as a means to stabilize the output signal HV. For example, this can be achieved by adding an inverting circuit (such as an inverter) or changing the type of transistor switch (such as replacing PMOS with NMOS, or replacing NMOS with PMOS).

In some embodiments, transistors T1, T3 and T4 may be implemented by NMOS, and transistor T2 may be implemented by PMOS. However, the present disclosure is not limited thereto. For example, according to different designs of the charge pump control signal CP_C, transistor T2 may also be implemented by NMOS.

According to the above-mentioned embodiments, the present disclosure provides a power supply circuit and a dynamic voltage adjustment method. By designing the power supply circuit of the present disclosure, it is not necessary to use an amplifier to compare voltages to output a digital control signal, thereby continuously adjusting the output voltage of the charge pump within a preset voltage range. In addition, the power supply circuit can significantly reduce the component area and power consumption, thereby reducing the complexity of the circuit layout.

Although the present disclosure is disclosed in detail with the embodiments as above, the present disclosure does not exclude other feasible implementations. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application, rather than being limited by the aforementioned embodiments.

For those skilled in the art, various changes and modifications can be made to the disclosed content without departing from the spirit and scope of the disclosed content. Based on the above embodiments, all changes and modifications made to the disclosed content are also covered by the protection scope of the disclosed content.

100, 100A, 100B, 100C, 100D, 100E, 100F: power supply circuit 110, 110A, 110B, 110C, 110D, 110E, 110F: clock buffer 120, 120A, 120B, 120C, 120D, 120E, 120F: charge pump 130, 130A, 130B, 130C, 130D, 130E, 130F: control circuit 131F: current mirror circuit 140, 140A, 140B, 140C, 140D, 140E, 140F, 141C: voltage clamp circuit 200: method 210~240: step CP_C: charge pump control signal CLK: clock signal CLK_IN: adjusted clock signal C1: capacitor HV: output signal I1~I2: stage I _HV , I _REF : reference current _IC : current N1: node R1~R2: variable resistor S1: constant current source S2, S3: variable current source SG1~SGn: diode/capacitor unit T1~T4: transistor VDD: system voltage VDD_CLK: level control signal Z1: Zener diode

The present disclosure can be better understood by referring to the implementation methods in the subsequent paragraphs and the following figures: Figure 1 is a circuit block diagram of a power supply circuit according to some embodiments of the present disclosure; Figure 2 is a flow diagram of a dynamic voltage adjustment method according to some embodiments of the present disclosure; Figure 3 is a signal timing diagram of a power supply circuit according to some embodiments of the present disclosure; Figure 4A is a circuit block diagram of a power supply circuit according to some embodiments of the present disclosure; Figure 4B is a circuit architecture diagram of a clock buffer in the power supply circuit of Figure 4A; Figure 5 is a circuit block diagram of a power supply circuit according to some embodiments of the present disclosure; FIG. 6 is a schematic diagram of a circuit block of a power supply circuit according to some embodiments of the present disclosure; FIG. 7 is a schematic diagram of a circuit block of a power supply circuit according to some embodiments of the present disclosure; FIG. 8 is a schematic diagram of a circuit block of a power supply circuit according to some embodiments of the present disclosure; and FIG. 9 is a schematic diagram of a circuit block of a power supply circuit according to some embodiments of the present disclosure.

100: Power supply circuit

110: Clock buffer

120: Charge pump

130: Control circuit

140: Voltage clamp circuit

CP_C: Charge pump control signal

CLK: clock signal

CLK_IN: adjusted clock signal

HV: output signal

VDD_CLK: Level control signal

VDD: system voltage

Claims (9)

A power supply circuit includes: a clock buffer, used to generate an adjusted clock signal according to a clock signal and a level control signal, wherein the clock signal has a preset level; a charge pump, coupled to the clock buffer, and used to generate an output signal according to the adjusted clock signal and a system voltage; a control circuit, coupled to the charge pump, and used to generate an output signal according to the adjusted clock signal and a system voltage. The output signal generates a charge pump control signal; and a first voltage clamp circuit is coupled between the control circuit and the clock buffer and is used to receive the system voltage and the charge pump control signal, wherein the first voltage clamp circuit generates the level control signal according to the charge pump control signal, and the adjusted clock signal has an adjusted level in response to the level of the level control signal. A power supply circuit as described in claim 1, wherein the control circuit comprises: a constant current source, the constant current source is used to output a first reference current, and the control circuit is used to generate a second reference current according to the output signal, and generate the charge pump control signal according to the first reference current and the second reference current. A power supply circuit as described in claim 2, wherein the first voltage clamping circuit further comprises a first variable resistor, a resistance value of which varies with the level of the charge pump control signal, wherein the control circuit further comprises: a second voltage clamping circuit coupled to the charge pump and the constant current source, and used to generate the second reference current according to the output signal, wherein the second voltage clamping circuit comprises: a second variable resistor, a resistance value of which varies with the level of the output signal to adjust the level of the second reference current. The power supply circuit as described in claim 2, wherein the control circuit further comprises: a variable current source coupled to the charge pump and the constant current source and used to convert the output signal into the second reference current; wherein the first voltage clamp circuit comprises: a first variable resistor, a resistance value of the first variable resistor changes with the level of the charge pump control signal. The power supply circuit as described in claim 2, wherein the control circuit further comprises: a Zener diode coupled to the charge pump and used to output a second reference current according to the output signal; and a first transistor, the first end of the first transistor is coupled to the Zener diode, and the second end of the first transistor is coupled to the constant current source. The power supply circuit as described in claim 5, wherein the first voltage clamping circuit further comprises: a first variable resistor, a resistance value of the first variable resistor changes with the level of the charge pump control signal. The power supply circuit as described in claim 5, wherein the first voltage clamping circuit further comprises: a variable current source coupled to the control circuit and used to receive the system voltage, wherein the level of an output current of the variable current source varies with the level of the charge pump control signal, and the level of the level control signal is proportional to the level of the output current. A power supply circuit as described in claim 5, wherein the first voltage clamping circuit comprises: a second transistor having: a first end for receiving the system voltage; a second end coupled to the clock buffer for outputting the level control signal to the clock buffer; and a control end coupled to the control circuit for receiving the charge pump control signal. A power supply circuit as described in claim 8, wherein the control circuit further comprises: a third transistor, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor and a ground terminal; and a fourth transistor, wherein the first terminal of the constant current source is coupled to the system voltage, the second terminal of the constant current source is coupled to the first terminal of the fourth transistor, the second terminal of the fourth transistor is coupled to the ground terminal, and the control terminal of the fourth transistor is coupled to the first terminal of the fourth transistor and the control terminal of the third transistor.

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