TWM498327U - Display gate drive circuit structure - Google Patents

Description

Display gate drive circuit structure 【0001】

This creation is a drive circuit structure, especially a gate drive circuit structure of a display.

【0002】

In a liquid crystal display, each pixel has a thin film transistor (TFT) whose gate is connected to a horizontal scanning line and the drain is connected to a vertical data line. The source is connected to the pixel electrode. If a sufficient positive voltage is applied to a certain scanning line in the horizontal direction, all the TFTs on the line will be opened, and the pixel electrodes on the line will be connected with the vertical data lines, and the display signals on the data lines will be displayed. The voltage is written into the pixels to control the transmittance of different liquid crystals to achieve the effect of controlling the color.

[0003]

At present, the driving circuit of the liquid crystal display is mainly completed by the external IC of the panel, and the CMOS process is used. The GOA technology, Gate Driver on Array, is a technology that directly fabricates gate driver ICs on an Array substrate instead of a driver chip fabricated from an external germanium wafer. . The application of this technology can be directly around the panel, reducing the production process and reducing product cost and volume.

[0004]

However, as the resolution of the panel becomes higher and higher, the area of the frame of the display device is continuously compressed. At this time, the GOA drive circuit must reduce its area relative to each other. The general practice is to reduce the thin film transistor and capacitor, but this will cause the power characteristics to change and affect the display characteristics of the panel. For example, the drive circuit may be insufficiently driven. .

[0005]

Therefore, the present invention provides a gate drive circuit structure for a display in response to the above problems.

[0006]

One of the purposes of the present invention is to provide a gate driving circuit structure for a display, which reduces the circuit area of the signal generating circuit by overlapping the thin film transistor and the capacitor in the signal generating circuit of the gate driving circuit to reduce the overall The circuit area of the gate drive circuit, and thus the effect of the narrow border of the display.

【0007】

In order to achieve the above-mentioned various purposes and effects, the present invention discloses a gate driving circuit structure of a display, which includes a plurality of signal generating circuits for generating a plurality of scanning signals and outputting the scanning signals. To a display panel, the signal generating circuits respectively comprise: a thin film transistor for turning on or off to output a scanning signal; an insulating layer above the thin film transistor, the insulating layer having a first connecting hole and a a first conductive film, located above the insulating layer and the thin film transistor, and electrically connected to the first metal layer via the first connection hole; and a second conductive film located on the first conductive film and insulating The second conductive layer is electrically connected to the second metal layer via the second connection hole; wherein the first conductive film and the second conductive film overlap the film transistor, and the first conductive film and the second film The conductive films are separated by a distance to form a capacitor.

[0008]

The present invention further discloses a gate driving circuit structure of a display, which includes a plurality of signal generating circuits for generating a plurality of scanning signals, and outputting the scanning signals to a display panel, the signal generating circuits respectively The method comprises: a first thin film transistor, one end of the first thin film transistor is electrically connected to a first contact, the first contact is located at a first metal layer; and the second thin film transistor is at one end of the second thin film transistor Located in a second metal layer, the first metal layer is located above the second metal layer; an insulating layer is located above the first thin film transistor and the second thin film transistor and a third thin film transistor, and the insulating layer has a first a first conductive film is disposed above the insulating layer, the first thin film transistor, the second thin film transistor and the third thin film transistor, and electrically connected through the first connection hole a contact and a second metal layer; and a second conductive film on the first conductive film, the insulating layer, the first thin film transistor, the second thin film transistor and the third thin film transistor And electrically connecting a second contact via the second connection hole, the second contact being located in the first metal layer; wherein the first conductive film and the second conductive film overlap the third thin film transistor, and first The conductive film is spaced apart from the second conductive film to form a capacitor.

1‧‧‧ display
10‧‧‧ display panel
12‧‧‧ gate drive circuit
121-124, 221-222‧‧‧ signal generation circuit
1210‧‧‧ Pull-up circuit
1212‧‧‧ Pulldown circuit
14‧‧‧Source drive circuit
16‧‧‧Sequence Control Circuit
201, 301, 401‧‧‧ substrates
202, 302‧‧‧ semiconductor layer
203, 204, 303, 304‧‧‧ electrodes
205, 305, 405‧ ‧ insulation
206, 207, 306, 307, 406, 407‧‧‧ conductive film
208, 209, 308, 309, 408, 409‧‧‧ dielectric layers
410‧‧‧ first joint
411‧‧‧Endpoint
412‧‧‧second junction
C1, C2‧‧‧ capacitor
CLK‧‧‧ clock signal
H1, H3‧‧‧ first connection hole
H2, H4‧‧‧ second connection hole
M1, M2, M3, M4, M5‧‧‧ film transistors
MT1, MT2‧‧‧ metal layer
SC1-SC4‧‧‧ scan signal
STV‧‧‧ start signal
V _SS ‧‧‧reference voltage terminal

【0009】

Figure 1 is a schematic view of the drive system of the display of the present invention;
2 is a circuit diagram of a gate driving circuit of a preferred embodiment of the present invention;
Figure 3 is a circuit diagram of a signal generating circuit of a preferred embodiment of the present invention;
Figure 4 is a schematic diagram showing the layout of a conventional signal generating circuit;
Figure 5 is a cross-sectional view of a conventional signal generating circuit;
FIG. 6 is a schematic diagram showing the layout of a signal generating circuit according to a preferred embodiment of the present invention;
Figure 7 is a cross-sectional view showing a signal generating circuit of a preferred embodiment of the present invention; and Figure 8 is a cross-sectional view showing a signal generating circuit of another preferred embodiment of the present invention.

[0010]

In order to give your reviewers a better understanding and understanding of the characteristics of the creation and the efficacies achieved, please provide a better example and a detailed description of the following:

[0011]

Please refer to FIG. 1 , which is a schematic diagram of the driving system of the display of the present invention. As shown, the display 1 includes a display panel 10, a gate drive circuit 12, a source drive circuit 14, and a timing control circuit 16. The gate driving circuit 12 generates and transmits a plurality of scanning signals to the display panel 10 to drive the display panel 10. The source driving circuit 14 uses the complex gamma voltage as a complex reference voltage, and selects the reference voltages according to the plurality of display data to generate and transmit the complex data signals to the display panel 10. The display panel 10 displays images according to the data signals. The timing control circuit 16 generates a scan control signal and a data control signal, and transmits the scan control signal to the gate drive circuit 12 and the data control signal to the source drive circuit 14 to control the gate drive circuit 12 and the source drive circuit. 14 transmitting the scan signals and the timings of the data signals to the display panel 10.

[0012]

Please refer to FIG. 2, which is a circuit diagram of a gate driving circuit of a preferred embodiment of the present invention. As shown, the gate driving circuit 12 includes complex signal generating circuits 121-124, which may be respectively a shift register, and the signal generating circuits 121-124 receive The timing control circuit 16 outputs a scan signal CLK and an enable signal STV, and sequentially generates and outputs the complex scan signals SC1-SC4 according to the clock signal CLK and the start signal STV.

[0013]

However, since there are many ways of connecting the signal generating circuits 121-124 of the gate driving circuit 12, and the connection manner thereof is not the technical focus of the present creation, the present invention only introduces the basic one in FIG. The manner in which the signal generating circuits 121-124 are connected is not intended to limit the art of the present invention.

[0014]

Please refer to FIG. 3, which is a circuit diagram of a signal generating circuit in accordance with a preferred embodiment of the present invention. Since the circuit structures of the signal generating circuits 121-124 are the same, the present invention is only described by the signal generating circuit 121. As shown, the signal generating circuit 121 includes a plurality of thin film transistors M1-M3, a plurality of capacitors C1-C2, a pull-up circuit 1210, and a pull-down circuit 1212. A gate of the thin film transistor M1 is coupled to the pull-up circuit 1210. One source of the thin film transistor M1 is coupled to the pull-down circuit 1212, and one of the thin film transistors M1 receives the clock signal CLK, and the thin film transistor M1 is used. Turns on or off to output the scan signal SC1. A gate of the thin film transistor M2 is coupled to the gate of the thin film transistor M1, and a source of the thin film transistor M2 is coupled to a reference voltage terminal Vss. One of the gates of the thin film transistor M3 is coupled to one of the gates of the thin film transistor M2, and one of the thin film transistors M3 is coupled to the gate of the thin film transistor M1, and one source of the thin film transistor M3 is coupled to the reference voltage terminal Vss. The capacitor C1 is coupled between the gate and the source of the thin film transistor M1. One end of the capacitor C2 receives the clock signal CLK, and the other end is coupled to the drain of the thin film transistor M2 and the gate of the thin film transistor M3.

[0015]

The thin film transistors M1-M3 of the present embodiment are N-type gold oxide half field effect transistors (N-MOSFET), but the creation is not limited thereto, and the thin film transistors M1-M3 may also be replaced by P-type gold. Oxygen half field effect transistor (P-MOSFET).

[0016]

Please refer to FIG. 4 and FIG. 5 together. FIG. 4 is a schematic diagram of the layout of a conventional signal generating circuit, and FIG. 5 is a cross-sectional view of a conventional signal generating circuit (a cross-sectional view of a hatching line A-A'). As shown in FIG. 4, the conventional signal generating circuits 221-222 are arranged in such a manner that the capacitor C1 is disposed beside the thin film transistor M1, and the capacitor C2 is disposed beside the thin film transistor M2-M5, wherein the thin film transistor M4 is M5 is a transistor inside the pull-up circuit 1210 and the pull-down circuit 1212.

[0017]

5 is a cross-sectional view taken along line A-A' of FIG. 4. As shown, a substrate 201, a semiconductor layer 202, an electrode 203 and an electrode 204 are located on a metal layer MT1, and the semiconductor layer 202, The electrode 203, the electrode 204 and the metal layer MT2 form a thin film transistor M1, the electrode 204 extends a part of the upper electrode of the capacitor C1, and the metal layer MT2 serves as a lower electrode of the capacitor C1, and the electrode 204 extends The metal layer MT2 is separated by a distance to form a capacitor C1. An insulating layer 205 is located above the metal layer MT1, that is, above the thin film transistor M1. A conductive film 206 and a conductive film 207 are both located above the insulating layer 205. In addition, a dielectric layer 208 is further included between the insulating layer 205 and the second metal layer MT2, and a dielectric layer 209 is further disposed over the insulating layer 205. The electrode 203 and the electrode 204 can be used as the drain or source of the thin film transistor M1 according to the type of the thin film transistor M1 (NMOS or PMOS).

[0018]

As can be seen from the above, the conventional signal generating circuits 221-222 set the capacitor C1 beside the thin film transistor M1 and the capacitor C2 beside the thin film transistors M2 and M3, thus occupying an excessive circuit area.

[0019]

Please refer to FIG. 6, which is a schematic diagram of the layout of the signal generating circuit of a preferred embodiment of the present invention. As shown in the figure, the signal generating circuit of the present invention is arranged by overlapping the capacitor C1 with the thin film transistor M1 and overlapping the capacitor C2 with the thin film transistors M2 and M4. In this way, the circuit area of the signal generating circuit can be reduced.

[0020]

Please refer to FIG. 7, which is a cross-sectional view of a signal generating circuit of a preferred embodiment of the present invention (ie, a cross-sectional view taken along line B-B' of FIG. 6). As shown, a substrate 301, a semiconductor layer 302, an electrode 303 and an electrode 304 are located on the metal layer MT1, and the gate of the thin film transistor M1 is located in the metal layer MT2, the semiconductor layer 302, the electrode 303, and the electrode 304. The metal layer MT2 forms a thin film transistor M1, and the metal layer MT2 is located below the metal layer MT1. An insulating layer 305 is located above the metal layer MT1, that is, above the thin film transistor M1, and the insulating layer 305 has a first connecting hole H1 and a second connecting hole H2. A conductive film 306 is disposed above the insulating layer 305 and the thin film transistor M1, and is electrically connected to the metal layer MT1 via the first connection hole H1, that is, electrically connected to the electrode 304 of the thin film transistor M1. A conductive film 307 is disposed above the conductive film 306, the insulating layer 305 and the thin film transistor M1, and is electrically connected to the metal layer MT2 via the second connection hole H2, that is, electrically connected to the gate of the thin film transistor M1. The conductive films 306 and 307 are overlaid over the thin film transistor M1, and the conductive films 306 and 307 are separated by a distance to form a capacitor C1. In addition, a dielectric layer 308 is further disposed between the insulating layer 305 and the metal layer MT2, and a dielectric layer 309 is further disposed over the insulating layer 305. The dielectric layer 309 is located between the conductive films 306 and 307.

[0021]

The thin film transistor M1 of the embodiment may be an N-type metal oxide half field effect transistor (N-MOSFET) or a P-type gold oxide half field effect transistor (P-MOSFET). If the thin film transistor M1 is an N-type gold oxide half field effect transistor, the electrode 303 is the drain of the thin film transistor M1, and the electrode 304 is the source of the thin film transistor M1. On the other hand, if the thin film transistor M1 is a P-type MOS field effect transistor, the electrode 303 is the source of the thin film transistor M1, and the electrode 304 is the drain of the thin film transistor M1.

[0022]

Please refer to FIG. 8, which is a cross-sectional view of a signal generating circuit of another preferred embodiment of the present invention (ie, a cross-sectional view taken along line C-C' of FIG. 6). As shown in the figure, the signal generating circuit 122 is formed on a substrate 401, and one end of the thin film transistor M2 is electrically connected to a first contact 410, and the first contact 410 is located on the metal layer MT1. One end 411 of the thin film transistor M3 is located on the metal layer MT2. In this embodiment, the end point 411 of the thin film transistor M3 is its gate. An insulating layer 405 is disposed above the thin film transistors M2-M4, and the insulating layer 405 has a first connecting hole H3 and a second connecting hole H4. A conductive film 406 is disposed above the insulating layer 405 and the thin film transistors M2-M4, and is electrically connected to the first contact 410 and the end point 411 of the thin film transistor M3 in the metal layer MT2 via the first connection hole H3. A conductive film 407 is disposed above the conductive film 406, the insulating layer 405, and the thin film transistors M2-M4, and is electrically connected to a second contact 412 via the second connection hole H4. The second contact 412 is located on the metal layer MT1. The conductive film 406 and the conductive film 407 are overlapped over the film transistors M2 and M4, and the first conductive film 406 is spaced apart from the second conductive film 407 to form a capacitor C2. In addition, a dielectric layer 408 is further disposed between the insulating layer 405 and the metal layer MT2, and a dielectric layer 409 is further disposed over the insulating layer 405. The dielectric layer 409 is located between the conductive films 406 and 407.

[0023]

The drain or the source of the thin film transistor M1 of the present embodiment (the drain or the source of the transistor type) is located at the second contact 412, that is, the conductive film 407 is electrically connected through the second connection hole H4. The drain or source of the thin film transistor M1, and the conductive film 407 receives the clock signal CLK through the path.

[0024]

In summary, the gate driving circuit structure of the display of the present invention reduces the circuit area of the signal generating circuit by overlapping the thin film transistor and the capacitor in the signal generating circuit of the gate driving circuit to reduce the overall gate The circuit area of the pole drive circuit, which in turn achieves the effect of the narrow border of the display.

[0025]

However, the above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the scope of the patent application. , should be included in the scope of the patent application of this creation.

[0026]

This creative department is a novelty, progressive and available for industrial use. It should meet the requirements of patent applications stipulated in China's Patent Law. It is undoubtedly a new type of patent application, and the Prayer Council will grant patents as soon as possible. prayer.

121‧‧‧Signal generation circuit

122‧‧‧Signal generation circuit

C1‧‧‧ capacitor

C2‧‧‧ capacitor

M1‧‧‧film transistor

M2‧‧‧film transistor

M3‧‧‧film transistor

M4‧‧‧film transistor

M5‧‧‧film transistor

Claims (11)

[Item 1] A gate driving circuit structure of a display, comprising a plurality of signal generating circuits, wherein the signal generating circuits are configured to generate a plurality of scanning signals, and output the scanning signals to a display panel, wherein the signal generating circuits respectively comprise:
a thin film transistor for turning on or off to output the scan signal;
An insulating layer is disposed above the thin film transistor, the insulating layer has a first connecting hole and a second connecting hole;
a first conductive film is disposed above the insulating layer and the thin film transistor, and is electrically connected to a first metal layer via the first connecting hole; and a second conductive film is disposed on the first conductive film and the insulating layer a layer above the thin film transistor, and electrically connected to a second metal layer via the second connection hole;
The first conductive film and the second conductive film overlap the film transistor, and the first conductive film and the second conductive film are separated by a distance to form a capacitor. [Item 2] The gate driving circuit structure of claim 1, wherein the first metal layer is located between the second metal layer and the insulating layer. [Item 3] The gate driving circuit structure of claim 1, wherein a source of one of the thin film transistors is located in the first metal layer, and a gate of the thin film transistor is located in the second metal layer, the first An electrically conductive film is electrically connected to the source of the thin film transistor via the first connection hole, and the second conductive film is electrically connected to the gate of the thin film transistor via the second connection hole. [Item 4] The gate driving circuit structure of claim 1, wherein one of the thin film transistors is located in the first metal layer, and one of the thin film transistors is located in the second metal layer, the first A conductive film is electrically connected to the drain of the thin film transistor via the first connection hole, and the second conductive film is electrically connected to the gate of the thin film transistor via the second connection hole. [Item 5] The gate driving circuit structure of claim 1, further comprising a dielectric layer between the first conductive film and the second conductive film. [Item 6] A gate driving circuit structure of a display, comprising a plurality of signal generating circuits, wherein the signal generating circuits are configured to generate a plurality of scanning signals, and output the scanning signals to a display panel, wherein the signal generating circuits respectively comprise:
a first thin film transistor, one end of the first thin film transistor is electrically connected to a first contact, the first contact is located in a first metal layer;
a second thin film transistor, one end of the second thin film transistor is located in a second metal layer, and the first metal layer is located above the second metal layer;
An insulating layer is disposed above the first thin film transistor and the second thin film transistor and a third thin film transistor, the insulating layer has a first connecting hole and a second connecting hole;
a first conductive film is disposed above the insulating layer, the first thin film transistor, the second thin film transistor and the third thin film transistor, and electrically connected to the first contact via the first connection hole The second metal layer; and a second conductive film is disposed over the first conductive film, the insulating layer, the first thin film transistor, the second thin film transistor, and the third thin film transistor The second connection hole is electrically connected to a second contact, the second contact is located in the first metal layer;
The first conductive film and the second conductive film overlap the third thin film transistor, and the first conductive film and the second conductive film are separated by a distance to form a capacitor. [Item 7] The gate driving circuit structure of claim 6, wherein one of the gates of the second thin film transistor is located in the second metal layer, and the first conductive film is electrically connected to the first conductive film via the first connection hole. The first contact and the gate of the second thin film transistor. [Item 8] The gate driving circuit structure of claim 6, wherein one of the third thin film transistors is located at the second contact of the first metal layer, and the second conductive film is connected to the second conductive film. The hole is electrically connected to the drain of the third thin film transistor. [Item 9] The gate driving circuit structure of claim 6, wherein a source of one of the third thin film transistors is located at the second contact of the first metal layer, and the second conductive film is connected to the second conductive film The hole is electrically connected to the source of the third thin film transistor. [Item 10] The gate driving circuit structure of claim 6, wherein the second conductive film is electrically connected to the first metal layer via the second connection hole to receive a clock signal. [Item 11] The gate driving circuit structure of claim 6, further comprising a dielectric layer between the first conductive film and the second conductive film.