M331733 ，八、新型說明： 7【新型所屬之技術領域】 、 本創作係有關於一種記憶體選取裝置，更詳而言之， •係關於一種可於電子裝置之第一、第二靜態隨機存取記憶 體之間執行記憶體選取動作之記憶體選取裝置。 【先前技術】 隨著電腦科技和高速設備的不斷開發，對資料儲存容 里及資料傳輸率的要求也越來越高。而由於傳輸方式的不 同，各種向速設備在運行時能否實現可靠的資料交換就顯 得十分重要。其中，高速雙SRAM(Static Rand〇m AccessM331733, eight, new description: 7 [new technical field], this creation is about a memory selection device, in more detail, is related to a first and second static random storage of electronic devices A memory selection device that performs a memory selection operation between memories. [Prior Art] With the continuous development of computer technology and high-speed equipment, the requirements for data storage capacity and data transmission rate are also increasing. Due to the different transmission methods, it is very important to realize reliable data exchange when various speeding devices are running. Among them, high-speed dual SRAM (Static Rand〇m Access
Memory，靜態隨機存取記憶體）的出現對於高速設備則提 供了可靠的資料交換效能。以常見之SRAM型號cy62128 為例，其係為 BMC(Baseboard Management Controller， 基板管理控制器）提供之SRAM，一個（^62128的容量是 128K X 8 Bit ’單片的CY62m的容量不能滿足系統的需 要，故於電子裝置中會使用二片CY62128,故而BMC的晶 片需要對這二片SRAM進行記憶體晶片的選取，以供電子 裝置於所選取之SRAM+進行對應之讀寫動作。’、 ， 明麥閱第1圖’係顯示習知技術中所採用的於二片例 如CYf 2128之SRAM中執行記憶體選取之設計電路圖。如 圖=，對於第—SRAM10,該㈣2之第一輸出接腳12〇 弟—輪出接腳122係透過第-轉換單元14的第一 S疆〇之例如接腳CS—N電性連接，其中，該第:=接 腳120係用以產生第一控制訊號，該第二輪出接腳Μ? M331733 係用以產生第二控制訊號，該第一控制訊號與第二控制訊 :，經該第—轉換單元14之訊號處理後產生-具有第-狀 、態值之選擇訊號輸出至該第一 SRAM1 〇之接腳cs—N，以供 • •選取該第一 SRAM10;而對於第二SRAMU，該MC12之第 * 一輸出接腳120與第二轉換單元16電性連接，並連同第 二輪出接腳122透過第三轉換單元18與第二SRAMU之接 腳CS_N電性連接，其中，該第一控制訊號與第二控制訊 號經該第二、第三轉換單元14、16之訊號處理後產生— _具有第二狀態值之選擇訊號並輸出至該第二sRMi2之接 腳CS_N，以供選取該第二SRAM12。於本實施例中，該第 一、第二轉換單元14、18係例如由或閘（〇R Gate )及其 周邊電子元件與線路所組成，該第二轉換單元16係例: 由反閘（NOT Gate )及其周邊電子元件與線路所組成。故 訊號之間的邏輯關係可以描述如下，當第二控制訊號為高 位準％，第一、第二SRAM10、11均不能被致能，當第二 鲁控制訊號為低位準時，第一、第三轉換單元14^ 8之或 閘被開啟。且當第一控制訊號為低位準時，則經由該第一 .轉換單元14之訊號轉換後產生具有第一狀態值之選擇訊 ，號（低位準訊號）至該第一 SRAM10之接腳CS_N，藉以選取 該第一 SRAM10，以供該電子裝置使用該第一 SRM 1〇 ;而 當苐一控制訊號為高位準時，經由該第二、第三轉換單元 16、18之訊號轉換後產生具有第二狀態值之選擇訊號（低 位準訊號）並輸出至該第二SRAM11之接腳CS_N，以供該 電子裝置使用該第二SRAM 11。 7 M331733 惟，於上述電路圖中，僅利用SRAM之單一接腳cs一N， -即將該控制訊號均輸入至該SRM之單一接腳Μ以完成 、A 體廷取作業。為此，需額外配置有例如由或閘及其周 • 子τΜ牛與線路所組成之第—、第三轉換單元 乂及由反閘及其周邊電子元件與線路所組成第二轉換單 元16以只現控制訊號之訊號轉換並產生具有第一狀態 值之選擇訊號及第二狀態值之選擇訊號，藉以選取該第一 SRAM 10或第二SRAM u，造成選取電路過於繁鎖，且相 _對而s ’增加電路設計之整體成本。 因此，如何提供一種電路簡單之記憶體選取裝置，藉 以克服，知記憶體選取設計中電路設計複雜、元件繁多: 成本較南之弊端，且可相應節省設計空間，遂成為目前亟 待解決之問題。 【新型内容】 鑒於上述習知技術之缺失，本創作之主要目的在於提 籲，一種記憶體選取裝置，以可於電子裝置之第一、第二靜 態隨機存取記憶體之間執行記憶體選取動作。 本創作之另一目的在於提供一種設計簡單且可節省 -佈局空間之記憶體選取裝置。 為達上述目的以及其他目的，本創作即提供一種記憶 ，選取裝.置，係應用於-具有第―、第二靜態隨機存取 憶體（Static Random ACCess Memory，SRAM)之電子裝置 中，其中，該第一、第二靜態隨機存取記憶體係分別具有 第一輸入接腳及第二輸入接腳，該記憶體選取裝置係包 8 M331733 理控制器:係具有第-輪出接腳及第二輸出接 腳/、中，该基板官理控制器之第_於中 一、第—轉能_ #六& 知出接腳係與該第 弟-靜心機存取記憶體之第一輪入接腳 ，基板管理控制器之第二輸出接腳係與該第 妾機 存取記憶體之第二輸人接腳電性連接，該基板管畔= 係用以產生致能訊號並經由該第一輸出接腳輪出，：：： :-具有第-狀態值之選擇訊號經由該第二輸出接腳輸 出，以及轉換單元’係與該基板管理控制器之第二 腳及第-靜態隨機存取記憶體之第二輸人接腳電性連 接，用以對該基板管理㈣n輸出的選擇訊號進行轉換声 理，以將該選擇訊號由第一狀態值轉換為第二狀態二，、= 將該第二狀態值之選擇訊號輸出至該第—靜態隨機存取 記憶體之第二輸人接腳，俾當該第―、第二靜態隨機存取 記憶體之第一輸入接腳接收到該基板管理控制器輸出的 致能訊號而處於致能狀態時，藉由該基板管理控制器輪出 的具有第一狀態值之選擇訊號及經該轉換單元轉^而輸 出的具有第二狀態值之選擇訊號選取該第一、第二靜態^ 機存取記憶體中之一者，以供該電子裝置使用。 上述該基板管理控制器之第二輸出接腳係與該第二 靜態隨機存取記憶體之第二輸入接腳之間係電性連接有 一電阻元件。 上述§己憶體選取震置中的轉換單元之具體實施方式 係包括反閘、提供電源予該反閘之供電電源、以及設於該 反閘與接地端之間的電容。 9 M331733 ’ 域記憶體選取裝置之具體實施方式係指該致能訊 -$係為低位準，第一狀態值之選擇訊號係為低位準，以及 .第一狀悲值之選擇訊號係為高位準，則選取該第一靜，熊隨 ，機存取記憶體；以及依據該致能訊號係為低位準，^二二 態值之選擇訊號係為高位準，以及第二狀態值之選擇訊號 係為低位準，則選取該第二靜態隨機存取記憶體。 相較於習知技術者，本創作之記憶體選取裝置主要係 透過將基板管理控制器之第一輸出接腳與該第一、第二靜 馨態隨機存取記憶體之第-輸人接腳電性連接，並將基板管 理控制益之第二輸出接腳與該第二靜態隨機存取記憶體 j第二輸入接腳電性連接以及經由一轉換單元與第一靜 恶隨機存取記憶體之第二輸入接腳電性連接，俾當第一、 第一 p迎機存取記憶體之第一輸入接腳接收 管理控制器輸出的致能訊號而處於致能狀態時，藉由^基 板^理控制器輸出的具有第一狀態值之選擇訊號及經轉 鲁2單7L轉換並輸出的具有第二狀態值之選擇訊號選取該 第一、第二靜態隨機存取記憶體中之一者，以供該電子裝 置使用，相較於習知技術，本創作之記憶體選取裝置不必 如白知技術須使基板管理控制器之第一、第二輸出接腳透 過^個轉換單元並電性連接至該第一、第二靜態隨機存取 記，體之輸入接腳即可實現相同之記憶體選取功能，因此 可間化電路結構，並達到節省電子零件、製造成本以及節 省設計空間的效果。 【實施方式】 10 M331733 ’ 以下係藉由特定的具體實例說明本創作之實施方 -式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 •瞭解本創作之其他優點與功效。本創作亦可藉由其他不同 •的具體貫例加以施行或應用，本說明書中的各項細節亦可 基於不同觀點與應用，在不悖離本創作之精神下進行各種 修飾與變更。 凊麥閱第2A圖，其係顯示本創作之記憶體選取裝置 之基本架構示意圖，本創作之記憶體選取裝置係應用於一 _具有第一靜態隨機存取記憶體2〇及第二靜態隨機存取記 憶體21之電子裝置中，其中，該第一靜態隨機存取記憶 體20係分別具有第一輸入接腳2〇〇及第二輪入接腳 202,且該第二靜態隨機存取記憶體21係分別具有第一輸 入接腳210及第二輸入接腳212。於本實施例中，該電子 裝置係為個人電腦、筆記型電腦，抑或為伺服器等其他資 料處理裝置。該第一、第二靜態隨機存取記憶體 _係以型號CY62128之靜態隨機存取記憶體⑺饨七“ RandQm Access Memory，SRAM)為例進行說明者。 如第2 A圖所示，本創作之記憶體選取裝置係包括具 ，有第一輸出接腳220及第二輸出接腳222之基板管理控制 器（Baseboard Management Controller，BMC)22、以及車备 換單元24。 該基板管理控制為2 2係至少具有第一輸出接腳2 2 〇 及第二輸出接腳222,其中，該第一輸出接腳22〇係與該 第一、第二靜態隨機存取記憶體20、21之第一輸入接腳 M331733 ’電性200、210電性遠接，兮* _ •-磚能P她+ 連接忒罘二輸出接腳222係與該第 :存取記憶體21之第二輸入接腳212電性連 J。管理控制器22係用以產生致能訊號並經由該 弟一輸出接腳220輪屮，u »文丄 摆翰出以及產生一具有第一狀態值之選 〇〜亚！由該第二輸出接腳222輸出。 該轉換單元24係與該基板㈣控制器22之第二輸出 fn9腳222及第—靜態隨機存取記憶體20之第二輸入接腳 電f生連接，用以對該基板管理控制器Μ輸出的選 Z進行轉換處理以產生—具有第二狀態值之選擇訊號 輸出。於本實施例中，該轉換單元24係例如由反閘及其 周邊電子兀件與線路所組成。 因此，透過上述記憶體選取裝置，^卑當該第一、第二 靜態隨機存取記憶體20、21之第一輸入接腳綱、21一〇 接，到4基板g理控制$ 22輸出的致能訊號而處於致能 狀恶時，ϋ由該基板管理控制器22輸出的具有第—狀態 值之遥擇汛唬及經由該轉換單元24輸出的具有第二狀能 值之選擇訊號來選取該第一或第二靜態隨機存取記f 體，以供該電子裝置使用。 一 復請參閱第2B圖，其係顯示本創作之記憶體選取裝 置之一具體實施例之電路示意圖，以下配合第2B圖詳^ 説明本創作之記憶體選取裝置之一較佳電路結構中各組 成元件之連接關係及其工作原理。 ' 如第2B圖所示，於本實施例中，該第一、第二靜態 隨機存取記憶體20、21之第一輸入接腳2〇〇、21〇係例如 12 M331733 一般靜態隨機存取記憶體晶片所具備的㈣cs N，而第 -輸入接腳202、212係例如_般靜態 二:斤具備的接腳CS，其中，該第一輸入接腳2〇二 二氏位準有效、该第二輸入接腳2()2、212係為高位準有 效。該基板管理控制器22係例如為一基板管 贿柳-CQntrGller，騰 第一輸出接腳220及第二輸出接腳222。其/，、該第二於 出接腳220係與該第一、第_靜 ^ 雨 — 矛—蛘您酼機存取記憶體20、 ^之弟一輸入接腳200、210雷枓遠垃·二斗μ m 299 ^ - 冤性連接，而該弟二輸出接 、2係/、该罘二靜態隨機存取記憶體21之第二 腳212電性連接。於本實施例中… 貝例肀該基板管理控制器22 出接腳222係與該第二靜態隨機存取記憶體Η 之弟-輸入接腳212之間係電性連接有一電阻元件別。 該轉換單元24係與該基板管理控制㈣之第二 =2及第一靜態隨機存取記憶體2。之第二輸入接腳 2,性連接。於本實施例中’該轉換單元24係包括反 甲(NOT Gate) 240、提供電源予該反閘24〇之供電電源 :、以及設於該反閘24〇與接地端之間供濾波之電容 :以對該第二輪出接腳m所輸出之選擇訊號執行位 =轉換處理以產生-具有第二狀態值之選擇訊號輸出。於 ^貫施射，該致能訊㈣為低位準有效，因此，該基板 吕理控制器22之第一輸出接腳22〇所輸出為第一狀離值 =選擇訊號，其中該第-狀態值係為低位準，並經過該反 甲 1 240使該第一狀態值由低位準轉為高位準以形成該第 13 M331733 ，二狀態值之選擇訊號，故就第—靜態隨機存取記憶體加 :之接聊cs而言’該第二狀態值之選擇訊號係為高位 ， 效。 • 本實施例電路結構之工作原理係如下所述：當第一、 第二靜態隨機存取記憶體2〇、21之第一輸入接：2〇。、、 210接收到該基板管理控制器22之第一輸出接腳22〇所 輸出之致能訊號（低位準訊號）時而處於致能狀態，因為第 一、第二靜態隨機存取記憶體2〇、21之接腳csji處於低 鲁位準訊號時為有效狀態，且#該基板㈣控制器&之第 二輸出接腳222所輸出之選擇訊號係為高位準時，即產生 具有第一狀態值之選擇訊號（高位準訊號）至該第二靜能 隨機存取記憶體21之第二輸入接腳212，因為第二靜 ，機存取記憶體21之接腳CS處於高位準訊號時為有效二 怨，故選取該第二靜態隨機存取記憶體2丨，以供該電子 裝置使用；而當該基板管理控制器22之第二輸出接腳M2 肇所輸出之選擇訊號係為低位準，則經由該轉換單元Μ之 訊號轉換（由低位準轉爲高位準）後產生具有第二狀態值 之選擇訊號（高位準訊號）至該第一靜態隨機存取記憶體 ’ 20之第二輸入接腳2〇2，因為第一靜態隨機存取記憶體 2〇之接腳CS處於高位準訊號時為效狀態，故選取該第一 靜恶隨機存取記憶體2 0，以供該電子裝置使用。 “上所述，相較於習知技術者，本創作之記憶體選取 裳置係透過將基板管理控制器之第一輸出接腳與該第 —、第二靜態隨機存取記憶體之第一輸入接腳電性連接， 14 M331733 並將基板s理控制益之第二輪出接腳與該第二記憶體之 第二輸入接腳電性連接以及經由一轉換單元與第一靜態 隨機2取記憶體之第二輸入接腳電性連接，俾當第一、第 一猙悲ik機存取記憶體之第一輸入接腳接收到該基板管 ，拴制态輪出的致能訊號而處於致能狀態時，藉由該基板 :理控制益輸出的具有第一狀態值之選擇訊號及轉換單 T輸出的具有第二狀態值之選擇訊號來選取該第一靜態 返枝存取。己h體或弟二靜態隨機存取記憶體，以供該電子 2置使用，相較於習知技術，本創作之記憶體選取裝置僅 ^利用記憶體所提供的輸入接腳來作為記憶體選取的判 斷’而不必如習知技術須使基板管理控制器之第一、第二 輸出接腳透過多個轉換單元並電性連接至該第一、第二靜 機存取記憶體之輸入接腳，因此，本創作之記憶體選 取衣置在貫現記憶體選取功能之同時，亦可達到簡化電路 結構、節省電子零件以及製造成本的目的，並可相應S省 設計空間。 上述實施例僅例示性說明本創作之原理及其功效，而 非用於限制本創作。任何熟習此項技藝之人士均可在不違 Z本創作之精神及範疇下，對上述實施例進行修飾與改 變。因此，本創作之權利保護範圍，應如後述之申於專 範圍所列0 月 【圖式簡單說明】 第1圖係為習知一用以對兩記憶體進行選取之設 電路示意圖； 15 M331733 / 第2A圖係為本創作之記憶體選取裝置之基本架構示 :意圖；以及 第2B圖係用以說明實現本創作之記憶體選取裝置之 電路範例。 ^【主要元件符號說明】 10 第一 SRAM 11 第二 SRAM 12 BMC 120 第一輸出接腳 122 第二輸出接腳 14 第一轉換單元 16 第二轉換單元 18 第三轉換單元 20 第一記憶體 21 第二記憶體 200、 210 第一輸入接腳 202、 212 第二輸入接腳 220 弟 輸出接腳 222 第二輸出接腳 22 基板管理控制器 24 轉換單元 240 反閘 242 供電電源 244 電容 26 電阻元件 16The emergence of Memory, Static Random Access Memory provides reliable data exchange performance for high speed devices. Take the common SRAM model cy62128 as an example. It is a SRAM provided by BMC (Baseboard Management Controller). One (^62128 capacity is 128K X 8 Bit'. The capacity of single-chip CY62m cannot meet the needs of the system. Therefore, two CY62128s are used in the electronic device. Therefore, the BMC chip needs to select the memory chips of the two SRAMs for the electronic device to perform corresponding reading and writing operations on the selected SRAM+. Referring to FIG. 1 ' is a design circuit diagram for performing memory selection in two SRAMs such as CYf 2128 used in the prior art. As shown in FIG. 2, for the first-SRAM 10, the first output pin 12 of the (4) 2 is used. The pin-pin 122 is electrically connected to the first S-switch of the first-conversion unit 14, for example, the pin CS-N, wherein the first:= pin 120 is used to generate the first control signal. The second round of the output pin? M331733 is used to generate the second control signal, the first control signal and the second control signal: after the signal processing by the first conversion unit 14 is generated - having the first state, the state value Select signal output to the first An SRAM1 pin cs_N for • selecting the first SRAM 10; and for the second SRAMU, the first output pin 120 of the MC 12 is electrically connected to the second conversion unit 16, and together with the second The switch pin 122 is electrically connected to the pin CS_N of the second SRAMU through the third conversion unit 18, wherein the first control signal and the second control signal are processed by the signals of the second and third conversion units 14 and 16. Then, the selection signal having the second state value is outputted to the pin CS_N of the second sRMi2 for selecting the second SRAM 12. In this embodiment, the first and second conversion units 14 and 18 are For example, it consists of a gate (R Gate) and its peripheral electronic components and lines. The second conversion unit 16 is composed of a reverse gate (NOT Gate) and its surrounding electronic components and lines. The logical relationship can be described as follows. When the second control signal is at a high level %, the first and second SRAMs 10 and 11 cannot be enabled. When the second control signal is low, the first and third conversion units 14^8 Or the gate is turned on, and when the first control signal is low When the signal is converted by the first conversion unit 14, the selection signal having the first state value (low level signal) is sent to the pin CS_N of the first SRAM 10, so that the first SRAM 10 is selected for The electronic device uses the first SRM 1〇; and when the first control signal is at a high level, the signal is converted by the second and third conversion units 16 and 18 to generate a selection signal having a second status value (low level signal) And outputting to the pin CS_N of the second SRAM 11 for the electronic device to use the second SRAM 11. 7 M331733 However, in the above circuit diagram, only the single pin cs-N of the SRAM is used, that is, the control signal is input to the single pin of the SRM to complete the work of the A body. To this end, it is necessary to additionally configure, for example, a first switching unit composed of a sluice gate and its τ Μ 与 与 and a line, and a second converting unit 16 composed of a reverse gate and its peripheral electronic components and lines. Only the signal of the control signal is converted and a selection signal having the first state value and the second state value is generated, thereby selecting the first SRAM 10 or the second SRAM u, thereby causing the selection circuit to be too complicated and And s 'increased the overall cost of circuit design. Therefore, how to provide a memory selection device with simple circuit can overcome the complicated circuit design and various components in the design of the memory selection: the cost is more disadvantageous than the south, and the design space can be saved accordingly, which has become a problem to be solved at present. [New content] In view of the above-mentioned lack of the prior art, the main purpose of the present invention is to provide a memory selection device for performing memory selection between the first and second static random access memories of the electronic device. action. Another object of the present invention is to provide a memory selection device that is simple in design and saves - layout space. In order to achieve the above and other purposes, the present invention provides a memory, which is applied to an electronic device having a first and a second static random access memory (SRAM), wherein The first and second static random access memory systems respectively have a first input pin and a second input pin, and the memory selection device is a package 8 M331733 controller: having a first-round pin and a first The second output pin/, the middle of the substrate management controller, the first one, the first one, the first one, the first one, the first one, the first one, the first one, the first one, the first one The second output pin of the substrate management controller is electrically connected to the second input pin of the second access memory, and the substrate tube is used to generate an enable signal and The first output pin is turned out, ::: :- the selection signal having the first state value is output through the second output pin, and the conversion unit is connected to the second leg and the first static random storage of the substrate management controller Taking the second input pin of the memory to be electrically connected, The substrate manages (4) the output signal of the n output to convert the sound to convert the selection signal from the first state value to the second state 2, and = output the selection signal of the second state value to the first static random access The second input pin of the memory, when the first input pin of the first and second static random access memory receives the enable signal output by the substrate management controller and is enabled, The selection signal having the first state value and the selection signal having the second state value outputted by the conversion unit are selected in the first and second static memory access memories. One of them is for use by the electronic device. A resistive element is electrically connected between the second output pin of the substrate management controller and the second input pin of the second static random access memory. The specific implementation manner of the conversion unit in the above-mentioned § recalling body includes a reverse gate, a power supply for supplying power to the reverse gate, and a capacitor disposed between the reverse gate and the ground. 9 M331733 'The specific implementation method of the domain memory selection device means that the enable message-$ is a low level, the selection signal of the first state value is a low level, and the selection signal of the first value is a high level. If the standard is selected, the first static, bear, machine access memory; and according to the enable signal is low, the selection signal of the second and second states is a high level, and the second state value selection signal If the level is low, the second static random access memory is selected. Compared with the prior art, the memory selection device of the present invention mainly connects the first output pin of the substrate management controller with the first input device of the first and second static random access memory. The electrical connection is electrically connected, and the second output pin of the substrate management control is electrically connected to the second input pin of the second static random access memory j and the first static random access memory via a conversion unit The second input pin of the body is electrically connected, and when the first input pin of the first and first p-on-access memory receives the enable signal output by the management controller and is enabled, by ^ The selection signal having the first state value outputted by the substrate controller and the selection signal having the second state value converted and outputted by the switch 2 are selected to select one of the first and second static random access memories. For the use of the electronic device, compared with the prior art, the memory selection device of the present invention does not have to pass the first and second output pins of the substrate management controller through the conversion unit and the power. Sexual connection to the first, first A static random access in mind, the body of the input pins of the memory can be selected to achieve the same function, and therefore may be inter-circuit structure, to achieve savings and electronic parts, manufacturing cost and space saving design effect. [Embodiment] 10 M331733 </RTI> The following describes the implementation of the present invention by a specific specific example, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present specification. The creations may be carried out or applied by other specific embodiments. The details of the present specification can also be modified and changed without departing from the spirit of the present invention. FIG. 2A is a schematic diagram showing the basic structure of the memory selection device of the present invention. The memory selection device of the present invention is applied to a first static random access memory 2 and a second static random. In the electronic device for accessing the memory 21, the first SRAM 20 has a first input pin 2〇〇 and a second wheel input pin 202, respectively, and the second static random access device The memory 21 has a first input pin 210 and a second input pin 212, respectively. In this embodiment, the electronic device is a personal computer, a notebook computer, or another server processing device such as a server. The first and second static random access memory_ are described by taking the static random access memory (7) of the model CY62128 and the "RandQm Access Memory (SRAM)" as an example. As shown in FIG. 2A, the creation The memory selection device includes a baseboard management controller (BMC) 22 having a first output pin 220 and a second output pin 222, and a vehicle replacement unit 24. The substrate management control is 2 2 has at least a first output pin 2 2 〇 and a second output pin 222, wherein the first output pin 22 is the first of the first and second static random access memories 20, 21 The input pin M331733 'electricity 200, 210 is electrically connected, 兮* _ • - brick can P her + connection 输出 second output pin 222 and the second access pin 212 of the access memory 21 Electrical controller J. The management controller 22 is configured to generate an enable signal and rim through the output pin 220 of the younger one, and to generate a first state value. The second output pin 222 is outputted. The conversion unit 24 is connected to the substrate (4) controller 22 The second output fn9 pin 222 and the second input pin of the first static random access memory 20 are electrically connected to perform a conversion process on the selected Z of the substrate management controller to generate a second state value. In the present embodiment, the conversion unit 24 is composed of, for example, a reverse gate and its peripheral electronic components and lines. Therefore, through the memory selection device, the first and second static When the first input pin of the random access memory 20, 21 is connected to the 21st, and the enable signal of the output of the 22 substrate is controlled to be enabled, the substrate management controller 22 Selecting the first or second static random access f body with the selection signal having the first state value and the output signal having the second energy value outputted by the conversion unit 24 for the electronic device Please refer to FIG. 2B, which is a circuit diagram showing a specific embodiment of the memory selection device of the present invention. The following is a detailed circuit structure of the memory selection device of the present invention. Component elements The connection relationship of the components and the working principle thereof. As shown in FIG. 2B, in the embodiment, the first input pins 2, 21 of the first and second SRAMs 20, 21 are For example, 12 M331733 generally has a (4) cs N, and the first input pins 202 and 212 are, for example, a pin CS provided by the static second: the first input pin 2 The second input pin 2 () 2, 212 is high level effective. The substrate management controller 22 is, for example, a substrate tube-CQntrGller, and the first output pin 220 And a second output pin 222. The /, the second outlet pin 220 and the first, the first _ static rain - spear - 酼 you access the memory 20, ^ brother of an input pin 200, 210 Thunder The second bucket μ m 299 ^ - is electrically connected, and the second output 212 of the second output connector, the second system 212, and the second leg 212 of the second static random access memory 21 are electrically connected. In this embodiment, the substrate management controller 22 and the second static random access memory device are connected to the input pin 212 to electrically connect a resistor element. The conversion unit 24 is connected to the second=2 of the substrate management control (4) and the first static random access memory 2. The second input pin 2 is connected sexually. In the present embodiment, the conversion unit 24 includes a NOT Gate 240, a power supply for supplying power to the reverse gate 24, and a capacitor for filtering between the reverse gate 24〇 and the ground. : Performing a bit=conversion process on the selection signal outputted by the second round of the output pin m to generate a selection signal output having the second state value. The signal (4) is effective for the low level. Therefore, the first output pin 22 of the substrate controller 22 outputs the first value of the value = the selection signal, wherein the first state The value is a low level, and the first state value is changed from a low level to a high level by the anti-body 1 240 to form the 13th M331733, the second state value selection signal, so the first static random access memory Plus: In the chat cs, 'the second state value selection signal is high, effective. The working principle of the circuit structure of this embodiment is as follows: when the first input of the first and second static random access memories 2, 21 is connected: 2 〇. The 210 receives the enable signal (low level signal) outputted by the first output pin 22 of the substrate management controller 22, and is enabled, because the first and second static random access memory 2 〇, 21 pin csji is in a low state when the low signal level is active, and # the substrate (four) controller & second output pin 222 output selection signal is high level, that is, the first state is generated a value selection signal (high level signal) to the second input pin 212 of the second static random access memory 21, because the second static memory access pin 21 of the memory access memory 21 is at a high level signal The second static random access memory (2) is selected for use by the electronic device; and the selected signal outputted by the second output pin M2 of the substrate management controller 22 is low. Transmitting, by the signal conversion of the conversion unit (from low level to high level), generating a selection signal (high level signal) having a second state value to the second input of the first static random access memory '20 Pin 2〇2, because the first When the pin CS of the static random access memory is in the high level signal, the first static random access memory 20 is selected for use by the electronic device. "Before, compared with the prior art, the memory of the present invention is selected by the first output pin of the substrate management controller and the first and second static random access memory. The input pin is electrically connected, and the 14 M331733 electrically connects the second round output pin of the substrate control with the second input pin of the second memory and the first static random 2 via a conversion unit The second input pin of the memory is electrically connected, and the first input pin of the first and first sorrow ik access memory receives the substrate tube, and the enable signal is turned on. In the enabled state, the first static branch access is selected by the substrate: the selection signal having the first state value and the selection signal having the second state value outputted by the conversion single T output. The second or second static random access memory is used for the electronic device. Compared with the prior art, the memory selection device of the present invention only uses the input pin provided by the memory as the memory. Judging 'without having to make the substrate as in the prior art The first and second output pins of the controller pass through the plurality of conversion units and are electrically connected to the input pins of the first and second static memory access memory. Therefore, the memory of the creation is selected. The memory selection function can also achieve the purpose of simplifying the circuit structure, saving electronic parts and manufacturing cost, and correspondingly designing the space. The above embodiment only exemplifies the principle and function of the creation, instead of It is used to limit the creation of this work. Anyone who is familiar with the art can modify and change the above embodiments without departing from the spirit and scope of Z. Therefore, the scope of protection of this creation should be as described later. In the specific range listed in the month of 0 [Simple Description of the Drawings] Figure 1 is a schematic diagram of a circuit for selecting two memories; 15 M331733 / 2A is the memory selection device of the creation The basic architecture shows: intent; and the 2B diagram is used to illustrate the circuit example of the memory selection device that implements the creation. ^ [Main component symbol description] 10 First SRAM 11 Second SRA M 12 BMC 120 first output pin 122 second output pin 14 first conversion unit 16 second conversion unit 18 third conversion unit 20 first memory 21 second memory 200, 210 first input pin 202, 212 second input pin 220 output pin 222 second output pin 22 substrate management controller 24 conversion unit 240 reverse gate 242 power supply 244 capacitor 26 resistance element 16