TWM327032U - On-glass single chip liquid crystal display device - Google Patents

Abstract

There is provided an LCD capable of reducing a whole size and minimizing a defective proportion thereof. An LCD panel of the LCD includes a gate driving circuit that drives gate lines formed extended along a row direction and a line block selecting circuit that drives data lines extended along a column direction. On the LCD panel, an integrated driving chip having a controller, a memory, a level shifter, a source driver, a common voltage generator and a DC/DC converter is mounted. The integrated driving chip not only drives the gate driving circuit and line block selecting circuit, but also controls the operation of the LCD panel to display an image. Accordingly, it is able to decrease a defective proportion of the LCD and reducing the whole size thereof.

Description

M327032 VIII. New Description: [New Technology Field 3 New Fields This new type relates to liquid crystal displays (LCDs), and more particularly to LCDs that can reduce the overall size of 5 and minimize its defect rate. [Prior Art 3 New Background

Recently, information processing devices have rapidly evolved into a variety of different structures and functions, as well as faster information processing speeds. The information processed in the information processing device 10 has the format of an electrical signal. In order to visually recognize the information processed in the information processing apparatus, a display apparatus must be provided as an interface. Compared with the conventional cathode ray tube (CRT), the LCD has, for example, a light weight, a small size, a high resolution, a low power consumption, and an easy adjustment to the environment, and the LCD can display full color. These advantages make it possible for LCDs to replace CRTs and are likely to become the next generation of displays. Typically, an LCD will use two substrates, each having an electrode and a TFT-LCD that can be switched to the power of the electrode. The TFT-LCD is classified into a non-silicone TFT LCD (a_Si TFT-LCD) and a polysilicon TFT LCD (poly-Si 20 TFT-LCD). Polycrystalline lithography TFT-LCD has the advantages of low power consumption and low price compared to amorphous 矽 TFT-LCD, but it also has the disadvantage of complicated process. Therefore, the polysilicon TFT-LCD is mainly used for a small-sized display device. For example, a mobile phone, etc. Amorphous germanium TFT-LCDs are used in display devices with large-size screens, such as notebook computers, LCD monitors, high-definition M327032 (HD) TV receivers, and more. Fig. 1 is a simplified schematic view showing an LCD panel of an amorphous 矽 TFT-LCD of the prior art. Referring to FIG. 1, an amorphous 矽TFT-LCD 50 includes an LCD 5 panel 1 具有 having an array of pixels, and driving printed circuit boards 36 and 42 provides driving signals to the LCD panel 1 〇 The carrier packages (TCP) 32 and 38 electrically connect the 1 LCD panel 10 to the drive printed circuit boards 36 and 42. The drive printed circuit boards 38 and 42 comprise a data printed circuit board 10 36. A plurality of data lines disposed in the LCD panel 10 can be driven; and a gate printed circuit board 42 can drive a plurality of gate lines disposed in the LCD panel 10. The data printed circuit board 36 is connected to the terminals of the data lines via the data side TCP 32, and the gate printed circuit board 42 is connected to the terminals of the gate lines through the gate side TCP 38. 15 The amorphous X-ray TFT-LCD has a data driving chip 34 disposed on the data side TCP 32 in a film-on-film (COF) manner, and a gate driving wafer 40 is also disposed on the gate side in a COF manner. On the TCB 38. Recently, many efforts have been made to reduce the number of combined processes by simultaneously forming the data with a pixel array on one of the 20 amorphous glass substrates of a non-crystalline germanium TFT-LCD and a polycrystalline germanium TFT-LCD. Drive circuit and gate drive circuit. Figure 2 is a simplified schematic diagram showing a conventional amorphous 矽 TFT-LCD panel having data and gate drive wafers thereon. Referring to Fig. 2, an amorphous 矽 TFT-LCD 90 includes a glass. The M327032 glass substrate 60 has a display area 6A, in which an array of pixels is disposed, and a peripheral region 60b is adjacent to the display region 6A. A plurality of data driving chips 61, gate driving chips 62, and the like are provided on the peripheral region 60b. Each of the output terminals of the data driving chips 61 is connected to a corresponding data line, and the output terminals of the respective driving electrodes 62 are connected to a corresponding gate line. The output terminals of the data and gate drive wafers 61 and 62 are connected to an integrated printed circuit board (not shown) via a flexible printed circuit board 70.

The flexible printed circuit board 70 includes a control drive chip 71 and a common voltage generator 72. The control driving chip 71 supplies a certain time signal 10 and an image data signal to the data driving chip 61 and the gate driving chip 62, respectively. The common voltage generator 72 generates a common voltage. The data and the structure in which the gate drive wafers 61 and 62 are disposed on the glass substrate 6 are reduced in cost due to the integration of the driver circuit, and the power consumption is minimized. I5 But when there are many drive chips on the glass, there are many problems as follows. When the majority of the drive wafer is placed on the glass substrate, the rate of failure will increase proportional to the number of wafers. That is, the yield of the LCD will be lowered because even if only one of the majority of the driver chips is defective, the entire LCD module cannot be used. However, when the defect rate increases, the manufacturing time of the LCD becomes longer, so the productivity thereof becomes lower. Second, from the standpoint of the mounting structure, the overall size of the LCD will increase as a result of mounting multiple wafers on the glass substrate. In other words, since the number of wafers is increased, the number of texture patterns M327032 to be provided on the glass substrate is also increased. In order to obtain a space for fabricating the lines, the size of the LCD panel must also be increased. As a result, high resolution may not be achieved in an LCD that requires a limited size. Thirdly, since a plurality of wafers are disposed adjacent to one side of the LCD panel, the structure of the LCD panel may become unbalanced, and the overall size of the LCD may become larger. Fourth, the image display characteristics of the LCD panel are such that the uniformity of the image cannot be obtained due to the fixed resistance between the plurality of wafers and the glass substrate. New Contents of L] 10 New Outline The reason is that 'the first purpose of this new type' is to provide an LCD that can reduce manufacturing time and overall size. A second object of the present invention is to provide an LCD having an integrated driver wafer with channel terminals that are compatible with the data lines. A third object of the present invention is to provide an LCD that can be used for a display device having a high vertical resolution. A fourth object of the present invention is to provide an LCD which can increase its effective display area. In order to achieve the first object, an LCD device includes a first 20 substrate having a display area and a peripheral area adjacent to the display area, a second substrate disposed opposite the first substrate, and a liquid crystal medium Provided between the first and second substrates. The first substrate includes a plurality of switching devices, pixel electrodes, gate lines, data lines, a gate driving circuit, and an integrated driving chip. The switching M327032 devices are arranged in a matrix in the display area. The pixel electrodes are also arranged in a matrix, and the pixel electrodes are connected to one of the switching devices. The 4th gate lines are arranged in a horizontal direction, and each of the lines is connected in common to the control electrodes of the switching devices arranged in the lateral direction. The data lines are arranged in a straight line, and the data lines are connected in common to the second current electrodes of the switching devices arranged in the vertical direction. The gate drive circuit is disposed in a first zone of one of the peripheral zones, i.e., where the first extension of the gates extends, and the gates are continuously scanned. The integrated driving chip is disposed in a second area of the peripheral area, that is, where the first end of the data line extends, and responds to an outer 10 pieces of image data and an external control signal to provide a Driving a control signal to the gate drive circuit and providing an analog signal to the data lines. In order to achieve the second object, an LCD device includes a first substrate having a display region and a peripheral region adjacent to the display region, a second substrate disposed opposite the first substrate, and a liquid crystal device Between the first and second base 15 plates. «Haidi substrate contains a large number of switching devices, pixel electrodes, gate lines, lean lines, gate drive circuits, one-line selection lines, and an integrated driver chip. The switching devices are arranged in a matrix in the display area. The image electrodes are also arranged in a matrix in the display area, and the pixel electrodes are connected to the first current electrode of each of the switching devices. The gate lines are arranged in a lateral direction, and the gate lines are commonly connected to the control electrodes of the plurality of laterally arranged switching devices. The data lines are arranged in a straight line, and the data lines are connected in common to the second current electrodes of the plurality of vertically arranged switching devices. The gate drive circuit is disposed in a first region of the peripheral region, i.e., where the first M327032 end of the gate line extends, and the gate lines are continuously scanned. The line selection circuit is disposed in a second area of the peripheral area, that is, where the first end of the data line extends, and the analog driving signal of the block unit is received, and one of the data lines is selected. And switching the analog drive signal of one block unit to the data line of the selected line area, and the like. The integrated driving chip is disposed in the second region, and responds to an external image data and an external control signal to provide a driving control k gate driving circuit, and provides a line selection signal and an analog signal of a block unit. Select the circuit for the line area. The 4 whole 5 driving chip system comprises a face that can refer to the external image material and external control signals, a memory can store external image data, and a source 2 driver n can respond to read from the memory block by block. The image data of the block unit is output to output analog driving signals of the block units, and an electric translating device can shift the levels of the driving control signals and the line selection signals, and a controller can respond The external control signal input to the face, and 15 external image data are stored in the memory, and the second control area of the driving control signal is generated, and the signal is supplied to the electric translating device, and the memory is driven by the memory. The image data is read out in blocks, and the read image data is supplied to the source driver one by one. Α • The integrated driver chip further includes a common power generator to generate an ugly 20 voltage 々, and provide the common voltage to a common electrode line provided on the -LCD panel; and a DC/DC converter Receiving an external voltage, raising or lowering the external μ, and supplying the boosted or reduced voltage to the (four) electrical translator, the source driver, and the common power to generate a cry. The control signals include a master clock signal, a horizontal sync signal M327032, a vertical dream signal, a data operation signal, and a mode selection signal, and the control funnel returns a mode selection signal to generate the line. Zone selection signal. 5 When the block has a size equivalent to % horizontal resolution, the first line area will contain odd data lines, etc., and a second line area will contain even data lines. The line selection circuit includes a plurality of first selection transistors, second selection transistors, and the like. The first current electrode of the first selection transistor is connected to a corresponding first output terminal of the first output terminal of the analog drive signal outputting the integrated drive chip, and the second current electrodes are connected And corresponding to the odd data lines; and each of the control electrodes is connected to a second output terminal corresponding to one of the second output terminals outputting the first line region selection signals. Each of the first current electrodes is connected to the corresponding first output terminal 15 and each of the first current electrodes is connected to a corresponding even data line, and the = electrode is connected to the output second line selection signal. A third output terminal corresponding to one of the outputs. The package contains the number of (3η·2) cap lines, the number of the second line area - the knot of the data line, and the third line area contains the (10) of 20 ^ = 7 the block has a considerable level The size of the resolution is 自然 η is a natural number. Each of the selected transistors, etc. The first selection transistor drives a signal from the first output terminal corresponding to one of the sub-portions, each of the 11 M327032 second current The electrode system is connected to a corresponding (3n_2)th data line, and each of the control electrodes is connected to a second output terminal corresponding to one of the first line selection signals. The current is returned to the corresponding first-output terminal, and each of the second current electrodes is connected to a pair of 5th (3n+1)th data and lines, and each control electrode is connected to the output second line region. a corresponding third output terminal of the signal. Each of the third current electrodes is connected to a corresponding first output terminal, and the second current electrode is connected to the corresponding (3_f feed line). And each control electrode is connected to a corresponding fourth output terminal that outputs the third line region selection signal For the third purpose, an LCD device includes a first substrate having a display area and a peripheral area adjacent to the display area, the second substrate is disposed opposite the first substrate, and the liquid crystal is Between the first and the first plate. 15 20 The T includes a plurality of switching devices, a pixel electrode, a gate line, a pendulum (four) gate drive circuit, a second gate drive circuit, a line region, and an integrated drive. The switching device is in the matrix and in the display area. The pixel electrodes are also arranged in a matrix in the display area, and each image is connected to the switching device - the first electric H The gate lines are arranged in a horizontal direction and each gate line is connected to the control electrodes of the switching devices. The data lines are arranged in a straight line: and each of the lines is connected In the switching device of the feed straight ship, the electric W electrode H brake drive circuit is driven to extend the gate line of the odd 12 M327032 number in the n of the peripheral zone. The second gate driving circuit is disposed in a second region of the peripheral region, that is, the second end of the gate lines Wherein, an extension of the inter-line can be driven, and connected to the first gate driving circuit via the 4-gate line, and the gate lines are continuously scanned. The line selection circuit is disposed in one of the peripheral areas. In the third and fifth zones, that is, where the first end of the data line extends, the analog drive signal of the block unit can be received, one of the data lines is selected, and the analog drive signal of one block unit is switched. Into the data line of the selected line area, the integrated driving chip is disposed in the third area, and can provide driving control signals to the first and second gate (1) driving circuits in response to an external image data and an external control signal. And providing - a line selection signal and an analog signal of a block unit to the line selection circuit. To achieve the fourth object, the device is provided with a first basic unit having a display area And a peripheral area adjacent to the display area, a second substrate is disposed opposite the first substrate, and a liquid crystal is disposed between the first and second base 15 plates. The first substrate includes a plurality of switching devices, pixel electrodes, gate lines, t-feed lines, a line selection circuit, and an integrated driver chip. The switching devices are arranged in a matrix in the display area. The pixel electrodes are also arranged in a matrix in the display area. Further, each of the pixel electrodes is connected to the -th current electrode of each of the switching devices 20. The gate lines are arranged in a lateral direction, and each of the lines is connected in common to the common electrode of the horizontally arranged switching devices. The data lines are arranged in a straight line, and each data line is connected to the second current electrode of the switching device arranged in series. The line selection circuit is disposed in a peripheral area where the first end of the data line extends, and the analog drive signal of the block 13 M327032 block unit is received, and one of the data lines is selected, and one line is selected. The analog drive signal of the block unit is switched to the data line of the selected line area, and the like. The integrated driving chip is disposed in the peripheral area where the line selection circuit is provided, and can receive external image data and external control signals, and provides a first gate driving signal to an odd number of brake materials, and provides a second gate The drive signal is supplied to an even number of gate lines or the like, and the line selection signal and the analog signal of the block unit are supplied to the line selection circuit. 10 15 20 The integrated driver chip includes a face, a memory for storing external image data, a source driver, a motor translator, a first-idle driver, a second gate driver, and a controller. This interface can be used for two. The shirt is like a poor material and external control signals. The source driver responds to the image data of the patch unit by block-by-block from the memory, and outputs the analog signal of the block 70. The electrical translation _the _ drive controls the H-second drive control signal and the level of the line selection semaphore. The first gate driver responds to the _th drive control signal to supply the _th drive signal to an odd gate line or the like. The second actuator transmits the second idle drive signal to the even number of lines and the like in response to the second drive control L number. The controller responds to the external control signal input by the interface to store the external image data in the memory, and generates the first and second driving control signals and the line selection signal, etc., and Provided to the electrical translating device, and the image data is read out block by block from the memory and provided to the source driver. According to the above CD, only the integrated driving wafer for driving the gCD panel is disposed in the peripheral area of the display area, so that the manufacturing time can be reduced, the defective rate can be minimized, and the overall size of the LCD panel can be reduced. 14 M327032 In addition, the line selection circuit disposed in the peripheral area of the display area, and the TFT transistor disposed in the display area are all completed by using only a process, and the pixel data corresponding to one line is utilized. The line selection circuit is driven in a shared time manner, so that the channel terminals of the integrated driver chip can be compatible with the data line. Further, the gate line driving circuit provided on the left and right sides of the peripheral area of the display area, and the TFT transistor provided in the display area are all completed by only one process. The gate drive circuit is formed in a concavo-convex shape, so that the brake drive circuit can be simultaneously disposed on the left and right sides of the peripheral zone. Moreover, the gate line 10 driving circuit can be used for an LCD having a high vertical resolution. Moreover, the integrated driver chip has a gate driver capable of driving the gate lines and a source driver capable of driving the data lines, and is disposed on the LCD panel, thereby increasing an effective display area of the LCD panel. BRIEF DESCRIPTION OF THE DRAWINGS The above and other advantages and advantages of the present invention will be more clearly understood from the detailed description of the preferred embodiments of the preferred embodiments herein. -Simplified schematic diagram of one of the LCD panels of the LCD; 20 Figure 2 is a simplified schematic view of a conventional amorphous TFT-LCD panel with data and gate drive wafers; Figure 3 is a preferred embodiment of the present invention FIG. 4 is a schematic view showing a first embodiment of the TFT substrate in FIG. 3; FIG. 5 is a schematic view showing a second embodiment of the TFT substrate in FIG. 3; 15 M327032 FIG. 6 is a block Figure 1 shows a first embodiment of the integrated driver wafer in Figure 5; Figure 7 is a block diagram showing a second embodiment of the integrated driver wafer; Figure 8 is a circuit diagram showing a first line region The selection circuit selectively divides 5 of the plurality of data lines into two blocks, and FIG. 9 is an output waveform of the first line area selection circuit in FIG. 8; FIG. 10 is a circuit diagram showing a second line area selection circuit. Selectively divide most data lines into three blocks; Figure 11 shows the 10th The output waveform of the second line selection circuit in the figure; 10 Fig. 12 is a circuit diagram showing a third line selection circuit selectively dividing a plurality of data lines into four blocks; Fig. 13 is a picture in Fig. 12. The output waveform of the third line region selection circuit; Fig. 14 is a block diagram of the first shift register of the gate driving circuit in the fifth diagram of the first embodiment of the present invention; 15 Fig. 15 is the 14th diagram Detailed circuit diagram of the first shift register in FIG. 16; FIG. 16 is an output waveform of the first shift register in FIG. 14; FIG. 17 is a diagram in FIG. 5 according to the second embodiment of the present invention Block diagram of a second shift register of one of the gate drive circuits; FIG. 18 is a block diagram of a third shift register of the gate drive 20 circuit in FIG. 5 of the third embodiment of the present invention Figure 19 is a circuit diagram of the third shift register shown in Figure 18; Figure 20 is a perspective view of the structure of one of the FPCs in Figure 3; and Figure 21 is an LCD panel of another embodiment of the present invention. Figure 22 is a fourth 16 M327032 and fifth shift register of the first and second gate drive circuits shown in Figure 21 Figure 23 is an output waveform of the fourth and fifth shift registers in Fig. 22; Fig. 24 is a schematic diagram of the lCd panel according to still another embodiment; 5 and 25 are One of the 24 figures integrates a block diagram of the driver chip. I: Embodiment 3

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will now be described in detail with reference to the drawings. 10 Fig. 3 is an exploded perspective view of one of the LCDs of the present invention. Referring to FIG. 3, an LCD 500 includes an LCD panel assembly, a backlight assembly 200, a frame 300, and a cover 400. The LCD panel assembly 1 includes an LCD panel 110, a flexible printed circuit board (hereinafter referred to as "FPC") 190, and an integrated drive wafer 180. The LCD panel 110 includes a TFT substrate 120 as a lower substrate, a color filter substrate 130 disposed on the TFT substrate 120, and a liquid crystal. The liquid crystal system is injected between the TFT substrate 120 and the color filter substrate 130, and then the injection port is sealed. On the TFT substrate 120, a display cell array circuit, a gate driving circuit, and the integrated driving chip 180 are provided. The TFT substrate 120 is disposed opposite to the color filter 20 substrate 130. The integrated drive wafer 180 is electrically coupled to an external circuit substrate (not shown) via the FPC 190. RGB pixels and a transparent common electrode are provided on the color filter substrate 130. The backlight assembly 200 includes a lamp assembly 220, a light guide plate 240, a series of optical sheets 260, a reflection plate 280, a mold frame 290, and the like. 17 M327032 Fig. 4 is a schematic view showing a first embodiment of the TFT substrate in Fig. 3. Referring to FIG. 4, the TFT substrate 120 is divided into a first region corresponding to the color substrate 130 and a second region not corresponding to the color filter substrate 13A. The first area includes a display area and a peripheral area adjacent to the display area. In the display area, a plurality of data lines DL are arranged to extend in the in-line direction, and a plurality of gate lines GL and the like are arranged to extend in the horizontal direction. A gate driving circuit 140 is connected to the gate lines GL and integrated on the left side of the peripheral area. In the second region of the TFT substrate 120, the integrated drive wafer 10180 is provided to control the operation of the LCD panel 110. The integrated driver chip 18 can receive an external image data signal 181a and an external control signal 181b from an external circuit substrate disposed separately from the LCD panel 110. The integrated driver chip 180 provides a drive control signal GC to the gate drive circuit 14 and provides an analog drive signal (or analog pixel data) to the data lines DL. A first and a second external connection terminal of the 15 integrated driver chip I80 are connected to the FPC 190, and the FPC is electrically connected between the external circuit substrate and the integrated driver chip 180. The external image data signal 18 is input via the first external connection terminal, and the external control signal 18 is input via the second external connection terminal. 20 In each of the plurality of wheel-out terminals of the integrated drive chip I80, the output terminals of the drive control signal GC are outputted to an input terminal of a corresponding drive circuit 140. And each channel terminal (3) is connected to a corresponding one of the lean lines DL. In detail, the terminal for outputting the output control signal sink includes a start signal output terminal, a first clock signal output terminal, 18 M327032 a second clock signal output terminal, a first power voltage terminal, and a first - A power supply voltage terminal. Fig. 5 is a view showing a second embodiment of the TFT substrate in Fig. 3. Referring to Fig. 5, the TFT substrate 120 is divided into a first region corresponding to the color filter substrate 5, and a second region not corresponding to the color filter substrate 130. The first zone includes the display zone and a peripheral zone adjacent to the display zone. In the display area, a plurality of data lines DL are provided extending in the in-line direction, and a plurality of gate lines GL and the like extend in the horizontal direction. A gate driving circuit 14 is integrated on the left side adjacent to the peripheral area of the display area, and the gate driving circuit 14 is connected to the gate lines GL. A line selection unit 150 is integrated at the top of the peripheral area and connected to the data lines DL. In the second region of the TFT substrate 120, an integrated drive wafer 18 is provided for controlling the operation of the LCD panel 110. The integrated driver chip 18A can receive an external image data signal 181a and an external control signal 181b sent from an external circuit substrate disposed separately from the LCD panel 11A. The integrated driving chip 180 provides a driving control signal g c and an analog driving signal to the gate driving circuit 140 and the data line DL, respectively. One of the first and second external connection terminals of the integrated driver chip 18 is connected to the FPC 190, and the FPC is electrically connected between the external circuit substrate and the integrated driver chip 18A. The external image 20 image signal 181a is input via the first external connection terminal, and the external control signal 181b is input via the second external connection terminal. Among the output terminals of the integrated drive wafer 180, an output terminal for outputting the drive control signal GC is connected to an input terminal of a corresponding gate drive circuit 140. The output terminal of the line selection signal TG is connected to the control terminal of the gate drive circuit 140 of 19 M327032. Each channel terminal CH is connected to an input terminal corresponding to one of the line area selection circuits 150. The output terminals of the line selection circuit 150 are connected to a corresponding data line dl. The number of the data lines DL may be N 5 times more than the channel terminal CH of the integrated drive wafer 180, which is an integer. Fig. 6 is a block diagram showing the first embodiment of the integrated drive wafer in Figs. 4 and 5. Referring to FIG. 6, the integrated driving chip 180 includes a dielectric portion 181, a memory 183, a source driver 185, a transponder 184, a common voltage generator 186, and a controller 182. . The interface portion 181 can receive the external image data signal 181a and the external control signal 181b as an interface between the controller 182 and an external device. The interface 181 is compatible with a CPU interface, a video board interface, and a media q interface. The controller 182 receives the external image data signal 181a and the external control signal 181b from the dielectric surface 181, and stores the external image data signal 181a in the memory 183. The external control signal 181b includes horizontal and vertical sync signals. Main clock signal, data operation signal, and mode selection nickname. The controller 182 will respond to the mode select signal to generate the line select signal TG. In addition, the controller 182 provides a drive control signal GC and a line select signal TG to the electrical translator 184. The drive control signal includes a start signal st, a first clock signal ck, a second clock signal CKB, a first power supply voltage VSS, and a second power supply voltage VDD. 20 M327032 In addition, the controller 182 provides digital image data to the source driver 185. That is, the controller 182 reads out the external video material signal 181a-block-block stored in the memory 183 and supplies it to the source driver 185. 5 The memory 183 temporarily stores the external image data signal supplied by the controller 182. The memory 183 stores the external image data signals frame by frame or line by line. If a row of memory is used as the memory 183, and the external image data signal is supplied to the control H 182 ' via 36 channels, the memory 183 has a storage capacity equivalent to two rows of 10, that is, 36. 〇/3 fly/2=12960 bits. The beta source driver 185 receives the digital image data from the memory 183 on a block-by-block basis and outputs the analog drive signals block by block. The channel terminals CH of the source driver 185 are connected to the corresponding data line DL. The pan shifting 184 changes the voltage level of the drive control signal GC and the line select signal TG from the controller 182 and outputs it. The axis control of the electric translation (4) GC includes a first-clock signal cK, which is rotated by the start-up signal, and the first clock, h#uCKB, which is rotated by the electric translation. The first power supply voltage vss, 2〇, and a second power supply voltage VDD that is electrically shifted. "Hui common voltage generator 186 will apply the common voltage vcom to the common electrode of the liquid helium layer in parallel to maintain the voltage of the liquid crystal layer. Fig. 7 is the view of the fourth and fifth figures A block diagram of a second embodiment of a driver chip is integrated. 21 M327032 Referring to FIG. 7, the integrated driver chip 18 includes the interface portion 181, the memory device 183, the source driver 185, and the electrical translation device 184. a common voltage generator 186, a DC/DC converter 187, and the controller 182, etc. The DC/DC converter 187 accepts one of the first DC power source voltages 187a' supplied by the outside and the second DC. The power supply voltage (AVDD, VSS, VDD, VCC, etc.) is supplied to the corresponding circuit portion of the integrated driver chip. Typically, the DC/DC converter 187 receives a first DC power supply voltage 187a of 7 to 12V, and The first DC power voltage 187a is boosted or lowered to a second DC power voltage AVDD, VSS, VDD, VCC, etc. of 5 V. 10 The second DC power voltage AVDD boosted or lowered by the DC/DC converter 187 , VSS, VDD, VCC, etc., will be supplied to the source driver 185 and the electric translator 184, respectively. a common voltage generator 186, a controller 182, etc. In other words, the DC/DC converter 187 provides the analog supply voltage AVDD to the source driver 185 and the common voltage generator 15 186, and provides an image driving power supply voltage. VSS and VDD give the electrical translation 184' and the digital driving power supply voltage VCC is supplied to the controller 182. Hereinafter, the line selection circuit 150 will be described in detail with reference to the drawings, 'the circuit 150 is connected to the integration. The channel terminal CH of the driving chip 180 is interposed between the data lines DL, and the image data can be selectively supplied from the wafer 180 to the data lines DL. FIG. 8 is a circuit diagram showing the first line area. The selection circuit selectively divides the data lines into two blocks; and the ninth picture is an analog waveform of the first line area selection circuit. Referring to FIG. 8, the first line selection circuit 151 is set Abutting 22 M327032 on top of the peripheral region of the TFT substrate 120, the analog drive signal 180 can be periodically applied to the data lines DL1 to DL2m in a block by the integrated driving chip 180. In other words, The 2m assets The first line area selection circuit 1515 of the feed line is divided into first and second blocks BL1 and BL2, each having m data lines. The first block BL1 includes m odd data lines DL1 to DL2m- l, the second block BL2 includes m even data lines DL2 to DL2m. The channel terminals CHI, CH2 ".CHm of the integrated driving chip 180 are commonly connected to the two data lines. For example, the first pass terminal CH1 of the wafer 18 is commonly connected to the first and second data lines DL1 and DL2 and the like. The first block BL1 of the first line area selection circuit 151 connected to the channel terminal CH and the odd data lines DL1 to DL2m-1 includes a first selection switch body SW1' which is driven by the integrated drive wafer 1. The first line area selection signal 15 (TG1) is driven. Similarly, the second block BL2 connected to the channel terminal ch and the even data lines DL2 to DL2m includes a second selection transistor SW2 driven by the second line selection signal (TG2) of the wafer 180. The TG1 and TG2 signals will have a high level. When a high level TG1 signal is output, the first selection transistor 20 SW1 is driven by the TG1 signal, and an analog drive signal from the channel terminal CH is supplied to the odd data lines DL1 to DL2m-1. . When a high level TG2 signal is output, the second selection transistor SW2 is driven by the TG2 signal' and the analog drive signal from the channel terminal CH is supplied to the even data lines DL2 to DL2m and the like. 23 M327032 As shown in Figure 9, when there are a majority of gate lines (31^1 to (31^ are continuously driven for the day ^' during the operation cycle of the gate lines GL1 to GLn, the tgi and TG2 # It will have a level of turn in turn. That is, the TG1 signal will remain high for half of the operating period of the gate lines GL1 to GLn, and the TG2 letter 5 will remain high for the other half of the period. Therefore, when the high level TG1 is output, the first selection transistor SW1 is driven, and the analog drive signal is supplied to the data line DL2m-1 of the first block BL1. Similarly, when high When the level TG2 is output, the second selection transistor 5; ^¥2 is driven, and the analog drive signal is supplied to the data line DL2m of the second block BL2. 10 Similarly, at the second gate line During the operation cycle of GL2, the high level TG1 signal is output, the first selection transistor SW1 is driven, and the analog drive signal is supplied to the data line DL2m-1 of the first block BL1. When the high level TG2 signal is output, the second selection transistor SW2 is driven, and the analog drive signal is supplied to the second block BL. 2 is in the data line DL2m 15. Fig. 10 is a circuit diagram showing that the first line area selecting circuit selectively divides the data lines into three blocks; and FIG. 11 shows the tenth figure in FIG. The analog waveform of the second line selection circuit. Referring to FIG. 1 , the second line selection circuit 152 is disposed at the top of the peripheral area adjacent to the 20 TFT substrate 120, and the analog drive signal is periodically The integrated driving chip 180 is supplied to the data lines DL1 to DL3m one by one. The second line selection circuit 152 has 3m data lines and is divided into first, second, and The three blocks BL1, BL2, BL3, etc., 24 M327032 each have m data lines. The first block BU contains ^^ data lines DL3m-2, for example, -, four, seven, etc. Block 2 of the second block also contains m data lines DLSm-i, such as the second, fifth, eighth, etc. The third block bl3 also contains m data lines DL3m, such as the third, sixth, ninth, etc. Each of the channel terminals CH of the driving chip 180 is commonly connected to one of the three-region data lines. That is, the first channel of the wafer 180 The terminal CH1 is commonly connected to the first, second, and third data lines DL1, DL2 & DL3, etc. The first block BL1 of the second line selection circuit 152 includes a first selection transistor SW1 connected to The channel terminal CH and the first, fourth, seventh, and ten data lines DL3m-2 are driven by the first line region selection # (TG1) from the integrated driver chip 18A. Similarly, the second The block BL2 includes a second selection transistor SW2 connected to the channel terminal cH and the second, fifth, eighth, etc. data line DL3m-1, and the second line region selection signal (TG2) of the wafer 18〇 ) driven. Moreover, the third block BL3 also includes a third 15 selection transistor SW3 connected to the channel terminal and the third, sixth, ninth, etc. data line DL3m, and the third line of the wafer 18 can be borrowed. The zone selection signal (TG3) is driven. These TGI, TG2, and TG3 signals will have _ high level in turn. In other words, when the high level TG1 signal is output, the first selection power 20 crystal SW1 is driven by the TG1 signal, and the analog drive signal from the channel terminal ch is supplied to the first, fourth, seventh... Data line DL3m. When the high level TG2 signal is output, the second selection transistor SW2 is driven by the TG2 signal, and the analog drive signal from the channel terminal CH is supplied to the second, fifth, eighth, etc. data line DL3m-1. When the TG3 signal is output at a high level, the 25 M327032 third selection transistor SW3 is driven by the TG3 signal, and the analog drive signal from the channel terminal CH is supplied to the third, sixth, ninth, etc. data line DL3m. As shown in Fig. 11, when a plurality of gate lines GL1 to GLn are continuously driven by the gate driving circuit 5, 140, in the operation cycle of each of the gate lines GL1 to GLn, the TG TG2, TG3 signals, etc. Take turns to have a high level. That is, the TGI, TG2, and TG3 signals will each maintain a high level of one-third of a cycle during the operation periods of the gate lines GL1 to GLn. Therefore, during the operation period of the first gate line GL1, when the high level TG1 10 signal is output, the first selection transistor SW1 is driven, and the analog drive signal is supplied to the first block BL1. Data line DL3m-2 and so on. Similarly, when the high level TG2 signal is output, the second selection transistor Sw2 is driven, and the analog drive signal is supplied to the data line DL3m-1 of the second block BL2 and the like. Further, when the TG3 signal of the high level is output, the third selection transistor SW3 is driven, and the analog drive signal is supplied to the data line DL3m of the third block BL3 and the like. During the operation period of the second gate line GL2, when the TG1 signal of the high level is output, the first selection transistor SW1 is driven, so the analog drive signal is supplied to the data line DL3m of the first block BL1. -2 and so on. Similarly, when the TG2 signal of the high level is output, the second selection transistor SW2 is driven, so that the analog driving signal is supplied to the data line DL3m-1 of the second block BL2 and the like. When the high level TG3 signal is output, the third selection transistor SW3 is driven, and the analog drive signal is supplied to the data line DL3m of the third block bl3 and the like. 26 M327032 Fig. 12 is a circuit diagram showing that the third line selection circuit selectively divides the data lines into four blocks, and Fig. 13 is an analog waveform of the third line area selection circuit in Fig. 12. . Referring to FIG. 12, the third line selection circuit 153 is disposed on the top of the peripheral region adjacent to the 5 TFT substrate 120, and the analog drive signal can be periodically integrated by the edge integrated drive wafer 180. The data lines dl 1 to DL4m are the same, and the second line selection circuit 153 has 4m data lines DL1 to DL4m, and is divided into first, second, third and fourth blocks bli, BL2, 10 BL3. , BL4, etc., each having m data lines. The first block BL1 includes m data lines DL4m-3, such as first, fifth, nine, etc. The second block bl2 also includes m data lines DL4m-2, such as second, sixth, ten, etc. The third block BL3 also includes m data lines DL4m-1, such as third, seventh, ----, and the like. The fourth block BL4 also includes m data lines D4m, such as fourth, eighth, fifteen, and the like. The channel terminals CH and the like of the integrated driving chip 180 are commonly connected to one of the corresponding four-region data lines. That is, the first channel terminal CH1 of the wafer 180 is commonly connected to the first, second, third, and fourth data lines DL1, DL2, DL3, DL4, and the like. The first block BL1 of the third line selection circuit 153 includes a first 20-selective transistor SW1 connected to the channel terminal CH and the first, fifth, ninth, etc. data lines DL4m-3, and will be integrated. The first line select signal (TG1) of the drive wafer 180 is driven. Similarly, the second block BL2 includes a second selection transistor SW2 connected to the channel terminal CH and the second, sixth, ten, etc. data lines DL4m-2, and can be selected by the second line region of the wafer 180. Signal 27 is driven by M327032 (TG2). The third block BL3 includes a third selection transistor SW3 connected to the channel terminal CH and the third, seventh, eleven, etc. data lines DL4m-1, and can be selected by the third line region of the wafer 180 ( Driven by TG3). The fourth block BL4 includes a fourth selection transistor SW4 connected to the 5-channel terminal CH and the fourth, eighth, twelve, etc. data lines DL4m, and can be selected by the fourth line region of the wafer 180 ( Driven by TG4). The TG1, TG2, TG3, and TG4 signals will alternately have a high level. In other words, when the high level TG1 signal is output, the first selection transistor SW1 is driven by the TG1 signal, so the analog 10 drive signal from the channel terminal CH is supplied to the first, fifth, nine, etc. Data line DL4m-3. When the high level TG2 signal is output, the second selection transistor SW2 is driven by the TG2 signal, and the analog drive signal from the channel terminal CH is supplied to the second, sixth, ten, etc. data lines DL4m- 2. When the high level TG3 signal is output, the third selection transistor SW3 is driven by the TG3 signal, and the analog drive signal from the 15-channel terminal CH is supplied to the third, seventh, eleven, etc. data lines DL4m. -l. When the high level TG4 signal is output, the fourth selection transistor SW4 is driven by the TG4 signal, and the analog drive signal from the channel terminal ch is supplied to the fourth, eighth, twelve, ..., etc. data lines DL4m. As shown in FIG. 13, when the gate lines GL1 to GLn are continuously driven by the gate drive circuit 140, the operation periods of the TGI, TG2, TG3, and TG4 signals at the gate lines GL1 to GLn are as follows. Medium will have this high level in turn. That is, the TGI, TG2, TG3, TG4 signals will remain at the high level during the quarter cycle of the operation periods of the gate lines GL1 to GLn. Therefore, during the operation period of the first gate line GL1, when the high level τσι 28 M327032 signal is output, the first selection transistor SW1 is driven, and the analog drive signal is supplied to the first block BL1. The data line DL4m-3. When the high level TG2 signal is output, the second selection transistor SW2 is driven, and the analog drive signal is supplied to the data line DL4m-2 of the second block BL2. Further, when the high level TG3 signal is output, the third selection transistor SW3 is driven, and the analog drive signal is supplied to the data line DL4m-1 of the third block BL3. When the high level TG4 signal is output, the fourth selection transistor SW4 is driven, and the analog drive signal is supplied to the data line DL4m of the fourth block BL4. 10 During the operation period of the second gate line GL2, when the high level TG1 signal is output, the first selection transistor SW1 is driven, and the analog drive signal is supplied to the data line of the first block BL1. DL4m-3. When the high level TG2 signal is output, the second selection transistor SW2 is driven, and the analog drive signal is supplied to the data line DL4m-2 of the second block BL2. Further, when the TG3 signal of the high level is output, the third selection transistor SW3 is driven' and the analog drive signal is supplied to the data line DL4m-1 of the third block BL3. When the high level TG4 signal is output, the fourth selection transistor S W 4 is driven, and the analog drive signal is supplied to the data line DL4m of the fourth block B L 4 . 20 As shown in FIGS. 8 to 13, although the number of the channel terminals CH of the integrated driving wafer 180 is fixed to m, it may also increase the number of data lines commonly connected to the channel terminals, for example, 2, 3 , 4, etc., to provide the analog drive signal to the greater number of data lines. Therefore, the degree of resolution of the L c D 5 〇 将 will be variably formed. The number of these data lines is determined by the charging time of the analog drive 29 M327032. However, when a main time is divided into 3, 4, 5, ... in order to increase the resolution of the LCD 500, the charging time is reduced. Therefore, the resolution of the LCD 500 is preferably increased in consideration of the charging time of the analog driving signal. The following description of the gate driving circuit 140 disposed adjacent to the left side of the peripheral portion of the LCD panel will be described in detail with reference to the drawings. Figure 14 is a block diagram showing a first shift register of one of the gate drive circuits shown in Figure 5 according to the first embodiment of the present invention; and Figure 15 is a first shift of the first shift in Figure 14 Detailed circuit diagrams of the various stages of the memory; and Figure 16 shows the analog output waveforms of the stages in Figure 1510. Referring to Fig. 14, the gate driving circuit 140 includes a first shift register 141 which includes a plurality of cascaded stages SRC1 to SRCn and the like. In other words, the output terminal OUT of the respective stages is connected to the input terminal of the next stage. The first shift register 141 includes n stages SRC1 15 to SRCn and the like corresponding to the gate lines GL1sGLn and the like, and further includes a dummy level SRCn+1. Each stage has an input terminal IN, an output terminal 〇υτ, a control terminal cT, and a clock signal input terminal.

The sub-CK ’ first power supply voltage terminal VSS, the second power supply voltage terminal VDD, and the like. A first stage input terminal IN receives a start signal St. The start 20 signal ST is a pulse signal synchronized with the vertical synchronizing signal VSYN of the controller 182 in Fig. 6. The output terminals OUT1 to 〇UTn of the respective stages are connected to the corresponding gate lines of the gate lines GL1 to GLn. The odd-numbered stages SRC1 and SRC3 receive the first clock signal CK, and the even-numbered stages SRC2 and SRC4 receive the second 30 M327032 clock signal CKB. The first clock signal CK and the second clock signal CKB have opposite phases. The output signals OUT2, 〇UT3, 〇UT4, etc. of the next stage SRC2, SRC3, and SRC4 are input to the control terminals 5 sub-CTs of the SRCs SRC2 and SRC3 of the respective stages as control signals. In other words, the control signal input to the control terminal is used to reduce the output signal of the previous stage to a low level. Therefore, since the output signals of the respective stages are continuously generated and have a high-state operation period, the gate lines corresponding to the operation periods of the respective output signals will be selected. 10, the first stage of the first shift register 141 includes a lifting portion 142, a lowering portion 144, a lifting driving portion 146, and a lowering driving portion 148. The lifting portion 142 includes a first portion. An NMOS transistor NT1 has a drain connected to a clock signal input terminal, a gate connected to a third node 15 N3 ′ and a source connected to an output terminal OUT. The lowering portion 144 includes a second NMOS transistor NT2, the drain of which is connected to an output terminal OUT, the gate of which is connected to a fourth node N4, and the source is connected to a first power supply voltage VSS. The boost drive unit 146 includes a capacitor c, and NMOS transistors 20 NT3 to NT5 and the like. The capacitor C is connected between the third node N3 and the output terminal OUT. The second electrode of the NMOS transistor NT3 is connected to the second power supply voltage ADD'. The gate of the NT3 is connected to the input terminal in, and the source of the NT3 is connected to the third node N3. The drain of the fourth NMOS transistor NT4 is connected to the second node N3. The gate of the NT4 is connected to the control terminal 31 M327032 CT, and the source of the NT4 is connected to the first power supply voltage VSS. The drain of the fifth NMOS transistor NT5 is connected to the third node N3, and the gate of the NT5 is connected to the fourth node N4. The source of the NT5 is connected to the first power supply voltage VSS. The third NMOS transistor NT3 is twice as large as the fifth NMOS transistor NT5. The channel width of the NMOS transistor NT3 is made twice larger than the width of the NMOS transistor NT5. The lowering driving unit 148 includes sixth and seventh NMOS transistors NT6 and NT7. The drain and gate of the sixth NMOS transistor NT6 are commonly connected to the 10 second power supply voltage VDD, and the source of the NT6 is connected to the fourth node N4. The drain of the seventh NMOS transistor NT7 is connected to the fourth node N4, and the gate of the NMOS 7 is connected to the third node N3, and the source of the NMOS transistor 7 is connected by the size of the sixth NMOS transistor NT6. At the first power supply voltage VSS. This # is 16 times larger than the seventh NMOS transistor NT7. As shown in FIG. 16, when there is a first and second clock signal CK and CKB, and the -start signal ST is supplied to the shift register i4i, the first stage SRC1 responds to the rising edge of the enable signal. will

_ to 〇 等, etc., will be continuously generated via the wheel terminals OUT of the respective stages. 32 M327032 苐17 is a block diagram of a second shift register of one of the gate drive circuits in FIG. 5 in accordance with the second embodiment of the present invention. ° 参阅 17 17 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图The OUT system is connected to the input terminal in of the next stage. The second shift register 149 includes n stages SRC1 to SRCn and the like corresponding to the respective gate lines GL1 to GLn, and further includes a dummy level SRCn+Ι. The stages are successively operated for one frame period, and the n gate lines of GL1 to GLn are continuously scanned. 10 The virtual pole SRCn+Ι provides a control signal to the control of the third stage SRCn^" And operate as a final stage. However, there is no next stage after the virtual level, so the virtual stage SRCn+Ι will operate in an unstable state, because the control terminal CT of the virtual stage SRCn+Ι In order to prevent the virtual stage SRCn+Ι from operating in an unstable state, the control terminal CT of the virtual pole 15 SRCn+Ι is connected to the start signal input terminal to receive the start signal ST, and The ST signal is supplied to the first stage srci. That is, the imaginary stage SRCn+Ι receives the start signal ST via its control terminal CT. As a control signal, in operation, when a high-level start signal is supplied to the start-up # of the first-stage SRC1 2〇 input, the local level is activated when the next frame is completed after completing one frame. "5 tigers will be supplied to the control terminal ct of the virtual stage SRCn+1 as a control signal. That is, by connecting the control terminal CT of the dummy stage SRCn+1 to the input terminal IN of the first stage SRC1, The imaginary stage SRCn+Ι can be prevented from operating in an unstable state. Similarly, as shown in FIG. 18, the control terminal CT of the imaginary stage SRCn+1 can also be connected to the previous stage SRCn to prevent The imaginary stage SRCn+1 operates in an unstable state. Fig. 18 is a block diagram of a third shift register in the gate driving circuit of Fig. 5 according to the third embodiment of the present invention, and the 19th The figure is a circuit diagram of the third shift register of 5 in Fig. 18. Referring to Fig. 18, the gate drive circuit 140 includes a third shift register 143 containing a plurality of cascaded stages of SRC1sSRCl^ In other words, the output terminal OUT of each stage is connected to the input end in the next stage, and the control end of the previous stage. The third shift register 143 includes n stages SRC1 10 to SRCn corresponding to the gate lines GL1 to GLn, and further includes a dummy level SRCn+1. A control signal is supplied to the control terminal CT' of the nth stage SRCn and operates as a final stage. However, since there is no next stage after the imaginary stage, the control terminal CT of the imaginary stage SRCn+1 is connected to The fourth node N4 of the Nth stage SRCn. 15 Below, the potential at the fourth node N4 will be explained with reference to Fig. 19. When the output signal of the current stage is supplied from the Nth stage SRCn to the input terminal IN of the next stage SRCn+1, the seventh NMOS transistor NT7 is turned on. Therefore, the potential of the fourth node N4 is reduced to the level of the first power supply voltage VSS. 2〇 Although the seventh NMOS transistor NT7 is turned on, the fourth node N4

The first power supply voltage VSS is maintained because the size of the sixth NMOS transistor NT6 is 16 times larger than that of the NT7. When the output signal of the dummy terminal SRCn+1 supplied to the control terminal CT of the Nth stage SRCn becomes a threshold voltage level, the seventh NMOS transistor NT7 is turned off, and only the second power supply voltage VDD 34 M327032 The fourth node N4 is supplied via the sixth NMOS transistor NT6. Therefore, the potential of the fourth node N 4 is increased from the level of the first power supply voltage VS S to the level of the second power supply voltage VDD. When the output signal supplied to the dummy stage SRCn+1 of the control terminal CT is reduced to 5 to the low level, the fourth NMOS transistor NT4 is turned off. However, the fourth node N4 will still have the bias level of the second power supply voltage VDD because the second power supply voltage VDD is applied to the fourth node N4 via the sixth Nmos transistor NT6. The fourth node N4 is connected to the control terminal 10 CT' of the imaginary stage SRCn+1. Therefore, the fourth NMOS transistor NT4 of the imaginary stage SRCn+Ι can be turned on by the potential of the fourth node N4. Therefore, the state of the output signal outputted from the output terminal of the dummy stage SRCn+1 is changed to the cut-off voltage, and the virtual stage SRCn+Ι can be operated in the steady state. That is, if the control terminal CT of the imaginary stage SRCn+Ι is connected to the fourth node N4 of the Nth stage 15 SRCn, there is no need to have a separate line for connecting the input terminal IN of the first stage SRC1 to control the imaginary stage. Control terminal of SRCn+1. Fig. 20 is a perspective view showing an FPC having only one texture pattern layer in Fig. 3. Referring to Fig. 20, the FPC 190 includes a circuit substrate disposed separately from the LCD panel 110, and a plurality of traces electrically connecting the circuit substrate to the LCD panel 110. The FPC 190 performs an operation to provide the signals generated by the circuit substrate to the integrated driver die 18A. The wafer 180 receives an external image data signal 181a and an external control signal 181b. In other words, the external control signal 18 ratio includes vertical and water 35 M327032 flat sync signals VSYNC and HSYNC, and the main clock signal MCLK. In other words, when the integrated driving chip 180 is disposed in the LCD panel 110, the number of signals supplied to the LCD panel 110 via the FPC is reduced, so that the number of lines 191a provided in the FPC 190 can be reduced. Therefore, the FPC 5 190 can be made to have only one texture layer. The texture 191a is disposed on one of the first films 191 of the FPC 190 and is covered by the second film 192 of the first film 191. 21 is a schematic diagram of an LCD panel according to another embodiment of the present invention, and FIG. 22 is a block diagram showing a fourth and fifth 10 shift register of the first and second gate driving circuits in FIG. And Fig. 23 is the output waveform of the shift register in Fig. 22. Referring to FIG. 21, the TFT substrate 120 is divided into a first region corresponding to the color-passing substrate 130 and a second region not corresponding to the color filter substrate 130. The first area includes a display area, and a peripheral area is adjacent to the display area. On the display area, there are a plurality of data lines DL extending in the in-line direction, and a plurality of gate lines GL extending in the horizontal direction. A first and a second gate drive circuit 160 and 170 are respectively integrated on the left and right sides of the peripheral zone. That is, the first gate driving circuit 160 is connected to the odd gate line gL and is disposed on the left side of the peripheral region. The second gate driving circuit 17 is connected to the even number of gate lines 20 GL and is disposed on the right side of the peripheral region. At the top of the peripheral area adjacent to the display area, a line selection circuit 150 is provided to be connected to the data lines. In the second region of the TFT substrate 120, the integrated driving wafer 180 is provided to control the operation of the LCD panel 110. The wafer 18 can receive an external image data signal 36 M327032 and an external control signal 181b from an external circuit substrate disposed separately from the panel 110. The wafer 180 provides first and second drive control signals GC2 capable of controlling the first and second gate drive circuits 160 and 170, and provides analog drive signals and the like to the data lines. Each of the plurality of output terminals of the wafer 180, the output terminals for outputting the first and fifth second drive control signals GC1 and GC2 are connected to corresponding input terminals of the first and second drive circuits 160 and 170; The output terminal of the output line selection signal TG is connected to the control terminal of the line selection circuit 15A. Each channel terminal CH is connected to a corresponding input terminal of the line area selection circuit 15A, and each output terminal of the circuit 15A is connected to a corresponding data line DL or the like. In other words, the first driving control signal GC1 includes an enable signal ST, a first clock signal CK, a first power supply voltage v〇FF or vss, and a first power supply voltage VON or VDD. The second drive control signal GC2 includes a second clock signal CKB, a first power supply voltage VOFF or VSS, and a second power source voltage VON or VDD. Referring to Fig. 22, the first gate driving circuit 16A includes a first shift register 161. The first shift register 161 is disposed on the left side of the peripheral area of the display area, that is, where the odd-numbered gate lines GL1 to GLn-Ι are extended, and the first shift register 161 is first. The output terminals 丁111 to 〇11丁11_1 are connected to the gate lines GL1 to GLn-Ι of each of the odd numbers. The second gate drive circuit 170 includes a second shift register 171. The second shift register 171 is disposed on the right side of the peripheral area of the display area, that is, the even gate line (}12 to (}1^ and the like) and the second shift register m Each output terminal 〇UT^〇UTn is connected to each of the even-numbered gate lines GL2 to GLn, etc. 37 M327032 The signal output from the i-th stage SRCi of the first shift register 161 will pass through the first gate The line Gli is supplied to the input terminal of the jth stage SRCj of one of the second shift registers 171 provided on the right side of the peripheral area. Meanwhile, the output outputted by the i-th stage SRCi of the first shift register 161 The signal is supplied to the control terminal CTj-]L of the fifth stage SRCj-Ι as a control signal. Similarly, the signal output by the jth stage SRCj of the second shift register 171 is supplied to The input terminal INi+Ι of the (i+Ι)th stage SRCi+Ι of the first shift register 161 is simultaneously supplied to the control terminal CTi of the second SRCi of the first shift register 161 as a control signal The last stage SRCn+1 10 of the first shift register 161 operates as a dummy level and provides the control signal to the control terminal CTn of the last stage 511 (:: 11. See Figure 23, odd number The gate lines GL1 to GLn-Ι and the even number of gate lines GL2 to GLn and the like are successively shifted by the enable signal ST. In synchronization with the first and second clock signals CK and CKB, the odd gate lines GL1 to GLn- Ι and 15 even gate lines GL2 to GLn are scanned alternately. In most of the pixels included in a horizontal line, each odd pixel can be operated by the corresponding odd gate lines GL1 to GLn-Ι, and the even images The element can be operated by the corresponding even gate lines GL2 to GLn. That is, the 'second gate lines GL1 and GL2 will be operated to drive all the pixels contained in a horizontal line 20, so the number of gate lines will be increased to Therefore, when the LCD panel 120 has 160 horizontal lines, 320 gate lines are required to operate the 160 horizontal lines. According to the gate driving method described above, two horizontally adjacent TFT transistors are commonly connected to each other. a gate line, and the two TFT electro-crystal system are respectively connected to a line of two minutes 38 M327032. That is, although the pixels are arranged in the same horizontal line, the odd-numbered pixels are firstly used by the first gate driving circuit 160. Charging, then the even number of pixels reuses the second gate drive circuit 17 0. The even-numbered pixels are charged one clock slower than the odd-numbered pixels. 5 Figure 24 is a schematic diagram of an LCD panel according to still another embodiment of the present invention. Referring to Figure 24, the TFT substrate 120 The first area corresponding to the color filter substrate 130 and the second area not corresponding to the color filter substrate 130. The first area includes the display area, and a peripheral area adjacent to the display area. There are a plurality of data lines DL· extending in the in-line direction, and a plurality of gate 10 lines GL extending in the horizontal direction. A line selection circuit 15 is provided at the top of the peripheral area adjacent to the display area to drive the data lines DL. In the second region of the TFT substrate 120, an integrated drive wafer 200 is provided to control the operation of the LCD panel 110. In detail, the wafer 2 can receive an external image 15 data signal and an external control signal 181b from an external circuit substrate provided separately from the LCD panel 11A. Then, the wafer 2 turns on the first gate drive signal GDI to drive the odd gate lines GLn-Ι and the like, and the second gate drive signal GD2 to drive the even gate lines GLn and the like. Further, the wafer 2 〇〇 also provides an analog drive signal to the data lines DL and the like. The output terminals of the integrated driving chip 200 for outputting the first gate driving signal gdi 20 are connected to the corresponding odd gate lines GLn-1; and the output terminals for outputting the second gate driving signals GD2 are connected to Corresponding even gate line GLn and so on. The channel terminals CH of the wafer 200 are connected to corresponding input terminals of the line selection circuit 150, and the selection signal TG outputted from the wafer 2 is supplied to the line selection circuit 150. 39 M327032 Figure 25 is a block diagram of the integrated driver chip in Figure 24. In the following, elements having the same functions as those of the elements in Fig. 7 will be denoted by the same reference numerals and the functions of the elements will not be redundant. Referring to FIG. 25, the integrated driving chip 2 includes a dielectric portion 5 181, a memory 183, a source driver 185, a transponder 184, a gate driver 188, and a second gate driver 189. And a controller 182 and the like. The controller I82 provides first and second drive control signals GC1 and GC2' and a line select signal tg to the electrical translator 184. The first and the twelfth driving control signals GC1 and GC2 include a start signal ST, a first clock signal CK, a second clock signal K8, a first power supply voltage Vss, and a second power supply voltage VDD. The electric translating device 184 changes the levels of the first and second driving control signals GC1 and GC2, and provides the first and second driving 15 control signals GC1 and GC2 to the first Second gate drivers 188 and 189. The first gate driver 188 outputs a first gate driving signal GDI in response to the first driving control signal GC1, and uses the signal GDI to drive the odd gate lines GLn-Ι and the like. Similarly, the second gate driver 189 outputs the second gate driving signal GD2 in response to the second driving control signal GC2, and uses the signal 20 GD2 to drive the even gate lines GLn and the like. Further, the integrated driver chip 200 includes a common voltage generator 186 and a DC/DC converter 187. The common voltage generator 186 generates a common voltage and supplies it to a common electrode line provided on the LCD panel 11A. The DC/DC converter 187 receives a DC power supply voltage 187a from the outside and turns to the level of the voltage 187a of 40 M327032, and supplies it to a controller 182, a transponder 184, and a source driver, respectively. 185, and a common voltage generator 186. The present invention has been described in conjunction with the above embodiments. However, many of the corrections will be readily apparent to the expert by the above description. Therefore, the 5th modification change should still be included in the spirit and scope of the attached patent application. 0 I: Simple description of the drawing 3 FIG. 1 is a simplified illustration of a conventional LCD panel of a non-crystalline germanium TFT-LCD. Intention, 10 Fig. 2 is a simplified schematic view of a conventional amorphous 矽 TFT-LCD panel, in which a stock and a gate drive wafer are provided, and Fig. 3 is an exploded perspective view of the LCD of the preferred embodiment of the present invention; FIG. 5 is a schematic view showing a first embodiment of the TFT substrate in FIG. 3; FIG. 5 is a schematic view showing a second embodiment of the TFT substrate in FIG. 3; FIG. 6 is a block diagram showing the integration in FIG. A first embodiment of a driver chip; FIG. 7 is a block diagram showing a second embodiment of the integrated driver chip; and FIG. 8 is a circuit diagram showing a first line selection circuit selectively selecting a plurality of data lines Divided into two blocks; 20 FIG. 9 is an output waveform of the first line area selection circuit in FIG. 8; FIG. 10 is a circuit diagram showing a second line area selection circuit selectively dividing a plurality of data lines into three Block; FIG. 11 is an output waveform of the second line selection circuit in FIG. 10; 12 is a circuit diagram showing a third line area selection circuit selectively 41 M327032 dividing a plurality of data lines into four blocks; Fig. 13 is an output waveform of a third line area selection circuit in Fig. 12; A > The block diagram of the first shift register of the gate drive circuit in the fifth diagram of the first embodiment of the present invention; the first diagram is a detailed circuit diagram of the first shift register in FIG. 14; 16 is the output waveform of the first shift register in FIG. 14; FIG. 17 is the gate drive t path in the fifth figure according to the second embodiment of the present invention, and a second shift register Figure 18 is a block diagram of a gate-driving circuit in Figure 5 of the third embodiment of the present invention, a third shift temporary buffer; Figure 19 is a block diagram of Figure 18. FIG. 20 is a perspective view showing the structure of one of the FPCs in FIG. 3; FIG. 21 is a schematic view showing the LCD panel of another embodiment of the present invention; Block diagrams of the fourth and fifth shift registers of the first and second gate drive circuits; and FIG. 23 is the fourth and fifth shifts of FIG. Output waveform; graph 24 of the present embodiment schematic view of yet another novel embodiment of an LCD panel; and one of graph 20 of FIG. 25 drives wafer integration block 24 in FIG. [Main component symbol description] KXCD panel 36, 42···Drives printed circuit board 32,38···Band carrier package 40,62···Gate drive chip

34,61 ·. ·Data Driven Chip 50,90· · ·Amorphous Shishi TFT-LCD 42 M327032

60...glass substrate 60a···display area 60b···peripheral area 70...flexible printed circuit board 7l···control drive wafer 72...common voltage generator 100···ΙΧΌ panel assembly 110...LCD panel 120— TFT substrate 130···Color filter substrate 140, 160, 170-" gate drive circuit 141, 161... first shift register 142... lift unit 143... third shift register 144... lower unit 146...lifting drive unit 148···lower drive unit 149, 171...second shift register 150···line area selection unit 151···first line area selection circuit 152···second line area selection Circuit 153··· Third line area selection circuit 180, 200··· integrated drive wafer 181a... external image data signal

181b... external control signal 181 ... interface 182 ... controller 183 ... memory 184 · · electric translator 185 · source driver 186 · common voltage generator 187 - DC / DC converter 187a " _DC Power supply voltage 188···first gate driver 189···second gate driver 190···flexible printed circuit board 191···first film 191a···pattern 192···second film 200··· Backlight assembly 220...light assembly 240···light guide plate 260··· optical sheet 280...reflecting plate 290...module frame 300...frame 400...cover 500...LCD 43

Claims (1)

M327032 IX. Patent Application No.: No. 96205612 Patent Application Patent Revision No. 1 1. A liquid crystal display device comprising: 96.9 5 _ - a first substrate having a display area and a peripheral area adjacent to the display 7 [^ a second substrate is disposed opposite the first substrate; and a liquid crystal is disposed between the first and second substrates; wherein the first substrate comprises a plurality of switching devices disposed in the display area in a matrix a plurality of pixel electrodes are arranged in a matrix in the display area, and the image electrodes are connected to one of the first current electrodes of the switching devices; and the majority of the gate lines are arranged in a lateral direction, and each gate is arranged Each of the line systems is connected to the control electrode of the plurality of switching devices arranged in the horizontal direction; a plurality of data lines are arranged in a straight direction, and each data line is commonly connected to the plurality of switching lines of the direct rows a second current electrode of the device; a gate driving circuit disposed in the first region of one of the peripheral regions, that is, where the first end of the gate lines extends, and the gate lines can be continuously scanned; and an integrated driving Wafer, located in In the second area of one of the peripheral areas, where the first ends of the bedding materials and the lines extend, respectively, an external image poor material and an external control signal are respectively provided to provide a driving control signal to the gate driving circuit' - Analog signals to these data lines. 2. A liquid crystal display device comprising: a first substrate having a display area and a peripheral area adjacent to the display area, 44 25 M327032 10 15 a second substrate is disposed opposite the first substrate; and a liquid crystal is disposed between the first and second substrates; wherein the first substrate comprises: a plurality of switching devices are disposed in the display region in a matrix; The pixel electrodes are arranged in a matrix in the display area, and the pixel electrodes are connected to one of the first current electrodes of the switching devices; a plurality of gate lines are arranged in a lateral direction, and each gate line is arranged Each of the data lines is connected in a straight line, and each data line is connected in common to the plurality of switching devices arranged in the direction of the plurality of switching devices. a second current electrode; a gate driving circuit disposed in a first region of the peripheral region, that is, where the first end of the gate lines extends, and the gate lines can be continuously scanned; and a line selection circuit, Provided in a second area of the peripheral area, that is, where the first end of the data line extends, and can receive an analog driving signal of the block unit, select one of the data lines, and select a block unit Switch analog signal to the office a data line of the line area, and an integrated driving chip, disposed in the second area, and capable of providing a driving control signal to the gate driving circuit in response to an external image data and an external control signal, and providing a line selection signal and An analog signal of a block unit is given to the line selection circuit. 3. The liquid crystal display device of claim 2, wherein the integrated drive chip comprises a memory for storing external image data signals frame by frame. 45 M327032 4. The liquid crystal display device of claim 2, wherein the integrated drive chip comprises a memory for storing two lines of data to store external image data signals. 5 10 15 20 5. The liquid crystal display device of claim 2, wherein the integrated driving chip comprises a face for referring to the external image data and an external control signal, the interface can be interfaced with a CPU. A video board interface, a media Q interface and the like are compatible. 6. The liquid crystal display device of claim 2, wherein the integrated driving chip comprises: a common voltage generator that generates a common voltage and supplies it to a common electrode line or the like provided on a liquid crystal panel; And a DC/DC converter can receive an external voltage and raise or lower the external voltage, and then provide the controller, the electric translator, the source driver and the common voltage generator. 7. The liquid crystal display device of claim 2, wherein the external image data has a total of 18-bit parallel data, the 18-bit data each including 6-bit red, green, blue, etc.; The external control signal includes a master clock signal, a horizontal sync signal, a vertical sync signal, and a data operation signal. 8. The liquid crystal display device of claim 7, wherein the external control signals further comprise a mode selection signal, and the controller responds to the mode selection signal to generate the line selection signal. 9. The liquid crystal display device of claim 2, wherein the size of the block corresponds to a group consisting of a horizontal resolution of 46 M327032 including 1/1, 1/2, 1/3, 1/4. Selected in the group, supplemented by 5 10 15 20 to declare a liquid crystal display device specifically called 1|9, wherein when the block = corresponds to the 丨/2 horizontal temper, Wei will contain odd numbers, feed lines and - The second-line area contains an even number of data lines. The liquid crystal display device of claim 1 (), wherein the line selection circuit comprises: a plurality of first-selective transistors, each of the first-current electrode connections 7 outputting an analog drive signal of the integrated drive chip The first output:: the corresponding first output terminal 'and each second current electrode system 2 is in the corresponding odd (four) line, and the power generation_ is connected to the second output terminal of the selectable area selection signal a corresponding second output transistor, wherein the first current transistor is connected to the second corresponding first output terminal, and each of the second current electrodes is connected to a corresponding even data line And each of the control electrodes is connected to a third output terminal corresponding to one of the third output terminals that can output the fourth region selection signal. The liquid crystal display of the ninth item of the Shenyue patent fen, wherein when the size of the block corresponds to 1/3 of the horizontal riding degree, the -first line area contains the data line of the (3n·2)th piece. A second line region comprises a data line of (4) and a data line of the (3η)th line of the second line region, wherein the η is a natural number. Χ ', 13. If the patent scope of the application is In the liquid crystal display device, the line selection circuit includes: 10 47 M327032 H secret, supplement 1 a plurality of first-selective transistors, each of which is connected to an analogy that can output the integrated driver chip __ - (d) - corresponding to the first output terminal, and each of the second current electrode systems 5 is connected to the corresponding (3n_2)th data line, and each control electrode is connected to the first line region selection signal a second output terminal corresponding to one of the second output terminals; and a plurality of second selection transistors, wherein each of the first current electrodes is connected to a corresponding first wheel terminal, and each of the second current electrodes is connected In 10 - corresponding to the (10)) data line, and each control power is connected to And outputting a third output terminal corresponding to one of the third output terminals of the second line selection signal; and a plurality of third selection transistors, wherein each of the first current electrodes is connected to a corresponding first output terminal, and each The second current electrode is connected to the corresponding (fourth) data line, and each of the control electrodes is connected to a fourth output terminal corresponding to one of the fourth output terminals of the third line region selection signal. 14' is a liquid crystal display device as claimed in (4), wherein the drive control signals include a start signal, a 1-clock signal and a second clock signal. The liquid crystal display device of claim 14, wherein the closed driving circuit comprises a shifting (four) buckle-level cascaded stage, the majority of the stages having - the mth moving signal is applied to the first - the input terminal, and the shift register causes the output signals outputted by the output terminals of the heart to continuously select the closed lines; 48 M327032 5 10 15 The level includes: an input scorpion is connected to a gate line connected to an output terminal of the previous stage; an output terminal is connected to a corresponding gate line; and the control raft is connected to an output terminal of the next stage a connected gate line; a clock terminal can be input with a corresponding clock signal; a lifting device can provide a corresponding first and second clock signals to the output terminal; a lowering device can provide a -th supply voltage to the output a lifting device connected to one of the input nodes of the lifting device and responsive to a rising edge of the input signal input by the input terminal, the charging device is used to activate the lifting device, and the response is The control terminal is configured to drive one of the brake lines connected to the next stage to drive the rising edge of the number, and the lifting device is turned off by electrically powering the capacitor; 20 a lowering driving device is connected to the lowering device An input node 'connected to the job' to set the input node, and can respond to the rising edge of the drive signal for driving to the lower-level gate line to clear the Apparatus, and start the reduction device. For example, the driving device of the invention includes: a liquid crystal display device of 15 items, wherein the lifting capacitor is connected to the input node and the output terminal of the lifting device 49 16. M327032 a first transistor having a drain connected to a second supply voltage, a gate connected to the input terminal, and a source connected to the input node of the lift-up; 5 a second transistor The drain is connected to the wheel-in node of the lifting device, the gate is connected to the control terminal, and the source is connected to the first power voltage; and a second transistor is connected to the wheel of the lifting device The ingress node has a gate connected to the input node of the reduction device and a source connected to the first supply voltage. The liquid crystal display device of claim 15, wherein the reduction driving device comprises: a fourth transistor, the drain and the gate are connected to the second power voltage, and the source is connected to the lowering device And a fifth transistor having a drain connected to the input node 15 of the lowering device, a gate connected to the input node of the lifting device, and a source connected to the first supply voltage. 18. The liquid crystal display device of claim 15, wherein the control terminal of the last stage of the shift temporary storage is connected to the input terminal of the first stage 0 20 I9 · as described in item 5 of the patent application scope In the liquid crystal display device, the control terminal of the last stage of the shift register is connected to the input node of the lowering device of the previous stage. 20. The liquid crystal display device of claim 2, further comprising a flexible printed circuit board having a grain pattern connected to the first substrate and providing 50 M327032 External image data and external control signals are given to the integrated driver chip. 21. The liquid crystal display device of claim 2, wherein the integrated driving chip comprises: a face that can refer to the external image data and an external control signal, and a memory can store the external image data; A source driver can respond to the image data of the block unit read out by the memory block by block, and output the analog driving signal of the block unit; 10 an electric translating device can change the driving control signals and line selection a level of the signal; and a controller responsive to the external control signal input by the interface to store the external image data into the memory, and generate the drive control signal and the line selection signal, and the signals The electro-transformer 15 is provided, and the image data is read out one by one by the memory and supplied to the source driver. 22. A liquid crystal display device comprising: a first substrate having a display area and a peripheral region adjacent to the display>, wherein the second substrate is disposed opposite the first substrate; and a liquid crystal is disposed in the first Between the first substrate and the second substrate; wherein the first substrate comprises: a plurality of switching devices are arranged in a matrix in the display region; a plurality of pixel electrodes are arranged in a matrix in the display region, the images 51 The M327032 element electrode is connected to one of the first current electrodes of the switching devices; a plurality of gate lines are arranged in a lateral direction, and the gate lines are commonly connected to the control electrodes of the plurality of horizontally arranged switching devices; A plurality of data lines are arranged in a straight direction, and the data lines are connected to a second current electrode of each of the plurality of switching devices arranged in a straight line; a first gate driving circuit is disposed in the peripheral region In one of the first zones, where the first end of the gate lines extends, an odd number of gate lines can be driven, and a second gate drive circuit is disposed in a second zone of the peripheral zone, that is, 10 Where the second end of the gate line extends, the even number of gate lines and the like can be driven, and the gate lines are connected to the first gate driving circuit to continuously scan the gate lines; the line area selection circuit is disposed in the peripheral area a third region, that is, where the first end of the data line extends, and can receive the analog 15 driving signal of the block unit, select one of the data lines, and switch the analog driving signal of one block unit. Information to the selected line area And an integrated driving chip disposed in the third region and responsive to the external image data and the external control signal to provide a driving control signal to the first and second gate driving circuits, and providing a line selection signal and a The analog signal of block unit 20 is applied to the line selection circuit. A liquid crystal display device comprising: a first substrate having a display area and a peripheral area adjacent to the display; a second substrate disposed opposite the first substrate; and 52 M327032 10 15 a liquid crystal is disposed between the first and second substrates; wherein the first substrate comprises: a plurality of switching switches are arranged in a matrix in the display area; a plurality of pixel electrodes are arranged in a matrix in the display area The pixel electrodes are connected to one of the first current electrodes of the switching devices; a plurality of gate lines are arranged in a lateral direction, and the gate lines are commonly connected to the plurality of switching devices arranged in the horizontal direction. Control electrode; a plurality of data lines are arranged in a straight direction, the data lines are connected to a second current electrode of each of the plurality of switching devices arranged in a straight line; a line selection circuit is disposed in the peripheral region Wherein the first end of the data lines extends, and the analog driving signals of the block units are received, one of the data lines is selected, and the analog driving signal of one block unit is switched to the selected line area. a data line, etc.; and an integrated driver chip, located in the peripheral area where a line selection circuit is provided, and can receive external image data and external control signals, and provide a first gate drive signal to an odd gate And a second gate driving signal to the even-numbered gate lines, and the supply line area selection signals and the analog driving signal to the unit block of a line selection circuit region. 24. The liquid crystal display device of claim 23, wherein the output terminal of the first gate driving signal of the integrated driving chip is connected to the gate of the peripheral region where the first end of the gate line extends Odd gate lines in the line, etc. 25. The liquid crystal display device of claim 23, wherein the integration 53 M327032 The wheel-out terminal of the first-closed drive signal for driving the cymbal is connected to the intermediate line of the peripheral portion where the second end of the gate line extends. 5 10 15 26 · The liquid day display device of claim No. 1, wherein the integrated drive chip further comprises a common voltage generator capable of generating a common voltage and providing it to the liquid crystal. a common electrode line on the panel; and the C/DC converter can receive an external power supply voltage and raise or lower it, and then supply the power supply voltage to the hybrid (4), the electric translator, the source driver, and the common voltage generator . 27. The application of the liquid crystal display device of the 23rd item, wherein the integrated driving chip comprises: a face can refer to the external image data and an external control signal; a memory can store the external image data; - a source The driving device can respond to the image data of the block list 7L read out one by one in the memory, and rotate the analog driving signals of the block units; 20 an electric translating device can change a level of a first driving control signal, a second driving control signal and a line selection signal; and a first gate driver can respond to the first driving control signal to provide a gate Driving signals to odd gate lines, etc.; a second gate driver responsive to the second drive control signal, providing a second gate drive signal to an even number of gate lines, etc.; and 54 M327032 a controller responsive to the external input by the face input Controlling the signal and storing the external image data into the memory, generating the first and second driving control signals, the line selection signal, and the like, and supplying the same to the electrical translating device, and the memory is block by block The image data is read out and supplied to the source driver. 55