TWM392430U - Control circuit of multi-modal and non-loading effect RF power amplifier - Google Patents

Description

M392430 V. New Description: [New Technology Field] This is a multi-modal no-load RF power amplifier control circuit, especially one that uses the impedance inversion Gmpedance * inVerting principle to make the RF power amplifier high. Medium and low power amplification: There is no load effect when the unit is turned off, so that the power switch for switching can be omitted to reduce the manufacturing cost. [Prior Art] The length of standby and talk time has always been the main performance emphasized by mobile devices such as mobile phones. In order to effectively extend the talk and standby time of mobile phones, many technologies have been proposed one after another, and the efficiency of RF power amplifiers has been improved. Among them, the development direction, as shown in the fifth figure, is one of the known technical solutions for improving the working efficiency of the RF power amplifier, mainly using a DC-DC converter (71) (LM32〇5). Supply and change the operating power (VCC) of the RF power amplifier (70) to improve the operating efficiency of the RF power amplifier (70)

Although the foregoing technical solution is feasible, the disadvantage is that the manufacturing cost is relatively high. The reason is that it is necessary to use an additional chip (DC/DC) & uH-level inductor, so it is difficult to call the delay. . As shown in the sixth figure, it discloses another technical solution for improving the working efficiency of the RF power amplifier, which is mainly composed of a plurality of amplifiers ΑΜρι~ΑΜρ4 and two power switches S1 and S2 respectively forming a high-power amplification unit (81). a medium power amplifying unit (82) and a low power amplifying unit (83); the high 3 medium and low power amplifying units (81) to (83) are connected in parallel to the RF input terminal (RFIN) and Between the RF output terminals (RFOUT); wherein: the same power amplifying unit (81) is connected in series by two amplifiers AMP1, AMP2, and the medium power amplifying unit (82) is connected by an amplifier AMP3, -, a matching circuit ( 84) and - power switch S1 _ connected to form; the low power amplifying unit (83) is also composed of - amplifier AMp4, a matching circuit (85) and a power switch S2 in series; due to the amplifier A of each power amplifying unit, ~ The number of AMP4 & transistors (m=2, 40, 8, O not (five), so the RF signal passes: the same power amplification unit, which will perform different power amplification processes to enable the RF power amplifier to be selected according to requirements. Execute not power amplification To improve the efficiency of its work. The switching between the back, middle and low power amplification units (81) to (83) is controlled by the bias voltage ((1) Μ) of its amplifier ΑΜρ卜ΑΜρ4 and the power switches S1, S2. However, the above known solutions still have the disadvantages: 1_ power switch causes power loss: when the middle and low power amplification units (82) (83) are respectively executed, the RF signal will be π Μ, % when passing power Causes additional power loss.

2. A special BiFET process is required. · Because the amplifier ΑΜρι~ * 4 is implemented by the HBT process, the power switch S1 and the S2 are replaced by the PHEMT process. The implementation of this technical solution must integrate the HB process and the PHEMT process. Or use additional power switching chips to achieve, but will increase the technical difficulty and production costs. As shown in the seventh figure, another technical solution is disclosed, which is similar to the previous technical solution. The main system is composed of a plurality of amplifiers AMp, AMp3, and a power switch S, respectively, and a high-power amplification unit (9彳) and a The low power amplifying M392430 unit (92); wherein: the high power amplifying unit (91) is composed of two amplifiers AMPHMP2 connected in series, and the output end of the back end amplifier aMp is connected with the matching circuit (90) and the low power amplifying unit ( 92) is connected in parallel with the high power amplifying unit (91), which is composed of an amplifier am P3, a λ/4 transmission line (93) and a power switch S; wherein the power switch s is connected to the input node of the transmission line (93) Between the ground terminal and the ground terminal # to control whether the transmission line (93) generates an impedance inversion effect.

The working principle of the foregoing technical solution is that the high power amplifying unit (9彳) works 'When the low power amplifying unit (92) is turned off', the power on_s will be turned on to make the transmission line (93) input node ground, # this - The transmission line (93) will generate an impedance inversion, while generating a high impedance at the output node of the transmission line (93) 'because the high power amplification unit (91) is operating, its output is matched to low by the matching circuit (90). The impedance node, when the output node of the transmission line (93) is high impedance, does not affect the output of the high power amplifying unit (91); #高力率率 amplifying unit (91) turns off 'and the low power amplifying unit (92) works, Then, the power switch S_' transmission line (93) is used as a transmission signal. According to the foregoing (4) scheme, the RF power amplifier can also be switched to perform high and low power amplification to improve the working efficiency, but it is the same disadvantage as the previous technical solution: that is, the RF signal generates extra power when passing through the power switch, Loss, and (d) the use of the process or the use of additional wafers, resulting in increased manufacturing costs. As can be seen from the above, although there are technical problems to improve the RF power amplifier, although it is feasible, the technical problems of the two-handed system and the high cost of the process are still to be further reviewed, and a feasible solution is sought. 5 [New content] The main purpose of this project is to provide a multi-modal no-load effect. Up to 1 == amplifier control circuit, which can be used for the purpose of ordering and eliminating the need to use power switches, thereby effectively controlling manufacturing costs. The main technical means of the above-mentioned RF power and drought amplification control circuit include: P & with - input terminal and - transmission system as - RF output terminal; , Output: high power The amplifying unit is composed of more than one amplifier, and the output terminal of the early 7^ is connected to the input end of the impedance matching circuit: the medium power amplifying unit is connected in parallel with the high power amplifying unit, and the package S is The first-impedance inverter unit has an input terminal and a wheel-out terminal, and the input power is in the input spot. The power is connected to the tm. The power is connected in the early morning 70, and the output end is connected to the input end of the impedance matching circuit. 2: the power amplifying unit is connected to the high- and medium-power amplifying unit and includes an amplifier; the second impedance inverting unit has an input end and a transmission wheel-in terminal connected to the low-power amplifying unit, The output end is connected to the first resistance; the input end of the inverter unit; the impedance 1 is used when the control circuit is used, and is connected to the end of the impedance matching circuit and the resistor to make the impedance matching circuit rabbit Low-impedance node; when the control circuit is operated in the high-power amplification mode, the high-power amplifier 6-impedance inverter 1 f towel, the low-power amplification unit is turned off, and the first and second will generate an impedance inversion effect, so that The medium and low power amplifiers are not affected by the =, and then the low-resistance large single-circuit circuit at the input end of the impedance matching circuit operates in the medium power amplification mode, and the high-power amplifier is operated at the same time. The first: 2 inverter unit, impedance matching circuit transmits the signal, in this case, the output of the power amplifying unit has no load effect; when the rate control circuit operates in the low power amplification mode, the high and the power is inverted: Off: only the low-power amplifier unit works, it transmits the signal through the second resistor...70 to match the circuit, and in the first-impedance inverter, the output of the high- and medium-power amplifier unit has no load effect; Know the flute creation in the inverter of high, medium and low power amplification units! The first and second impedance inverting units use the first and second impedance terminals 2: the two-impedance inverter action 'the output load effect when the power amplifying unit is turned off', thereby eliminating the power switch for switching, and thus the wood It is troublesome with the BIFET process and effectively reduces manufacturing costs. [Embodiment] The circuit structure of the first preferred embodiment of the present invention is as follows: FIG. 2 is mainly composed of a high-power amplification unit (1〇), and a power amplification single low power amplification unit (12) - an impedance matching circuit (13), a first: an anti-inverting unit (14) and a second impedance inverting unit, wherein: the impedance matching circuit (13) is connected to the high power amplifying unit (1) Between the JVI view 430 output terminal and a RF output terminal (RF〇UT), a 50 ohm resistor is connected to the RF output terminal during use, and the input of the impedance matching circuit (13) is made low. Impedance (eg 2 ohm) node. The same power amplification unit (1 〇) is composed of more than one amplifier. In the present example, it contains two amplifiers AMP11, wherein the output of the back-end amplifier AMP12 is connected to the impedance matching circuit (13). The input is connected to the 'front end amplifier II AMP1' and the wheel end is connected to a radio frequency input terminal (RFIN);

The medium power amplifying unit (彳1) comprises an amplifier AMP2 having a 钿 and an output terminal, the output end of which is transmitted through the first impedance inverting unit (14) and the input end of the impedance matching circuit (13) Connected to the high power amplifying unit (10) in a parallel state; in this embodiment, the first impedance inverting unit (14) is composed of a transmission line of -λ/4, which has a wheel end and One round of the output, the input end is connected to the output end of the medium power amplifying unit (1), and the output end of the first impedance inverting unit (14) is connected to the impedance matching circuit (13)

In the present embodiment, the power amplification single S(1) in the first step includes the L delay line (111), and the end of the delay line (1)]) is connected to the input end of the amplifier Ρ2, and the other end is - The RF input terminal (RFIN) is connected, and the delay line (111) is described in detail later. Furthermore, the low power amplifying unit (12) includes an amplification circuit 3, and its input terminal is still connected to the RF wheel input terminal ( RF|N) connection, the output of the two-impedance inverter unit (15) is poor, ^, the ancient ', the input terminal of the impedance inverter unit (14) is connected with the south power amplification single opening (0) in parallel state; In this embodiment, the second impedance inverter unit (1 r has an input terminal and a transmission line, and the output terminal thereof has an output terminal and a low power amplification unit 8 M392430 (12 The output end of the connection is connected to the input end of the first impedance inverting unit (14). The detailed construction of the first preferred embodiment of the present invention can be understood from the above description, and the working principle is as follows: Said: · '#前前的' The aforementioned RF power amplifier uses its RF input: * terminal (RF〇U) A resistor is provided, which is typically 50 ohms, and the input of the impedance matching circuit (13) constitutes a low impedance (e.g., 2 ohm) node. # ” The aforementioned control circuit operates in a high power amplification mode with high power. The two amplifiers AMP11 and AMP12 of the amplifying unit (1〇) operate, the amplifiers AMP2 and AMP3 of the medium and low power amplifying unit (11) (12) are turned off, and the wheel end of the impedance matching circuit (13) is low impedance (Z1A). Therefore, the RF power amplifier operates in a high power amplification mode (HIGH P〇WER M0DE); the amplifier AMP3 of the low power amplification unit (12) is turned off, and its output is high impedance (Z3A), passing through the second impedance inverting unit. (15) Generate impedance inversion, 产生 generate a low impedance (Z2B) at the output of the f-impedance reverse side unit (15), and, in addition, the power amplifier unit. The amplifier AMp2 is also turned off, and its output is 冋 impedance. Therefore, the input signal of the first-impedance inverter unit (14) is determined by the low-impedance output terminal (Z2B) of the second impedance inverting unit (15), which is not affected by the high impedance of the output of the amplified AMP2, so that the first impedance is reversed. Variable unit (14) due to input For low impedance, the output is inverted to high impedance (Z1B), and Z1B is greater than Z1 A, so it does not affect the output of the high power amplification unit (10). The aforementioned control circuit operates in low power amplification mode with low power. Amplified single 兀 (12) amplified state AMP3 working high power amplification unit (1 〇) put 9 M392430 large AMP11, AMP12 are turned off, and amplifier AMP12 output is high impedance 'with no load effect; and power amplification unit (11) The amplifier AMP2 is also turned off, its output is high impedance, and there is no load effect. · Due to the impedance matching of the impedance matching circuit (13), its input terminal Z1A is still low impedance, and is reversed via the first impedance. The variable unit (14) generates an impedance inversion, forms a relatively high impedance (22.a) at the input end of the first impedance inverting unit (14), and generates an impedance inversion through the second impedance inverting unit (15). A high impedance (Z3A) is formed at the input of the second impedance inverting unit (15), wherein:

Z3A = (Z〇_TL2)2/Z2A Z0_TL2 = impedance of the second impedance inverter unit (14) Since Z3A (100 ohms) is greater than Z1A (2 ohms), and Z3A is greater than Z2A (25 ohms), the amplifier The AMP3 performs low power amplification in a low current mode of operation. If the foregoing control circuit operates in the medium power amplification mode, the amplifiers AMP2 and AMP3 of the medium and low power amplification units (11) (12) operate simultaneously, and the amplifier AMP11'AMP12 of the south power amplification unit (10) is turned off, and the amplifier is turned on. The output of AMP1 2 is high impedance without load effect; due to the impedance matching of impedance matching circuit (13), its input terminal z彳A is still low impedance, and is generated via the first impedance inverting unit (14). Impedance inversion, forming a relatively high impedance (Z2A) at the input end of the first impedance inverting unit (14), thereby constituting the loads of the amplifiers AMP2, AMP3 of the medium and low power amplifying units (11) (12), wherein: Z1A = 2 ohms Z2A = 25 ohms Impedance of the first impedance inverter unit (14) z〇_TL1=(Z1A*Z2A)0 5 Amplifier AMP2 of the medium and low power amplification unit (1 1) (1 2) M392430 AMP3 load impedance = Z2A = 25 ohms, assuming that the amplifiers AMP2, AMP3 have the same number of transistors (m2 = m3), ij (AMP2 RL) / / (AMP3 RL) = Z2A and (AMP2 RL) = (AMP3 RL) = 2*Z2A = 50 ohms due to the load impedance of the amplifier AMP2, AMP3 = Z2A = 25 ohms The medium and low power amplification units (11) and (12) perform medium power amplification in the low current operation mode. Furthermore, the medium and low power amplifying units (11) (12) operate simultaneously, and the amplifier AMP3 of the low power amplifying unit (12) transmits the radio frequency signal to the first impedance inverting unit through the second impedance inverting unit (15). (14) The amplifier AMP2 of the medium power amplifying unit (11) directly transmits the RF signal to the first impedance inverting unit (14). To avoid causing the time difference, the AM P2 input terminal of the amplifier of the medium power amplifying unit (1 1) is provided. There is a delay line (彳11) to balance the signal transmission time. As shown in the second figure, the circuit configuration of the second preferred embodiment of the present invention is mainly composed of a high power amplifying unit (1〇), a medium power amplifying unit (11), and a low power amplifying unit (12A). , an impedance matching circuit (13), a first impedance inverting unit (14) and a second impedance inverting unit (15), etc., the main structure is substantially the same as the first embodiment, the difference is: the low The power amplifying unit (12A) further includes an amplifier AMP4 which is connected in parallel with the original amplifier am P3, and the amplifier am P4 has a smaller number of transistors than the amplifier AMP3. In terms of working principle, the 'high power amplification mode is the same as the first embodiment, and in the low power amplification mode, the amplifiers AMPU, AMP12, AMP2 and low power amplification unit (12) of the high and medium power amplification units (10) (11) The M392430 AMP3 is turned off, only the low-power amplifier unit (12) new amplifier AMP4 ^ 'high power amplifier unit 0G) amplification n AMP11 'AMP12 are off' and the amplifier aMP12 output is high impedance, no load The effect '· and the amplifier AMp2 of the medium power amplifier unit (1彳) is turned off, and its output is high impedance' and no load effect; due to the impedance matching of the impedance matching circuit (13), its input terminal Z1A is still low impedance. An impedance inversion is generated via the first impedance inverse unit (14), a relatively high impedance (Z2A) is formed at the input end of the first impedance inverting unit (14), and an impedance inverse is generated by the second impedance inverting unit (15). Variable, while forming a high impedance (Z3A) at the input of the second impedance inverting unit (15), since Z3A (100 ohms) is always greater than Z1A (2 ohms) 'Z3A is greater than Z2A (25 ohms), and the power of the amplifier AMP4 Number of crystals (m3&g t;m4) is less than the amplifier AMP3, so the amplifier AMp4 performs low power amplification in the low current mode of operation. In the medium power amplification mode, the medium and low power amplification units (11) (12) work simultaneously, but the amplifier of the low power amplification unit (12) is turned off, and only the amplifier AMP3 operates 'the middle and low power amplification units (1 1 The amplifiers AMP2, AMP3 of (12) perform low power amplification in the low current mode of operation. As shown in the third figure, the circuit structure of the third preferred embodiment of the present invention is mainly composed of a high power amplifying unit (1-8) and a medium power amplifying unit (1 1) 'a low power amplifying unit. (12), an impedance matching circuit (13), a first impedance inverting unit (14), a second impedance inverting unit (15), and a third impedance inverting unit (16); The difference between an embodiment is that the high power amplifying unit (10A) further includes a delay line (1〇1) and an amplifier AMP13, and the delay line (101) is serially connected to the original two amplifiers 12 AMP11 and AMP12. In addition, the newly added amplifier 13 has an input terminal and an output terminal whose input terminal is connected to the output end of the amplified stomach AMP11. The amplification _ AMP13 output terminal is transmitted through the third impedance inverting unit (16). The wheel terminal of the impedance matching circuit (13) is connected, and the output of the second impedance inverting unit (15) is connected to the input of the third impedance inverting unit (10). When the foregoing control circuit operates in the high power amplification mode, the amplifiers AMP1i, amp12, and AMP13 of the high power amplification unit (10A) operate, but the amplifiers AMP2 and AMP3 of the medium and low power amplification units (11) (12) are both turned off and impedance. The input of the matching circuit (13) is low impedance (Z1A), so the RF power amplifier works in the high power amplification mode (H|GH p〇WER m〇de): the amplification of the low power amplification unit (12) is $ AMp3 _closed, its output is high impedance (Z3A) 'passed through the second impedance inverting unit (15), the first impedance inverting unit (14), and at the output of the first impedance inverting unit (14) Produces high impedance (Z1D) with no load effect. In addition, when the amplifiers αμρί2 and ΑΜΡ13 of the power amplifying unit (1〇A) have the same number of electrical aa bodies (mi2 = m13), the impedance of the third impedance inverting unit (16) is Z〇_TL3 = 2 Z1A = 4 ohm. When the foregoing control circuit operates in the low power amplification mode, the amplifier AM P3 of the low power amplification unit (12) operates, and the amplifiers AMP11'AMP12, AMP13 of the high power amplification unit (1A) and the amplifier of the medium power amplification unit (ή) AMP2 is turned off, the output of amplifier AMP2 and AMpi2 is high impedance, and there is no load effect; while the amplifier AMP3 of low power amplifier unit (12) works, due to the impedance matching function of impedance matching circuit (13), its input terminal Z1A still For low impedance, impedance inversion is generated via the third impedance inverting unit (16) 13 M392430'. A relatively high impedance is formed at the input of the third impedance inverting unit (16) (Z1C, Z1C=(Z〇一TL3) 2/Z1A), and the impedance inversion is generated by the first impedance inverting unit (14) and a high impedance is formed at the input end of the first impedance inverting unit (14) (Z2A, Z2A=(Z〇_TL1)2 /Z1C), finally the impedance inversion is generated by the second impedance inverting unit (15), and the high impedance is formed at the input end of the second impedance inverting unit (15) (Z3A, z3A = (Z〇_TL2) 2/ Z2A), by - Z3A (1 ohm) strange is greater than Z1A (2 ohms), and Z3A is large -Z2A (25 ohms), it is based amplifier AMP3 at low current operation mode of a low power amplification line I performed. If the aforementioned control circuit operates in the medium power amplification mode, the amplifiers AMP2 and AMP3 of the medium and low power amplification units (1 1) (12) operate simultaneously, and the amplifiers AMP1 1 , AMP 12 , and AMP 13 of the high power amplification unit ( 10 A ) are both Closed, the amplifier AMP12 output is high impedance, no load effect; due to the impedance matching of the impedance matching circuit (13), its input terminal Z1A is still low impedance, and via the third impedance inverter unit (16) Generate impedance - Inverter 'forms a relatively high impedance at the input of the third impedance inverting unit (16) (Z1 C, Z1 C = (Z〇_TL3) 2 / Z1 A) 'Because of the medium power amplification mode, Z2A The load impedance of the amplifiers AMP2 and AMP3 of the medium and low power amplification units is greater than Z1A, and the load impedance of the amplifiers AMP2 and AMP3 is = Z2A = 25 ohms. Assuming that the number of transistors of the amplifiers AMP2 and AMP3 is the same (m2 = m3),

(AMP2 RL) / / (AMP3 RL) = Z2A and (AMP2 RL) = (AMP3 RL) = 2 * Z2A = 50 ohms Because the load impedance of the amplifier AMP2, AMP3 = Z2A = 25 ohms, the medium and low power amplification unit (11) (12) Performs medium power amplification in the low current operation mode. M392430 is also shown in the fourth figure, the circuit structure of the fourth preferred embodiment of the present invention is basically a combination of the foregoing second and third embodiments, mainly by a power amplification unit (10A), a middle a power amplifying unit 、), a low power amplifying unit (12A)' - an impedance matching circuit (13), a first impedance inverting unit (14), a second impedance inverting unit (15) and a third impedance The inverter unit (16) and the like; wherein the low power amplifying unit (12A) is the same as the low power amplifying unit (12) of the second embodiment, further comprising an amplifier AMp4, the amplifier AMP4 and the original amplifier AMp3 Parallel, and for amplification, AMP4 has fewer transistors than amplifier AMp3. The high power amplification unit: M10A) is the same as the high power amplification unit (1GA) of the third embodiment. [Simple description of the diagram] First diagram Second diagram Third diagram Fourth diagram Fifth diagram

A circuit diagram of the first preferred embodiment of the present invention. A circuit diagram of a second preferred embodiment of the present invention. A circuit diagram of a second preferred embodiment of the present invention. The circuit circle of the fourth preferred embodiment of the present invention is created. The circuit diagram of the known RF power amplifier control circuit is shown in the sixth figure: the other is the seventh picture: another known RF power amplifier control circuit, the known RF power amplifier || control (4) Circuit power [main component symbol description] 15 M392430 (10) (10A) South power amplifier unit (101) (111) delay line (u 1) power amplifier unit (1 2) (1 2A) low power amplifier unit ( 13) Impedance matching circuit f First impedance inversion unit (15) Second impedance inversion unit (16) Third impedance inversion unit (70) RF power amplification n (71) DC to DC converter (81) still power Power amplification unit (83) in the amplification unit (81) low power amplification unit (84) (85) E distribution circuit

(91) High power amplification unit (92) Low power amplification unit (93) Transmission line 16

Claims (1)

Ming 2430 VI. Application Patent Range: 1. A multi-mode no-load effect RF power amplifier control circuit 'includes: - Impedance matching circuit with one input and one round output, and its output is used as a RF output A high power amplifying unit is composed of more than one rose, and is connected to an output end of the power amplifying unit to an input end of the impedance matching circuit; a medium power amplifying unit is connected in parallel with the high power amplifying unit , comprising an amplifier; a first impedance inverting unit having an input end and an output end, the input end of which is connected to the medium power amplifying unit; the output end of which is connected to the wheel end of the impedance matching circuit; The power amplifying unit is connected in parallel with the foregoing high and medium power amplifying unit, and includes an amplifier; a second impedance inverting unit has an input end and an output end, and the input end thereof is connected to the low power amplifying unit, and the output thereof is The end system is connected to the input end of the first impedance inverting unit. 2. The multi-modal no-load effect of the RF power amplifier controlled by Yue Yue. As described in the scope of the patent application, the power amplifier unit is mainly composed of AMP11 and AMP 12 in series. The back-end amplifier AMP12 output is connected to the input of the impedance matching circuit. 3. The multi-mode no-load effect RF power amplifier control system as described in claim 2, the power amplification unit is electrically connected between the two amplifiers AMP1 1, AMP12. Delay line 'and front-end amplifier 17