TWI913722B - Method of forming semiconductor structure - Google Patents

Abstract

The present disclosure provides a method of forming a semiconductor structure. A method of forming a semiconductor structure includes forming an active region on a substrate. A first etching process is performed to form a recess in the active region. A second etching process is performed to laterally expand the recess such that the recess has a first sidewall and a second sidewall connected to the first sidewall, and an angle is formed between the first sidewall and the second sidewall, in which the angle is in a range of 100 degrees to 120 degrees.

Description

Methods for forming semiconductor structures

This disclosure relates to a method for forming semiconductor structures.

In the semiconductor industry, advancements in integrated circuit materials and design have led to several generations of integrated circuits, each with smaller and more complex circuits than the previous one.

However, existing semiconductor structures still face many problems. For example, the size of the bit-line contacts in semiconductor structures is too small, resulting in excessively high impedance between the bit-line contacts and the bit lines. In addition, the electron mobility of semiconductor structures (especially through the bit-line contacts) still needs improvement. Therefore, it is desirable to improve the structure of the bit-line contacts and develop semiconductor structures with higher performance.

The technique disclosed herein is a method for forming semiconductor structures.

According to some embodiments of this disclosure, a method for forming a semiconductor structure includes forming an active region on a semiconductor substrate. A first etching process is performed to form a groove in the active region. A second etching process is performed to laterally expand the groove, such that the groove has a first sidewall and a second sidewall connecting the first sidewall, and the first sidewall and the second sidewall form an angle, wherein the angle is in the range of 100 degrees to 120 degrees.

In some embodiments disclosed herein, the method of forming a semiconductor structure further includes performing a third etch process to deepen the groove, so that the groove has a third sidewall extending downward from the second sidewall.

In some embodiments disclosed herein, the second etching process is a wet etching process, and the third etching process is a dry etching process.

In some embodiments disclosed herein, the method of forming a semiconductor structure further includes filling a groove with a conductive material to form a conductive contact in the active region. Bit lines are formed on the active region and electrically connected to the conductive contacts.

In some embodiments disclosed herein, a second etching process is performed to deepen the grooves.

The technique disclosed herein is a method for forming semiconductor structures.

According to some embodiments of this disclosure, a method for forming a semiconductor structure includes forming an active region on a semiconductor substrate. A first etching process is performed to form a groove in the active region, wherein the first etching process results in a groove having a first depth. A second etching process is performed to laterally expand the groove, such that the groove has a first sidewall and a second sidewall connecting the first sidewall. A third etching process is performed to deepen the groove, such that the groove further has a third sidewall extending downward from the second sidewall, wherein the third etching process results in a groove having a second depth, the ratio of the second depth to the first depth being in the range of 1.5 to 2.5.

In some of the embodiments disclosed herein, the same etching mask is used for performing the first etching process, the second etching process, and the third etching process.

In some embodiments disclosed herein, the method of forming a semiconductor structure further includes filling a groove with a conductive material to form a conductive contact in the active region.

In some embodiments disclosed herein, the method of forming a semiconductor structure further includes forming a character line in the active region and adjacent to a conductive contact, wherein the top surface of the conductive contact and the top surface of the character line are substantially coplanar.

In some embodiments disclosed herein, the method of forming a semiconductor structure further includes forming bit lines on the active region and electrically connecting them to conductive contacts.

According to the above-described embodiment disclosed herein, since the conductive contact includes a top portion and a bottom portion, and the top portion has a first sidewall and a second sidewall connected to the first sidewall, and the first sidewall and the second sidewall form an angle, the volume of the conductive contact can be increased and the tensile stress can be increased, thereby increasing the electron mobility. Therefore, the performance of the semiconductor structure can be improved.

The following diagrams disclose several embodiments of this disclosure. For clarity, many practical details will be explained in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, these practical details are unnecessary in some embodiments of this disclosure and therefore should not be used to limit this disclosure. In addition, for the sake of simplicity, some conventional structures and components will be shown in the diagrams in a simplified manner. Furthermore, for the convenience of the reader, the dimensions of the components in the diagrams are not drawn to scale.

As used in this disclosure, “about,” “approximately,” or “substantially” generally means within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent. The values given herein are approximate, meaning that unless explicitly stated otherwise, the meaning of the terms “about,” “approximately,” or “substantially” can be inferred.

Figure 1 is a cross-sectional view of a semiconductor structure 10 according to some embodiments of the present disclosure, and Figure 2 is a top view of the layout of the semiconductor structure 10 in Figure 1. In other words, Figure 1 is a cross-sectional view of the semiconductor structure 10 along line A-A in Figure 2. Figure 3 is a partially enlarged view of region R (i.e., bit line contact 140) in Figure 1. Referring to Figures 1 to 3, the semiconductor structure 10 includes a semiconductor substrate 110, an active region 120, a word line 130, a bit line contact 140, and a bit line 150. The active region 120 is disposed on the semiconductor substrate 110. The word line 130 is disposed in the active region 120. The bit line contact 140 is disposed in the active region 120 and adjacent to the word line 130. The bit line contact 140 includes a top portion 140a and a bottom portion 140b. The top portion 140a of the bit line contact 140 has a top surface 145, a first sidewall 141, and a second sidewall 143, wherein the first sidewall 141 extends continuously downward from the top surface 145, and the second sidewall 143 connects to the first sidewall 141 and extends continuously downward from the first sidewall 141, wherein the first sidewall 141 and the second sidewall 143 form an angle θ. A bit line 150 is disposed on the bit line contact 140. Through the configuration of the bit line contact 140, the volume of the bit line contact 140 can be increased and the tensile stress of the bit line contact 140 can be increased, thereby increasing the electron mobility. Therefore, the performance of semiconductor structure 10 can be improved. For example, electron mobility can be increased by approximately 60% to 65%.

In some embodiments, the angle θ between the first sidewall 141 and the second sidewall 143 of the top portion 140a of the bit line contact 140 is a blunt angle. For example, the angle θ is in the range of about 100 degrees to about 120 degrees (e.g., about 110 degrees). If the angle θ falls within the above range, it helps to increase the tensile stress of the bit line contact 140, thereby increasing the electron mobility. In some embodiments, the top portion 140a of the bit line contact 140 has two tips 142, respectively located at the junction of the first sidewall 141 and the second sidewall 143. The two tips 142 may be located in opposite positions on the same horizontal plane, and the two tips 142 are respectively located at the outermost edge of the bit line contact 140. In some embodiments, the first sidewall 141 and the second sidewall 143 are linear sidewalls. In some embodiments, the first sidewall 141 and the second sidewall 143 are inclined sidewalls.

The bottom portion 140b of the bitline contact 140 has a sidewall 144 connecting to the second sidewall 143 of the top portion 140a and a bottom surface 146 connecting to the sidewall 144. The sidewall 144 extends continuously downward from the second sidewall 143. In some embodiments, the bottom portion 140b of the bitline contact 140 has a U-shaped cross-sectional profile. That is, the sidewall 144 of the bottom portion 140b is a curved sidewall. In some other embodiments, the bottom portion 140b of the bitline contact 140 has a quadrangular cross-sectional profile, such as a rectangular cross-sectional profile. That is, the sidewall 144 of the bottom portion 140b is a linear (or straight) sidewall and is perpendicular to the bottom surface 146.

In some embodiments, the top portion 140a and the bottom portion 140b of the bit line contact 140 have different cross-sectional profiles. For example, the top portion 140a of the bit line contact 140 has a hexagonal cross-sectional profile, while the bottom portion 140b of the bit line contact 140 has a quadrangular cross-sectional profile.

In some embodiments, the top portion 140a of the bit line contact 140 has a maximum width W1 at a vertical distance D1 from the top surface 145 of the bit line contact 140. In other words, the maximum width W1 is the distance between the two tips 142 of the bit line contact 140. In some embodiments, the maximum width W1 is in the range of approximately 70 nanometers to approximately 110 nanometers (e.g., approximately 90 nanometers). If the maximum width W1 falls within this range, it helps to increase the tensile stress of the bit line contact 140, thereby increasing the electron mobility. In some embodiments, the vertical distance D1 is in the range of approximately 10 nanometers to approximately 20 nanometers (e.g., approximately 15 nanometers).

In some embodiments, the top surface 145 of the bit line contact 140 has a width W2, and the bottom surface 146 of the bit line contact 140 has a width W3, wherein the width W2 is greater than the width W3. In some embodiments, the width W2 is in the range of about 50 nanometers to about 70 nanometers (e.g., about 60 nanometers), and the width W3 is in the range of about 40 nanometers to about 60 nanometers (e.g., about 50 nanometers). In some embodiments, the width of the bottom portion 140b of the bit line contact 140 is constant. That is, the entire width of the bottom portion 140b of the bit line contact 140 is substantially the width W3. In some embodiments, the maximum width of the bottom portion 140b of the bit line contact 140 (e.g., width W3) is smaller than the maximum width of the top portion 140a of the bit line contact 140 (e.g., maximum width W1).

In some embodiments, the horizontal distance S1 between the top surface 145 of the bit line contact 140 and the nearest tip 142 is in the range of about 10 nanometers to about 20 nanometers (e.g., about 14 nanometers). The horizontal distance S2 between the bottom surface 146 of the bit line contact 140 and the nearest tip 142 is in the range of about 20 nanometers to about 30 nanometers (e.g., about 24 nanometers). In some embodiments, the horizontal distance S2 is greater than the horizontal distance S1. In some embodiments, the maximum width W1 of the top portion 140a of the bit line contact 140 is equal to the sum of the width W2 of the top surface 145 of the bit line contact 140 and twice the horizontal distance S1. The maximum width W1 of the top portion 140a of the bit line contact 140 is equal to the sum of the width W3 of the bottom surface 146 of the bit line contact 140 and twice the horizontal distance S2.

In some embodiments, the top portion 140a of the bit line contact 140 has a maximum width W1 at a vertical distance D2 from the bottom surface 146 of the bit line contact 140. That is, the vertical distance D2 is the vertical distance between the tip 142 and the bottom surface 146. The vertical distance D2 can be in the range of about 40 nanometers to about 50 nanometers (e.g., about 45 nanometers). In some embodiments, the depth D3 of the bit line contact 140 is equal to the sum of the vertical distances D1 and D2, and the depth D3 can be in the range of about 50 nanometers to about 70 nanometers (e.g., about 60 nanometers or 65 nanometers). If the depth D3 falls within the above range, it helps to increase the tensile stress of the bit line contact 140, thereby increasing the electron mobility.

In some embodiments, the aspect ratio of the bit line contact 140 (i.e., the ratio of depth D3 to maximum width W1) is in the range of about 1.25 to about 1.75 (e.g., about 1.5). If the aspect ratio of the bit line contact 140 falls within the above range, it helps to increase the tensile stress of the bit line contact 140, thereby increasing the electron mobility; if the aspect ratio of the bit line contact 140 is not in the above range, there may be excessively high impedance between the bit line contact 140 and the bit line 150 or insufficient tensile stress of the bit line contact 140, resulting in a slow electron mobility.

The character line 130 is entirely located within the active region 120. In other words, the character line 130 extends downwards from the top surface 121 of the active region 120, and the top surface 131 of the character line 130 is substantially coplanar with the top surface 121 of the active region 120. The bit line contact 140 is entirely located within the active region 120. In other words, the bit line contact 140 extends downwards from the top surface 121 of the active region 120, and the top surface 145 of the bit line contact 140 is substantially coplanar with the top surface 121 of the active region 120. The bit line contact 140 and the character line 130 are separated by the active region 120. The bit line contact 140 can be a conductive contact made of metal, doped polysilicon, or other suitable materials. In some embodiments, the top surface 121 of the active area 120, the top surface 131 of the character line 130, and the top surface 145 of the bit line contact 140 are substantially coplanar (i.e., located at the same horizontal position). In some embodiments, the bottom surface 146 of the bit line contact 140 is located above the bottom surface (or lowest point) of the character line 130.

Bit line 150 is disposed above active area 120, and bit line 150 contacts bit line contact 140 and active area 120. Bit line 150 is electrically connected to bit line contact 140. Bit line 150 completely covers the top surface 145 of bit line contact 140. Specifically, the vertical projection length of bit line 150 on the bottom surface 123 of active area 120 is greater than the vertical projection length of bit line contact 140 on the bottom surface 123 of active area 120.

In some embodiments, the semiconductor structure 10 further includes an isolation structure 160. The isolation structure 160 is disposed on the semiconductor substrate 110 and surrounds the active region 120. As shown in Figure 1, a bit line contact 140 is located between the isolation structure 160 and the word line 130.

In some embodiments, the semiconductor structure 10 further includes a capacitive contact 170, a connecting pad 180, and a capacitor 190. Specifically, the capacitive contact 170 is disposed in the active region 120 and adjacent to the word line 130. The word line 130 is located between the bit line contact 140 and the capacitive contact 170. The word line 130, bit line contact 140, and capacitive contact 170 are separated from each other. Specifically, the bit line contact 140 and the word line 130 are separated by the active region 120, and the word line 130 and the capacitive contact 170 are separated by the active region 120. The connecting pad 180 is disposed above the active region 120 and contacts the capacitive contact 170. The top surface of the connector pad 180 is above the top surface of the bit line 150, and the bottom surface of the connector pad 180 is substantially coplanar with the bottom surface of the bit line. A capacitor 190 is disposed on and in contact with the connector pad 180. In some embodiments, the semiconductor structure 10 is dynamic random access memory (DRAM), wherein capacitor contact 170 is configured to provide an electrical connection between capacitor 190 and active region 120.

In some embodiments, current I flows from bit line 150 sequentially through bit line contact 140, active region 120 and capacitor contact 170, and through connecting pad 180 to capacitor 190. By improving the structure of bit line contact 140, tensile stress can be increased, thereby increasing electron mobility.

In some embodiments, the top surface 145 of the bit line contact 140, the top surface 131 of the word line 130, and the top surface 171 of the capacitor contact 170 are substantially coplanar. A connecting pad 180 partially covers the top surface 171 of the capacitor contact 170. Specifically, the vertical projection length of the connecting pad 180 onto the bottom surface 123 of the active region 120 is less than the vertical projection length of the capacitor contact 170 onto the bottom surface 123 of the active region 120.

In some embodiments, as shown in Figure 2 (top view), bit lines 150 extend along a first direction, and character lines 130 extend along a second direction, wherein the first direction is perpendicular to the second direction. The active area 120 extends obliquely to either the first or second direction. The active area 120 surrounds the bit line contact 140, and the bit line contact 140 is disposed between the two character lines 130. In Figure 2, the active area 120 has an elliptical outline, the character lines 130 and bit lines 150 have strip-shaped (or straight) outlines, the bit line contact 140 has a circular outline, and the connecting pad 180 has a rectangular (or square) outline. It is worth noting that Figure 2 is a top view of the layout of the semiconductor structure 10, and shows the active area 120, word line 130, bit line contact 140, bit line 150 and connection pad 180. For clarity, the isolation structure 160, capacitor contact 170 and capacitor 190 are omitted in Figure 2 and are shown in Figure 1.

Figures 4 through 8 are cross-sectional views of methods for forming the semiconductor structure 10 of Figure 1 at different stages according to some embodiments disclosed herein.

Referring to Figure 4, a semiconductor substrate 110 is provided. In some embodiments, the semiconductor substrate 110 comprises silicon. In some other embodiments, the semiconductor substrate 110 comprises semiconductors of other elements, such as germanium; compound semiconductors comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or combinations thereof.

Active region 120 is formed on semiconductor substrate 110. In some embodiments, active region 120 includes P-type dopants, such as boron (B), _BF2 , _BF3 , or combinations thereof. In some other embodiments, active region 120 includes N-type dopants, such as phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof.

An isolation structure 160 is formed to surround the active region 120. In some embodiments, the isolation structure 160 is a shallow trench isolation. The isolation structure 160 may contain an insulating material, such as silicon dioxide. In some embodiments, the isolation structure 160 is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or similar methods.

Character lines 130 are formed in the active region 120. Forming character lines 130 may involve first forming a trench in the active region 120, and then filling the trench with a conductive material to form character lines 130. Character lines 130 may contain a metal (e.g., tungsten) or other suitable conductive material. Capacitive contacts 170 are formed in the active region 120. Forming capacitive contacts 170 may involve first forming a trench in the active region 120, and then filling the trench with a conductive material to form capacitive contacts 170. Capacitive contacts 170 may be conductive contacts of a metal, metal compound, or other suitable conductive material.

A mask 210 is formed on the active region 120 and the isolation structure 160. Forming the mask 210 may include first depositing a mask layer on the active region 120 and the isolation structure 160, and then patterning the mask layer to form the mask 210. The mask 210 exposes a portion of the active region 120. Then, using the mask 210 as an etching mask, a first etching process E1 is performed to form a groove 220 in the active region 120, wherein the groove 220 has sidewalls that extend continuously downward from the sidewalls of the mask 210. In some embodiments, the first etching process E1 is a dry etching process. For example, a dry etching gas, such as hydrogen bromide (HBr) or other suitable dry etching gases, can be selected for the dry etching process. In some embodiments, the groove 220 has a first depth d1 in the range of about 25 nanometers to about 35 nanometers (e.g., about 30 nanometers).

Referring to Figures 4 and 5, using the same mask 210 as the etching mask, a second etching process E2 is performed after the first etching process E1 to laterally expand the groove 220. At this time, the groove 220 can have a maximum width W1 in the range of approximately 70 nanometers to approximately 110 nanometers (e.g., approximately 90 nanometers). The groove 220 has a first sidewall 221 and a second sidewall 223 connecting the first sidewall 221, and the first sidewall 221 and the second sidewall 223 form an angle θ. The angle θ can be in the range of approximately 100 degrees to approximately 120 degrees (e.g., approximately 110 degrees). If the angle θ falls within the aforementioned range, it helps to increase the tensile stress of the subsequently formed bit line contact 140 (see Figure 1), thereby increasing the electron mobility. In some embodiments, the first sidewall 221 and the second sidewall 223 are linear sidewalls. In some embodiments, the first sidewall 221 and the second sidewall 223 are inclined sidewalls, and the first sidewall 221 and the second sidewall 223 are inclined in different directions.

In some embodiments, the second etching process E2 further deepens the groove 220. Specifically, the groove 220 in Figure 5 has a second depth d2, and the second depth d2 is greater than the first depth d1. The second depth d2 can be in the range of about 40 nanometers to 50 nanometers (e.g., about 45 nanometers). In some embodiments, the ratio of the second depth d2 to the first depth d1 can be in the range of about 1.2 to about 2 (e.g., about 1.5). In some embodiments, performing the second etching process E2 causes the groove 220 to have a polygonal cross-sectional profile, such as a hexagonal cross-sectional profile.

In some embodiments, the second etching process E2 is a wet etching process. The second etching process E2 can be performed using an alkaline etching solution, such as tetramethyl ammonium hydroxide (TMAH), ammonium hydroxide ( _NH₄OH ), or other suitable wet etching solutions. The concentration of the etching solution in the second etching process E2 can range from about 2% to about 5% (e.g., 2.5%, 3%, 3.5%, 4%, or 4.5%). If the concentration of the etching solution falls within the above range, it helps to increase the tensile stress of the subsequently formed bit line contact 140 (see Figure 1), thereby increasing electron mobility. If the concentration of the etching solution is greater than 5%, the width of the groove 220 may be too large. If the concentration of the etching solution is less than 2%, the width of the groove 220 may be too small to improve the tensile stress of the subsequently formed bit line contact 140 (see Figure 1).

In some implementations, the second etching process E2 comprises multiple etching processes. For example, the second etching process E2 includes three sequentially performed wet etching processes: a wet etching process using dilute hydrofluoric acid (dHF) as the etching solution, a wet etching process using TMAH as the etching solution, and a wet etching process using deionized water as the etching solution. In wet etching processes using diluted hydrofluoric acid as the etching solution, the ratio of water to hydrofluoric acid in the diluted hydrofluoric acid can be in the range of about 150 to about 250 (e.g., about 200), the process temperature can be in the range of about 20 degrees Celsius to 30 degrees Celsius (e.g., about 25 degrees Celsius), and the process time can be in the range of about 30 seconds to about 90 seconds (e.g., about 60 seconds). In wet etching processes using TMAH as the etching solution, the concentration of TMAH can range from about 2% to about 5% (e.g., 2.35%, 2.5%, 3%, 3.5%, 4%, or 4.5%), the process temperature can range from about 20°C to about 30°C (e.g., about 25°C), and the process time can range from about 90 seconds to about 150 seconds (e.g., about 120 seconds). In some embodiments, the process time of wet etching processes using TMAH as the etching solution is longer than that of wet etching processes using diluted hydrofluoric acid as the etching solution.

Referring to Figures 4, 5, and 6, using the same mask 210 as the etching mask, a third etching process E3 is performed after the second etching process E2 to deepen the groove 220. At this time, the groove 220 may have a third depth d3 in the range of approximately 50 nanometers to approximately 70 nanometers (e.g., approximately 60 nanometers or 65 nanometers). The third depth d3 of the groove 220 is the same as the depth D3 of the bit line contact 140 subsequently filled with conductive material (see Figure 3). If the third depth d3 falls within the above range, it helps to increase the tensile stress of the subsequently formed bit line contact 140 (see Figure 3), thereby increasing the electron mobility. In some embodiments, the ratio of the third depth d3 of the groove 220 in Figure 6 to the first depth d1 of the groove 220 in Figure 4 is in the range of about 1.5 to about 2. For example, the third depth d3 of the groove 220 in Figure 6 is about 60 nanometers and the first depth d1 of the groove 220 in Figure 4 is about 30 nanometers, and the ratio of the third depth d3 to the first depth d1 is 2.

As shown in Figure 6, performing the third etching process E3 causes the groove 220 to extend toward the bottom surface 123 of the active region 120. More specifically, the groove 220 further has a third sidewall 225 connecting to the second sidewall 223. That is, the second sidewall 223 extends continuously downward from the first sidewall 221, and the third sidewall 225 extends continuously downward from the second sidewall 223. In some embodiments, the depth d4 of the groove 220 during the third etching process E3 is in the range of approximately 15 nanometers to approximately 25 nanometers (e.g., approximately 20 nanometers), where the depth d4 is the difference between the third depth d3 and the first depth d1.

In some embodiments, the third etching process E3 is a dry etching process. For example, a dry etching gas, such as hydrogen bromide (HBr) or other suitable dry etching gases, can be selected for the dry etching process. In some embodiments, the first etching process E1 and the third etching process E3 use the same etching gas.

Referring to Figures 6 and 7, conductive material is filled into the groove 220 to form a bit line contact 140 in the active region 120. Because the bit line contact 140 fills the groove 220, the bit line contact 140 inherits the contour of the groove 220. In some embodiments, the bit line contact 140 includes a portion 148 located above the top surface 121 of the active region 120.

In some embodiments, the bit line contact 140 comprises polycrystalline silicon, a metal, or other suitable conductive material. In some embodiments, the bit line contact 140 comprises dopants including N-type dopants, phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. For example, the bit line contact 140 is made of phosphorus-doped polycrystalline silicon. The bit line contact 140 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

Referring to Figures 7 and 8, mask 210 is removed. For example, if mask 210 is photoresist, it is peeled off by ashing. In some embodiments, a planarization process (e.g., chemical mechanical polishing) is performed to remove portion 148 of bitline contact 140, such that the top surface 145 of bitline contact 140 is substantially coplanar with the top surface 121 of active region 120. At this time, bitline contact 140 includes a top portion 140a and a bottom portion 140b. The structure of bitline contact 140 has been described in detail in Figures 1 and 3, and will not be repeated here.

In some embodiments, the character line 130 and/or the capacitive contact 170 are formed before the bit line contact 140 is formed, but this disclosure is not limited thereto. That is, in some other embodiments, the character line 130 and/or the capacitive contact 170 are formed after the bit line contact 140 is formed.

Returning to Figure 1, after forming bit line contacts 140, word lines 130, and/or capacitor contacts 170, bit line 150 is formed on the active region 120 and electrically connected to bit line contacts 140, and a connection pad 180 is formed on the active region 120 and electrically connected to capacitor contacts 170. Next, capacitor 190 is formed on the connection pad 180 and electrically connected to the connection pad 180. Thus, the semiconductor structure 10 shown in Figure 1 can be obtained.

In summary, the bit line contact disclosed herein includes a top portion and a bottom portion. The top portion has a first sidewall and a second sidewall connected to the first sidewall, and the first sidewall and the second sidewall form an angle, which can increase the volume of the bit line contact and increase the tensile stress, thereby increasing the electron mobility. Therefore, the performance of the semiconductor structure can be improved.

Although this disclosure has been made in practice as described above, it is not intended to limit this disclosure. Anyone skilled in this art may make various modifications and alterations without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope of the attached patent application.

10: Semiconductor Structure 110: Semiconductor Substrate 120: Active Region 121: Top Surface 123: Bottom Surface 130: Character Line 131: Top Surface 140: Bit Line Contact 140a: Top Portion 140b: Bottom Portion 141: First Sidewall 142: Tip 143: Second Sidewall 144: Sidewall 145: Top Surface 146: Bottom Surface 148: Portion 150: Bit Line 160: Isolation Structure 170: Capacitor Contact 171: Top Surface 180: Connector Pad 190: Capacitor 210: Mask 220: Groove 221: First sidewall 223: Second sidewall 225: Third sidewall D1: Vertical distance D2: Vertical distance D3: Depth d1: First depth d2: Second depth d3: Third depth d4: Depth E1: First etching process E2: Second etching process E3: Third etching process I: Current R: Area S1: Horizontal distance S2: Horizontal distance W1: Maximum width W2: Width W3: Width A-A: Line θ: Angle

To make the above and other objects, features, advantages, and embodiments of this disclosure more apparent, the accompanying drawings are explained as follows: Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments of this disclosure. Figure 2 is a top view of the layout of the semiconductor structure in Figure 1. Figure 3 is a partial enlarged view of a region in Figure 1. Figures 4 to 8 are cross-sectional views of methods for forming semiconductor structures at different stages according to some embodiments of this disclosure.

Domestic Storage Information (Please record in order of storage institution, date, and number) None International Storage Information (Please record in order of storage country, institution, date, and number) None

10: Semiconductor Structure

110: Semiconductor substrate

120: Active Zone

121: Top surface

123: Bottom surface

130: Character Line

131: Top surface

140: Bit line contact

140a: Top section

140b: Bottom section

141: First side wall

143: Second side wall

145: Top surface

146: Bottom

150: Bitline

160: Isolation Structure

170: Capacitor Contact

171: Top surface

180: Connecting Pad

190: Capacitor

I: Current

R: Region

Claims (6)

A method for forming a semiconductor structure includes: forming an active region on a semiconductor substrate; performing a first etching process to form a groove in the active region; performing a second etching process to laterally expand the groove, such that the groove has a first sidewall and a second sidewall connected to the first sidewall, and the first sidewall and the second sidewall form an angle, wherein the angle is in the range of 100 degrees to 120 degrees and the angle is directed toward the center of the groove; filling a conductive material into the groove to form a bit line contact in the active region; forming a bit line on the active region and electrically connecting the bit line contact; and A character line is formed in the active area, wherein the character line is adjacent to the bit line in contact, and wherein a top surface of the bit line in contact with the top surface of the character line is substantially coplanar. The method as described in claim 1 further includes: performing a third etching process to deepen the groove, such that the groove further has a third sidewall extending downward from the second sidewall. The method as described in claim 2, wherein the second etching process is a wet etching process and the third etching process is a dry etching process. The method described in claim 1, wherein the second etching process is performed to deepen the groove. A method for forming a semiconductor structure includes: forming an active region on a semiconductor substrate; performing a first etching process to form a groove in the active region, wherein the first etching process causes the groove to have a first depth; performing a second etching process to laterally expand the groove, such that the groove has a first sidewall and a second sidewall connecting the first sidewall; performing a third etching process to deepen the groove, such that the groove further has a third sidewall extending downward from the second sidewall, wherein the third etching process causes the groove to have a second depth, the ratio of the second depth to the first depth being in the range of 1.5 to 2.5; and filling a conductive material into the groove to form a bit line contact in the active region. A bit line is formed on the active region and electrically connected to the bit line contact; and a word line is formed in the active region, wherein the word line is adjacent to the bit line contact, and wherein a top surface of the bit line contact is substantially coplanar with a top surface of the word line. The method described in claim 5, wherein the same etching mask is used to perform the first etching process, the second etching process, and the third etching process.