TWI913750B - Manufacturing method of semiconductor structure - Google Patents

Abstract

A manufacturing method of semiconductor structure includes forming a second dielectric layer on a first dielectric layer; forming a patterned hard mask layer on the second dielectric layer, in which the hard mask layer has a plurality of openings; etching the first dielectric layer and the second dielectric layer under the openings to form a plurality of trenches and a higher edge area; depositing a metal layer on a sidewall of the first dielectric layer, a sidewall of the second dielectric layer and a sidewall and a top surface of the hard mask layer; and performing a chemical-mechanical polishing to grind the metal layer and the hard mask layer, in which the chemical-mechanical polishing has a high selectivity between the hard mask layer and the second dielectric layer.

Description

Semiconductor structure manufacturing method

This disclosure relates to a method for manufacturing a semiconductor structure.

With each generation of advancements, memory has become smaller and smaller. However, existing manufacturing processes are prone to inadequacies due to the reduction in critical dimensions. This is because the processes used to manufacture memory cells often excessively etch the top electrode plate and the underlying dielectric layer used to deposit the capacitors. Consequently, at critical dimensions, the capacitors are prone to bending or having excessively wide cross-sections, leading to contact and short circuits.

One of the technical features disclosed herein is a method for manufacturing a semiconductor structure.

According to some embodiments of this disclosure, a method for manufacturing a semiconductor structure includes forming a second dielectric layer on a first dielectric layer; forming a patterned hard mask layer on the second dielectric layer, wherein the hard mask layer has a plurality of openings; etching the first dielectric layer and the second dielectric layer below the openings; and etching the sidewalls of the first dielectric layer, the sidewalls of the second dielectric layer, and the hard mask layer. A metal layer is deposited on the sidewalls and top surface of the mask layer; after depositing metal layers on the sidewalls of the first dielectric layer, the second dielectric layer, and the sidewalls and top surface of the hard mask layer, an oxide layer is deposited along the metal layers; and the metal layers and the hard mask layer are polished using a chemical mechanical planarization method, wherein the chemical mechanical planarization method has a high selectivity for the hard mask layer and the second dielectric layer.

In some embodiments, the first and second dielectric layers below the opening are etched to form a plurality of holes and a higher edge region.

In some embodiments, polishing the metal layer and the hard mask layer by chemical mechanical planarization further includes polishing the hard mask layer with a hard polishing pad so that the distance between the top surface of a remaining portion of the hard mask layer and the interface between the second dielectric layer and the hard mask layer is less than 50 nanometers.

In some embodiments, grinding the metal layer and the hard mask layer with chemical mechanical planarization further includes grinding the remaining portion of the hard mask layer with a soft polishing pad after grinding the hard mask layer with a hard polishing pad.

In some embodiments, the selection ratio of the hard masking layer and the second dielectric layer is greater for soft polishing pads than for hard polishing pads.

In some embodiments, the semiconductor structure manufacturing method further includes polishing the metal layer and hard mask layer using a chemical mechanical planarization method, and then using a polishing rate monitor to monitor the polishing endpoint.

In some implementations, the metal layer and hard mask layer are polished using chemical mechanical planarization, which also includes polishing the oxide layer.

In some embodiments, depositing an oxide layer along a metal layer includes depositing an oxide layer by atomic layer deposition.

In some embodiments, the semiconductor structure manufacturing method further includes removing the oxide layer after polishing the metal layer and the hard mask layer using a chemical mechanical planarization method.

In some implementations, oxide removal involves using wet cleaning methods to remove the oxide layer.

In the above-disclosed embodiment, since the dry etching method traditionally used to remove the hard mask layer is replaced by chemical mechanical polishing, and this chemical mechanical planarization method has a high selectivity for the hard mask layer and the second dielectric layer, over-etching will not occur, and thus the capacitor short circuit caused by over-etching can be avoided.

The embodiments disclosed below provide numerous different embodiments, or examples, for implementing the various features of the provided object. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and/or letters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself specify the relationship between the various embodiments and/or configurations discussed.

Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.

Figure 1 illustrates a flowchart of a method for manufacturing a semiconductor structure according to one embodiment of this disclosure. Referring to Figure 1, the method for manufacturing the semiconductor structure includes the following steps: firstly, in step S1, a second dielectric layer is formed on a first dielectric layer; then, in step S2, a patterned hard mask layer is formed on the second dielectric layer, wherein the hard mask layer has a plurality of openings; then, in step S3, the first dielectric layer and the second dielectric layer below the openings are etched. To form a plurality of holes and a higher edge region; then in step S4, a metal layer is deposited on the sidewalls of the first dielectric layer, the sidewalls of the second dielectric layer, and the sidewalls and top surface of the hard mask layer; finally in step S5, the metal layer and the hard mask layer are polished by chemical mechanical planarization, wherein the chemical mechanical planarization has a high selectivity for the hard mask layer and the second dielectric layer.

In some embodiments, the method of manufacturing the semiconductor structure is not limited to steps S1 to S5 described above. For example, each of steps S1 to S5 may include other more detailed steps. In some embodiments, steps S1 to S5 may further include other steps between two preceding and following steps, or may include other steps before step S1 and after step S5. The above steps will be described in detail in the following description.

Figures 2 through 8 illustrate cross-sectional views of the intermediate stage of the semiconductor structure fabrication method of Figure 1. Referring to Figure 2, the semiconductor structure fabrication method includes forming a second dielectric layer 120 on a first dielectric layer 110. The first dielectric layer 110 may contain silicon oxide or any suitable material, and the second dielectric layer 120 may contain silicon nitride or any suitable material. Below the first dielectric layer 110, there may be another dielectric layer 140, which may contain silicon nitride. Next, a patterned hard mask layer 130 is formed on the second dielectric layer 120, wherein the hard mask layer 130 has a plurality of openings 132. The hard mask layer 130 may contain polysilicon or other suitable materials. After the hard mask layer 130 is formed to cover the second dielectric layer 120, the hard mask layer 130 is further patterned to form a plurality of openings 132. The openings 132 may be formed by dry etching or other similar methods.

Referring to Figure 3, the second dielectric layer 120, the first dielectric layer 110, and the dielectric layer 140 below the opening 132 are then etched to form a plurality of holes 112. That is, the holes 112 penetrate the first dielectric layer 110 and the second dielectric layer 120. The etching of the first dielectric layer 110 and the second dielectric layer 120 can include dry etching or other suitable methods. At this point, since the hard mask layer 130 of the edge region 134 is not etched, there is a relatively high surface area.

Referring to Figure 4, a metal layer 150 is then deposited on the sidewalls of dielectric layer 140, the sidewalls of the first dielectric layer 110, the sidewalls of the second dielectric layer 120, and the sidewalls and top surface of the hard mask layer 130. That is, the metal layer 150 is formed along the sidewalls of the via 112 and the top surface of the hard mask layer 130. The material of the metal layer 150 can include titanium silicon nitride (TiSiN), titanium nitride (TiN), a combination thereof, or other suitable materials. In this step, the metal layer 150 is also formed on the upper surface of the edge region 134. The metal layer 150 will form the capacitance of the memory cell in subsequent processes. In some embodiments, the capacitor formation step also involves filling the vias 112 with a high-k dielectric material. Since the metal layer 150 is deposited after the vias 112 are formed, it can prevent the metal layers 150 between adjacent vias 112 from coming into contact and causing a short circuit after the process is completed.

Referring to Figure 5, an oxide layer 160 is then deposited along the metal layer 150. The oxide layer 160 may contain silicon oxide and can be formed using atomic layer deposition (ALD) or a similar method. In this step, the oxide layer 160 is also formed on the upper surface of the edge region 134. The formation of the oxide layer 160 is primarily to protect the metal layer 150, reducing the aperture of the holes 112, making it less likely for tiny particles easily generated during the subsequent chemical mechanical planarization process to fall into the holes 112, thus preventing damage to the metal layer 150 during the subsequent chemical mechanical planarization process.

Referring to Figure 6, the metal layer 150, oxide layer 160, and hard mask layer 130 are then polished using Chemical-Mechanical Polishing (CMP), where CMP has a high selectivity for the hard mask layer 130 and the second dielectric layer 120. In this embodiment, the semiconductor structure fabrication method further includes measuring the position of the interface 122 (see Figure 5) between the second dielectric layer 120 and the hard mask layer 130 using a metrology instrument. This step involves monitoring the end point detection (EPD) using an in-situ rate monitor (ISRM). The polishing rate monitor controls the rate of chemical mechanical polishing and detects the interface 122 between the second dielectric layer 120 and the hard mask layer 130 to determine when to stop polishing. The chemical mechanical planarization process initially uses a hard pad, which offers better planarization properties. Therefore, initially, only the higher edge region 134 of the hard mask layer 130 is extensively polished. Polishing the hard mask layer 130 with a hard pad continues until the distance D between the top surface of the remaining portion of the hard mask layer 130 and the interface 122 is less than 50 nanometers.

Referring to Figure 7, when the distance D (see Figure 6) between the top surface of the remaining portion of the hard mask layer 130 and the interface 122 is less than 50 nanometers, the polishing endpoint monitored by the polishing rate monitor is approaching. At this point, the thickness of the hard mask layer 130 outside the edge region 134 will be much less than 50 nanometers, and in some embodiments, the hard mask layer 130 outside the edge region 134 will be almost completely polished due to overpolishing. Since the second dielectric layer 120 serves as the upper electrode of the capacitor (i.e., the polished metal layer 150), it must not be overpolished during chemical mechanical planarization. To avoid over-polishing the second dielectric layer 120, after polishing the hard mask layer 130 with a hard polishing pad until the distance D between the top surface of the remaining portion of the hard mask layer 130 and the interface 122 is less than 50 nanometers, a soft polishing pad will be used to polish the remaining portion of the hard mask layer 130. The selection ratio of the hard mask layer 130 and the second dielectric layer 120 is greater with the soft polishing pad than with the hard polishing pad. In some embodiments, the selection ratio of the hard masking layer 130 and the second dielectric layer 120 of the hard polishing pad is approximately in the range of 10:1 to 15:1, while the selection ratio of the hard masking layer 130 and the second dielectric layer 120 of the soft polishing pad is approximately in the range of 30:1 to 70:1.

Because the soft polishing pad has a higher selectivity for the hard mask layer 130 and the second dielectric layer 120 compared to the hard polishing pad, it does not excessively damage the exposed second dielectric layer 120 during polishing. This allows for a longer polishing time, effectively removing the remaining hard mask layer 130 (mostly in the higher edge region 134). Throughout the polishing process, because the oxide layer 160 covers the metal layer 150, even if tiny particles generated by chemical mechanical planarization fall into the holes 112, these particles only contact the oxide layer 160 and not the metal layer 150. In this way, the presence of the oxide layer 160 effectively protects the metal layer 150 from damage caused by chemical mechanical planarization.

Referring to Figure 8, next, after polishing the metal layer 150, oxide layer 160, and hard mask layer 130 using chemical mechanical planarization, the remaining oxide layer 160 is removed _. This step may include removing the oxide layer 160 using wet cleaning. The solution used for wet cleaning may include sulfuric acid ( _H₂SO₄ ), hydrogen _peroxide ( _H₂O₂ ), or a mixture thereof or a similar solution. In this step, the fine particles that are easily generated during the aforementioned chemical mechanical planarization process are also removed, leaving the complete metal layer 150.

In summary, by replacing the traditional dry etching method used to remove the hard mask layer with chemical mechanical polishing (CMP), and because CMP has a high selectivity for both the hard mask layer and the second dielectric layer, over-etching is avoided, thus preventing capacitor short circuits caused by over-etching. Furthermore, a metal layer and an oxide layer are deposited before CMP, and the oxide layer also protects the metal layer, preventing particles from falling into the holes and damaging it during CMP.

The foregoing outlines the characteristics of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them without departing from the spirit and scope of this disclosure.

110: First dielectric layer 112: Hole 120: Second dielectric layer 122: Interface 130: Hard mask layer 132: Opening 134: Edge region 140: Dielectric layer 150: Metal layer 160: Oxide layer D: Distance S1, S2, S3, S4, S5: Steps

When read in conjunction with the accompanying figures, the form of this disclosure can be best understood from the embodiments described below. Note that, according to standard practice in this industry, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased at will for clarity of explanation. Figure 1 illustrates a flowchart of a method for manufacturing a semiconductor structure according to one embodiment of this disclosure. Figures 2 through 8 illustrate cross-sectional views of the manufacturing process of the semiconductor structure of Figure 1 at intermediate stages.

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S1, S2, S3, S4, S5: Steps

Claims (10)

A method for manufacturing a semiconductor structure includes: forming a second dielectric layer on a first dielectric layer; forming a patterned hard mask layer on the second dielectric layer, wherein the hard mask layer has a plurality of openings; etching the first dielectric layer and the second dielectric layer beneath the openings; depositing a metal layer on the sidewalls of the first dielectric layer, the sidewalls of the second dielectric layer, and the sidewalls and top surface of the hard mask layer; after depositing the metal layer on the sidewalls of the first dielectric layer, the sidewalls of the second dielectric layer, and the sidewalls and top surface of the hard mask layer, depositing an oxide layer along the metal layer; and The metal layer and the hard mask layer are polished using a chemical mechanical planarization method, wherein the chemical mechanical planarization method has a high selectivity for the hard mask layer and the second dielectric layer. A method of manufacturing a semiconductor structure as described in claim 1, wherein the first dielectric layer and the second dielectric layer below the openings are etched to form a plurality of holes and a higher edge region. The method for manufacturing a semiconductor structure as described in claim 1, wherein polishing the metal layer and the hard mask layer using the chemical mechanical planarization method further comprises: polishing the hard mask layer using a hard polishing pad such that the distance between the top surface of a remaining portion of the hard mask layer and an interface between the second dielectric layer and the hard mask layer is less than 50 nanometers. The method for manufacturing a semiconductor structure as described in claim 3, wherein polishing the metal layer and the hard mask layer using the chemical mechanical planarization method further comprises: After polishing the hard mask layer using the hard polishing pad, polishing the remaining portion of the hard mask layer using a soft polishing pad. The method for manufacturing a semiconductor structure as described in claim 4, wherein the selection ratio of the soft polishing pad to the hard mask layer and the second dielectric layer is greater than the selection ratio of the hard polishing pad to the hard mask layer and the second dielectric layer. The method for manufacturing the semiconductor structure as described in claim 1 further comprises: After polishing the metal layer and the hard mask layer using the chemical mechanical planarization method, monitoring a polishing endpoint using a polishing rate monitor. The method for manufacturing a semiconductor structure as described in claim 1, wherein grinding the metal layer and the hard mask layer by the chemimechanical planarization method further includes grinding the oxide layer. The method of manufacturing a semiconductor structure as described in claim 1, wherein depositing the oxide layer along the metal layer comprises depositing the oxide layer by atomic layer deposition. The method for manufacturing the semiconductor structure as described in claim 1 further comprises: removing the oxide layer after grinding the metal layer and the hard mask layer using the chemical mechanical planarization method. The method of manufacturing a semiconductor structure as described in claim 9, wherein removing the oxide layer comprises removing the oxide layer using a wet cleaning method.