TWI913677B - Control circuit and control method thereof - Google Patents

Abstract

A low power consumption control circuit includes a digital circuit, an analog circuit and a reset device. The digital circuit has a standby controller. The analog circuit includes a latch device, a power regulator and an oscillator. The standby controller controls the latch device to have and lock a first value representing the standby mode. The latch device outputs the first value to turn off the power regulator and the oscillator, thereby causing the digital circuit to enter the standby mode. When the reset device outputs a reset signal to the standby controller and the latch device, the latch device outputs a second value representing the working mode to turn on the power regulator and the oscillator, and after a predetermined time, the standby controller controls the latch device to have the second value, thereby causing the digital circuit to enter the working mode.

Description

Control circuit and its control method

This invention relates to the technical field of electronic circuits, and in particular to a control circuit and control method for reducing standby power consumption.

In standby mode, electronic products that typically include both digital and analog circuits (such as display products) still require the power regulator and oscillator to continue operating in order for the digital signals of the digital circuits to properly notify the analog circuits that the integrated circuit (IC) is in standby mode. This results in continued power consumption, meaning that electronic products cannot truly save power effectively when in standby mode.

Therefore, there are still many shortcomings in the circuit design of habitual standby control, which need to be improved.

The main purpose of this invention is to provide a control circuit and control method that further reduces the standby power consumption of electronic products by shutting down the power supply device and clock device that supply the power and clock signals required for the operation of the digital circuit.

To achieve the aforementioned objectives, the present invention provides a control circuit comprising: a digital circuit operable in an operating mode or a standby mode, the digital circuit having a standby controller; an analog circuit including a latching device coupled to the standby controller, a power supply device, and a clock device, wherein the power supply device is used to supply power to the digital circuit and can be activated or deactivated by the latching device. The clock device provides a clock signal to the digital circuit and can be activated or deactivated by the latching device; and a reset device coupled to the latching device and the standby controller, wherein the standby controller controls the latching device to have and lock a first value representing a standby mode, the latching device outputs the first value to deactivate the power supply and the clock device, thereby putting the digital circuit into the standby mode.

The present invention further proposes a control method for controlling a control circuit, the control circuit including a digital circuit, an analog circuit, and a reset device. The digital circuit can operate in a working mode or a standby mode and has a standby controller. The analog circuit includes a locking device, a power supply device for supplying power to the digital circuit, and a clock device for providing a clock signal to the digital circuit. The control method includes the steps of: (A) the standby controller controlling the locking device to have a locking function. (A) The latching device outputs the first value to shut down the power supply and the clock device, thereby putting the digital circuit into the standby mode; (B) The reset device outputs a reset signal; (D) Based on the reset signal, the latching device activates the power supply and the clock device; and (E) After a predetermined time, the standby controller controls the latching device to have a second value representing the operating mode, thereby putting the digital circuit into the operating mode.

The above overview and the following detailed description are illustrative in nature and are intended to further illustrate the scope of the invention. Other purposes and advantages of the invention will be explained in the following description and drawings.

To make the purpose, technical solution, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the implementation of this invention and are not intended to limit this invention.

Figure 1 shows a schematic diagram of the control circuit of the present invention. The control circuit includes a digital circuit 10, an analog circuit 20, and a reset device 30. The present invention is applied to an electronic product to reduce the standby power consumption of the electronic product. To achieve the functions to be provided by the electronic product, the electronic product typically includes digital and analog circuits. Taking a display device as an example, Figure 2 shows the circuit structure diagram of the display device. The digital circuit in the display device... Circuit 10 may include clock, power supply, common voltage, gate, source, latch, and other circuits, while analog circuit 20 may include gate control, source control, latch control, timing control, data path, interface, and other circuits. The display function is provided by the cooperation of digital circuit 10 and analog circuit 20. It should be noted that the circuit structure diagram shown in Figure 2 above is only used to illustrate digital circuit 10 and analog circuit 20 in electronic products, and is not intended to limit the present invention.

Referring again to Figure 1, the digital circuit 10 of the control circuit of the present invention can operate in a working mode or a standby mode, and the digital circuit 10 has a standby controller 11, which has a counter 111. The analog circuit 20 of the control circuit of the present invention has a latching device 21, a power supply device 23, and a clock device 25. The power supply device 23 is used to supply power to the digital circuit 10 and can be started or stopped by the latching device 21. The clock device 25 is used to provide a clock signal to the digital circuit 10 and can be started or stopped by the latching device 21. The reset device 30 of the control circuit of the present invention is coupled to the latching device 21 and the standby controller 11.

Furthermore, the latching device 21 in the aforementioned analog circuit 20 is coupled to the standby controller 11 in the digital circuit 10. In one embodiment, the latching device 21 includes a flip-flop 211 and a logic and AND gate 213. The flip-flop 211 is, for example, a D-type flip-flop, which has a data terminal D connected to the standby controller 11, a power terminal EN connected to the standby controller 11, a status output terminal Q, and a clear terminal CN connected to the counter 111 of the standby controller 11. The logic and AND gate 213 has two input terminals I1 and I2 connected to the status output terminal Q and the reset device 30 respectively, and an output terminal OT connected to the power supply device 23 and the clock device 25. It should be noted that although the flip-flop 211 in this embodiment is illustrated using a D-type flip-flop as an example, the present invention is not limited thereto. In other embodiments, the flip-flop 211 may also be a similar flip-flop such as an SR-type, JK-type, or T-type, or a component with equivalent functions. The present invention is not limited to this embodiment. Furthermore, in other embodiments, the aforementioned logic gate 213 may also be selected to be combined with a logic reverse gate or a combination of logic reverse and gate to realize the function of the aforementioned locking device 21.

When the digital circuit 10 operates in working mode, both the power supply device 23 and the clock device 25 are activated to provide power and clock signals to the digital circuit 10 to support its normal operation. When the digital circuit 10 wants to enter standby mode, please refer to Figure 3 for the flowchart of the control method of this invention for entering standby mode. First, in step S31, the standby controller 11 controls the locking device 21 to have and lock a first value representing the standby mode. In one embodiment, the first value is 1. Specifically, the standby controller 11 can output a standby mode signal SB (step S311). In one embodiment, the active level of the standby mode signal SB is 1. The standby mode signal SB is received by the data terminal D of the flip-flop 211 (step S312) to make the locking device 21 have a first value (=1) representing the standby mode, and the standby controller 11 then outputs a state lock signal LK, wherein, in one embodiment, the active level of the state lock signal LK is 0 (active low), and the state lock signal LK is received by the enable terminal EN of the flip-flop 211 to control the locking device 21 to lock the first value (=1) representing the standby mode (step S313).

Next, in step S32, since the locking device 21 has and locks a first value (=1) representing the standby mode, the state output terminal Q of the flip-flop 211 of the locking device 21 outputs the first value (=1) of the locking device 21 to the logic and gate 213. The logic and gate 213 performs logic and calculation on this first value (=1) and the reset signal RST output by the reset device 30. Since the first value representing the standby mode is 1, and the active level of the reset signal RST is 0, The bit level is 1 (inactive) at this time. Therefore, the output of the logic and gate 213 will output the first value (=1) to turn off the power supply device 23 and the clock device 25, thereby putting the digital circuit 10 into the standby mode.

When the reset device 30 is used to return the digital circuit 10 from standby mode to working mode, please refer to Figure 4, which shows the flowchart of the control circuit leaving standby mode using the control method of the present invention. First, in step S41, the reset device 30 outputs a reset signal RST to the standby controller 11 and the latching device 21. In one embodiment, the reset device 30 may be a mobile device, such as a mobile phone, that sends and outputs a reset signal RST. The level of the reset signal RST output by the reset device 30 is 0 (active). Next, in step S42, due to the logic of the latching device 21 and the gate 213 receiving the reset signal RST with a level of 0, the device outputs... A second value (=0) is output, that is, according to the reset signal RST, the latching device 21 outputs a second value (=0) representing the working mode to activate the power supply device 23 and the clock device 25; then, in step S43, when the digital circuit 10 regains power and clock signals and starts to operate, the standby controller 11 calculates a predetermined time. Specifically, the standby controller 11 starts counting with counter 111 to a target value, and the counting time is equal to the predetermined time; then, in step S44, after the counting is completed, the counter 111 outputs a clear signal CL, wherein, in one embodiment, the active level of the clear signal CL is 1. The clear signal CL is received by the clear terminal CN of the flip-flop 211, causing the standby controller 11 to control the latch device 21 to have a second value (=0) representing the working mode, thereby enabling the digital circuit 10 to enter the working mode. Accordingly, the digital circuit 10 can successfully return from standby mode to working mode. In this embodiment, although the first value representing the standby mode is 1 and the second value representing the working mode is 0, in other embodiments, the first value representing the standby mode can also be 0, and the second value representing the working mode can also be 1. Therefore, the values in the above embodiments are not intended to limit the invention. Furthermore, in other embodiments, the active level of the reset signal can also be 1, and the active level of the clear signal CL can be 0. The above description is not intended to limit the invention.

As can be seen from the above description, the present invention uses the standby controller in the digital circuit to control the latching device in the analog circuit, so that when the digital circuit enters standby mode, the power supply device and clock device provided to the digital circuit in the analog circuit can be turned off, thereby effectively reducing the standby power consumption of electronic products.

The above embodiments are merely illustrative examples for the purpose of explanation. The scope of the rights claimed by this invention shall be based on the scope of the patent application, and not limited to the above embodiments.

10: Digital Circuit 20: Analog Circuit 30: Reset Device 11: Standby Controller 111: Counter 21: Latch Device 23: Power Supply Device 25: Clock Device 211: Shift Switch 213: Logic and Gate D: Data Terminal EN: Enable Terminal Q: Status Output Terminal CN: Clear Terminal I1, I2: Input Terminals OT: Output Terminal SB: Standby Mode Signal LK: Status Latch Signal RST: Reset Signal CL: Clear Signal S31, S311, S312, S313, S32: Steps S41, S42, S43, S44: Steps

Figure 1 shows a schematic diagram of the control circuit of the present invention. Figure 2 shows a circuit structure diagram of an electronic product as a display device. Figure 3 shows a flowchart of the control circuit entering standby mode using the control method of the present invention. Figure 4 shows a flowchart of the control circuit leaving standby mode using the control method of the present invention.

10: Digital Circuits

20: Analog Circuits

30: Reset Device

11: Standby Controller

111: Counter

21: Bolt-locking device

23: Power Supply Equipment

25: Clock Device

211: Flipper

213: Logic and Gates

D: Data terminal

EN: Enable terminal

Q: Status Output Terminal

CN: Cleanup End

I1, I2: Input terminals I2: Input terminals

OT: Output terminal

SB: Standby mode signal

LK: Status Lock Signal

RST: Reset signal

CL: Clear signal

Claims (10)

A control circuit includes: a digital circuit operable in an operating mode or a standby mode, the digital circuit having a standby controller; an analog circuit including a latching device coupled to the standby controller, a power supply device, and a clock device, wherein the power supply device is configured to supply power to the digital circuit and can be activated or deactivated by the latching device, and the clock device is configured to provide a clock signal to the digital circuit and can be activated or deactivated by the latching device; and a reset device coupled to the latching device and the standby controller, The standby controller controls the locking device to have and lock a first value representing a standby mode. The locking device outputs the first value to shut down the power supply and the clock device, thereby putting the digital circuit into standby mode. The control circuit as described in claim 1, wherein when the reset device outputs a reset signal to the standby controller and the locking device, the locking device outputs a second value representing the operating mode to activate the power supply device and the clock device, and after a predetermined time, the standby controller controls the locking device to have the second value representing the operating mode, thereby causing the digital circuit to enter the operating mode. The control circuit as described in claim 1, wherein the standby controller has a counter that, after the power supply device and the clock device are activated, the counter starts counting until the time to a target value is equal to the predetermined time, and after the counting is completed, the counter outputs a clear signal. The control circuit as described in claim 3, wherein the standby controller outputs a standby mode signal to control the latching device to have the first value representing the standby mode. The control circuit as described in claim 4, wherein the standby controller outputs a status lock signal to control the locking device to lock the first value representing the standby mode. The control circuit as described in claim 2, wherein the standby controller controls the output of a clear signal to control the latching device to have the second value representing the operating mode. The control circuit as described in claim 6, wherein the locking device includes a flip-flop having: a data terminal connected to the standby controller to receive the standby mode signal; a capability terminal connected to the standby controller to receive the status lock signal; a status output terminal for outputting a first value or a second value possessed by the locking device; and a clear terminal connected to the counter of the standby controller to receive the clear signal. The control circuit as described in claim 7, wherein the locking device further includes: a logic gate having two input terminals respectively connected to the status output terminal and the reset device, and an output terminal connected to the power supply device and the clock device. A control method for controlling a control circuit, the control circuit including a digital circuit, an analog circuit, and a reset device, the digital circuit being operable in a working mode or a standby mode and having a standby controller, the analog circuit including a latching device, a power supply device for supplying power to the digital circuit, and a clock device for providing a clock signal to the digital circuit, the control method including the steps of: (A) the standby controller controlling the latching device to have and lock a first value representing the standby mode; (B) the latching device outputting the first value to shut down the power supply device and the clock device, thereby causing the digital circuit to enter the standby mode; (C) the reset device outputting a reset signal; (D) Based on the reset signal, the latching device activates the power supply and the clock device; and (E) After a predetermined time, the standby controller controls the latching device to have a second value representing the operating mode, thereby causing the digital circuit to enter the operating mode. The control method as described in claim 9, wherein step (A) includes: the standby controller outputs a standby mode signal; based on the standby mode signal, controlling the locking device to have the first value; and the standby controller outputs a status lock signal to control the locking device to lock the first value.