TWI910992B - Semiconductor memory devices - Google Patents

Abstract

This invention provides a semiconductor memory device capable of performing erase operations on a plurality of memory blocks in parallel. The semiconductor memory device includes: a plurality of memory blocks, each having memory cells and word lines; voltage supply lines commonly grounded and electrically connected to a plurality of word lines corresponding to the plurality of memory blocks; a plurality of transistors electrically connected between the plurality of word lines and the voltage supply lines; a plurality of signal supply lines connected to the gate electrodes of the plurality of transistors; a plurality of block decoder units capable of outputting signals to any of the plurality of signal supply lines according to input signals corresponding to block addresses; and control circuitry. Each of the multiple block decoder units has a latch circuit. During the erase operation of multiple memory blocks, the control circuit overwrites the data of the multiple latch circuits corresponding to the multiple selected memory blocks.

Description

Semiconductor memory devices

This embodiment relates to a semiconductor memory device.

A semiconductor memory device is known, comprising: a plurality of memory blocks, each having a memory cell and a word line connected to the memory cell; and bit lines and source lines, all of which are electrically connected to the plurality of memory cells corresponding to the plurality of memory blocks.

A semiconductor memory device is provided that can perform erase operations on a plurality of memory blocks in parallel.

A semiconductor memory device according to an embodiment includes: a plurality of memory blocks, each having a memory cell and a character line connected to the memory cell; bit lines and source lines, all commonly electrically connected to a plurality of memory cells corresponding to the plurality of memory blocks; a first voltage supply line, all commonly electrically connected to a plurality of character lines corresponding to the plurality of memory blocks; and a plurality of first transistors, each corresponding to the plurality of memory blocks and electrically connected to... A plurality of first signal supply lines are connected between the character lines and the first voltage supply lines; a plurality of first signal supply lines are configured corresponding to a plurality of memory blocks and are respectively connected to the gate electrodes of a plurality of first transistors; a plurality of block decoder units are configured corresponding to a plurality of memory blocks and are capable of outputting signals to any of the plurality of first signal supply lines according to the input of the signal corresponding to the block address; and a control circuit that controls the plurality of block decoder units.

The plurality of block decoder units respectively include: a plurality of second transistors, which are connected in series with equal electrical polarity between the second voltage supply line and the third voltage supply line, and each has a signal corresponding to the block address input at its gate electrode; a third transistor, which is electrically connected between the plurality of second transistors and the second voltage supply line; a fourth transistor, which is electrically connected between the plurality of second transistors and the third voltage supply line; and a latch circuit, which is connected to the gate electrode of the fourth transistor.

The control circuit is configured to perform a plurality of memory block erase operations, wherein the plurality of memory block erase operations select two or more memory blocks as a plurality of selected memory blocks, and perform the erase operations on the plurality of selected memory blocks in parallel; in the plurality of memory block erase operations, before performing the erase operation, the data of the plurality of latch circuits corresponding to the plurality of selected memory blocks is overwritten.

Next, the semiconductor memory device of the embodiments will be described in detail with reference to the drawings. Furthermore, the embodiments described below are merely examples and are not intended to limit the invention.

Furthermore, when referring to "semiconductor memory device" in this specification, it sometimes means memory chip (memory die), and sometimes it means memory system containing controller chip, such as memory card or SSD. Moreover, it sometimes also refers to a device containing a mainframe computer, such as a smartphone, tablet, or personal computer. Also, in this specification, NAND flash memory is used as an example of a semiconductor memory device. However, a semiconductor memory device can also refer to memory other than NAND flash memory.

Furthermore, in this specification, when it is stated that the first component is "electrically connected" to the second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

Furthermore, in this specification, when it is said that the first component is "electrically connected" between the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is electrically connected to the third component through the first component.

Furthermore, in this specification, when referring to a circuit or the like that makes two wires "conduct", for example, it sometimes means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wires, and that the transistor or the like is in a conducting state.

[First Embodiment] [Memory System 10] Figure 1 is a schematic block diagram showing the composition of the memory system 10.

The memory system 10 performs tasks such as reading, writing, and erasing user data based on signals sent by the autonomous computer 20. The memory system 10 may be, for example, a memory card, SSD, or other system capable of storing user data. The memory system 10 includes a plurality of memory chips (MDs) storing user data, and a controller chip (CD) connected to these plurality of memory chips (MDs) and the main computer 20. The controller chip (CD) may have components such as a processor and RAM, and performs processes such as logical address to physical address conversion, bit error detection/correction, garbage collection (compression), and wear averaging.

Figure 2 is a schematic side view showing an example of the configuration of the memory system 10. Figure 3 is a schematic plan view showing the example of the configuration. For ease of explanation, some of the configuration is omitted in Figures 2 and 3.

As shown in Figure 2, the memory system 10 of this embodiment includes a mounting substrate MSB, a plurality of memory chips MD stacked on the mounting substrate MSB, and a controller chip CD stacked on the memory chips MD. A pad electrode P is provided in the area at the Y-direction end of the upper surface of the mounting substrate MSB, and other areas are connected to the lower surface of the memory chips MD via an adhesive or the like. A pad electrode P is provided in the area at the Y-direction end of the upper surface of the memory chips MD, and other areas are connected to the lower surface of other memory chips MD or controller chips CD via an adhesive or the like. A pad electrode P is provided in the area at the Y-direction end of the upper surface of the controller chip CD.

As shown in Figure 3, the mounting substrate MSB, the plurality of memory chips MD, and the controller chip CD each have a plurality of pads P arranged along the X direction. The mounting substrate MSB, the plurality of memory chips MD, and the plurality of pads P disposed on the controller chip CD are interconnected by bonding wires B.

Furthermore, the configurations shown in Figures 2 and 3 are merely illustrative, and the specific configurations can be appropriately adjusted. For example, in the examples shown in Figures 2 and 3, controller chips CD are stacked on a plurality of memory chips MD, and these components are connected by bonding wires B. In such a configuration, the plurality of memory chips MD and controller chips CD are contained in a single package. However, the controller chips CD may also be contained in a different package than the memory chips MD. Additionally, the plurality of memory chips MD and controller chips CD may also be interconnected not via bonding wires B, but via through electrodes or the like.

[Structure of Memory Die MD] Figure 4 is a schematic circuit diagram showing a portion of the structure of a memory die MD. As shown in Figure 4, the memory die MD includes memory cell arrays (MCAs) that store user data, and peripheral circuitry (PCs) connected to the MCAs.

[Composition of Memory Cell Array (MCA)] The memory cell array (MCA) has a plurality of memory blocks (BLK). Each of the plurality of memory blocks (BLK) contains a plurality of string units (SU). Each of the plurality of string units (SU) contains a plurality of memory strings (MS). One end of each of the plurality of memory strings (MS) is connected to the peripheral circuit (PC) via a bit line (BL). The other end of each of the plurality of memory strings (MS) is connected to the peripheral circuit (PC) via a common source line (SL).

A memory string (MS) has drain-side select transistors (STDT, STD) connected in series between bit line (BL) and source line (SL), multiple memory cells (MC) (memory cell transistors), and source-side select transistors (STS, STSB). Hereinafter, the drain-side select transistors (STDT, STD) and the source-side select transistors (STS, STSB) are sometimes abbreviated as select transistors (STDT, STD, STS, STSB, etc.).

A memory cell (MC) is a field-effect transistor with a semiconductor layer, a gate insulation film, and gate electrodes. The semiconductor layer functions as a channel region. The gate insulation film contains a charge storage film. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. The memory cell (MC) stores 1 bit or multiple bits of user data. Furthermore, character lines (WLs) are connected to the gate electrodes of multiple memory cells (MCs) corresponding to one memory string (MS). These character lines (WLs) are all commonly connected to all memory strings (MS) in a memory block (BLK).

Selector transistors STDT, STD, STS, and STSB are field-effect transistors with a semiconductor layer, a gate insulating film, and gate electrodes. The semiconductor layer functions as a channel region. Selector gate lines SGDT, SGD, SGS, and SGSB are connected to the gate electrodes of the selector transistors STDT, STD, STS, and STSB, respectively. On the drain side, the selector gate line SGD is configured corresponding to the serial unit SU and is commonly connected to all memory strings MS in one serial unit SU. The drain-side selector line SGDT and the source-side selector lines SGS and SGSB are commonly connected to all memory strings MS in the memory block BLK.

Figure 5 is a schematic three-dimensional view showing the composition of a portion of the memory cell array (MCA). The memory cell array (MCA) is disposed above the semiconductor substrate 100. Furthermore, a plurality of transistors (Tr) constituting a peripheral circuit (PC) are disposed on the upper surface of the semiconductor substrate 100. Each of the plurality of transistors (Tr) has: a channel region formed by a portion of the upper surface of the semiconductor substrate 100, a gate insulating film formed on the upper surface of the semiconductor substrate 100, and a gate electrode facing the channel region through the gate insulating film.

The memory cell array (MCA) has a plurality of memory blocks (BLKs) arranged in the Y direction. Furthermore, a block insulation layer (ST) such as silicon oxide ( _SiO₂ ) is provided between two adjacent memory blocks (BLKs) in the Y direction. Also, a plurality of bit lines (BLs) extending in both the X and Y directions are provided above the memory cell array (MCA).

The memory block BLK includes a plurality of conductive layers 110 arranged along the Z direction, a plurality of semiconductor pillars 120 extending along the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120 respectively.

The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of barrier conductive film such as titanium nitride (TiN) and metal film such as tungsten (W). Furthermore, the conductive layer 110 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide ( _SiO2 ), is disposed between the plurality of conductive layers 110 arranged along the Z direction.

Furthermore, one or more of the lowest conductive layers 110 serve as the gate electrodes for the source-side select gate line SGSB (FIG. 4) and the multiple source-side select transistors STSB (FIG. 4) connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

Furthermore, one or more conductive layers 110 located above it function as gate electrodes for the source-side select gate line SGS (FIG. 4) and the multiple source-side select transistors STS (FIG. 4) connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

Furthermore, the plurality of conductive layers 110 located above it function as gate electrodes for the character lines WL (FIG. 4) and the plurality of memory cells MC (FIG. 4) connected thereto. Each of the plurality of conductive layers 110 is electrically independent for each memory block BLK.

Furthermore, one or more conductive layers 110 located above it function as drain-side selectable gate lines SGD (FIG. 4) and the gate electrodes of the multiple drain-side selectable transistors STD (FIG. 4) connected thereto. The width of these multiple conductive layers 110 in the Y direction is smaller than that of the conductive layer 110 functioning as character lines WL, etc.

Furthermore, one or more conductive layers 110 located above it function as drain-side selectable gate lines (SGDT) (FIG. 4) and as gate electrodes of the multiple drain-side selectable transistors (STDT) (FIG. 4) connected thereto. The width of these multiple conductive layers 110 in the Y direction is smaller than that of the conductive layer 110 functioning as character lines (WL).

A semiconductor layer 112 is disposed below the plurality of conductive layers 110. The semiconductor layer 112 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, an insulating layer 101 such as silicon oxide ( _SiO2 ) is disposed between the semiconductor layer 112 and the conductive layers 110.

Semiconductor layer 112 functions as source line SL (Figure 4). The source line SL is, for example, commonly set for all memory blocks BLK contained in the memory cell array MCA.

Semiconductor pillars 120 are arranged in a prescribed pattern in the X and Y directions. The semiconductor pillars 120 function as channel regions for the multiple memory cells MC contained in a memory string MS (FIG. 4) and for the selection transistors STDT, STD, STS, and STSB. The semiconductor pillars 120 are, for example, semiconductor layers such as polycrystalline silicon (Si). As shown in FIG. 5, the semiconductor pillars 120 have a generally cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central portion. Furthermore, the outer peripheral surfaces of the semiconductor pillars 120 are each surrounded by conductive layers 110, facing each other.

An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the end of the bit line BL of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via contact Ch and contact Cb.

The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 may include, for example, a tunneling insulating film, a charge storage film, and a blocking insulating film deposited between the semiconductor pillar 120 and the conductive layer 110. The tunneling insulating film and the blocking insulating film may be, for example, insulating films such as silicon oxide ( _SiO₂ ). The charge storage film may be, for example, a film capable of storing charges such as silicon nitride (SiN). The tunneling insulation film, the charge storage film, and the blocking insulation film have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120, except for the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

Furthermore, the gate insulation film 130 may, for example, be a floating gate containing polycrystalline silicon with N-type or P-type impurities.

A plurality of contacts CC are connected to a plurality of conductive layers 110. The plurality of conductive layers 110 are electrically connected to a peripheral circuit PC via the plurality of contacts CC. As shown in FIG5, the plurality of contacts CC extend in the Z direction and are connected to the conductive layers 110 at their lower ends. The contacts CC may, for example, be a laminated film containing barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

Furthermore, the memory cell array MCA can also be formed with the top and bottom reversed. For example, the bit line BL can be located below the plurality of memory blocks BLK. Also, the semiconductor layer 112 can be located above the plurality of conductive layers 110.

[Operations of the Memory Array MCA] Next, the operations of the memory array MCA will be explained. This embodiment of the memory array MCA is configured to perform read, write, and erase operations.

Figure 6 is a schematic cross-sectional view used to illustrate the reading action. In the following description, the character line WL that is the object of the action is sometimes referred to as the selected character line WL _S , and the other character lines WL are referred to as the non-selected character lines WL _U.

During the readout operation, for example _, an operating voltage _VDD is supplied to the bit line BL. Also, a voltage _VSRC is supplied to the source line SL. The voltage _VSRC can be greater than or equal to the ground voltage _VSS . The operating voltage _VDD is greater than the voltage _VSRC .

Furthermore, during the readout operation, a voltage _VSG is supplied to the drain-side selective gate lines SGDT and SGD. This voltage _VSG is greater than the operating voltage _VDD . Also, the voltage difference between _VSG and the operating voltage _VDD is greater than the critical voltage of the drain-side selective transistors STDT and STD. Therefore, an electron-rich channel is formed in the channel region of the drain-side selective transistors STDT and STD to transmit the operating voltage _VDD .

Furthermore, during the readout operation, a voltage V _{_SG} is supplied to the source-side selective gate lines SGS and SGSB. This voltage V_{_SG} is greater than the voltage V_{_SRC} . Also, the voltage difference between V_{_SG} and V_{_SRC} is greater than the critical voltage of the source-side selective transistors STS and STSB. Therefore, an electron-rich channel is formed in the channel region of the source-side selective transistors STS and STSB, allowing the transmission of voltage V _{_SRC} .

Furthermore, during the read operation, the read path voltage _VREAD is supplied to the non-selected character line _WLU . The read path voltage _VREAD is greater than the operating voltage _VDD and voltage _VSRC . Also, the voltage difference between the read path voltage _VREAD and the operating voltages _VDD and _VSRC is unrelated to the data recorded in the memory cell MC and is greater than the threshold voltage of the memory cell MC. Therefore, an electron-containing channel is formed in the channel region of the non-selected memory cell MC, transmitting the operating voltage _VDD and voltage _VSRC to the selected memory cell MC.

Furthermore, during the read operation, a read voltage V_{_CGR} is supplied to the selection character line W_L _S _S. The read voltage V _{_CGR} is smaller than the read path voltage V _{_READ} . The voltage difference between the read voltage V _{_CGR} and the voltage V _{_SRC} is greater than the threshold voltage of the memory cell MC that records a portion of the data. Therefore, the memory cell MC that records a portion of the data becomes conductive. Consequently, current flows through the bit line BL connected to this memory cell MC. On the other hand, the voltage difference between the read voltage V _{_CGR} and the voltage V _{_SRC} is smaller than the threshold voltage of the memory cell MC that records a portion of the data. Therefore, the memory cell MC that records a portion of the data becomes deactivated. Therefore, current does not flow through the bit line BL connected to such a memory cell MC.

Furthermore, during the reading process, the current or voltage of each element line BL is detected by the sensing amplifier SA (described later), stored as user data, and output to the cache memory CM (described later).

Figure 7 is a schematic cross-sectional view used to illustrate the writing action.

In a write operation, for example, a voltage V_{_SRC} is supplied to the bit line BL_{_W} of the selector connected to a plurality of select memory cells MC that adjust the threshold voltage. An operating voltage V_{_DD} is supplied to the bit line BL_{_P} of the selector connected to a plurality of select memory cells MC that do not adjust the threshold voltage. Hereinafter, the selector connected to the plurality of select memory cells MC that adjust the threshold voltage is sometimes referred to as the "write memory cell MC," and the selector connected to a ...

Furthermore, during the write operation, the voltage _VSGD is supplied to the selected gate lines SGDT and SGD on the drain side.

The voltage V _{_SGD} is greater than the voltage V_{_SRC} . Furthermore, the voltage difference between V _{_SGD} and V_{_SRC} is greater than the critical voltage of the drain-side selective transistors ST_DT and ST_D. Therefore, an electron channel is formed in the channel region of the drain-side selective transistors ST_DT and ST_D connected to the bit line BL_{_W} to transmit the voltage V _{_SRC} .

On the other hand, the voltage difference between voltage _VSGD and operating voltage _VDD is smaller than the threshold voltage of the drain-side selection transistors STDT and STD. Therefore, the drain-side selection transistors STDT and STD connected to the bit line BL _P are in the off state.

Furthermore, during the write operation, a voltage V _{_SRC} is supplied to the source line SL, and a ground voltage V_{_SS} is supplied to the source-side selector lines SGS and SGSB. As a result, the source-side selector transistors STS and STSB are turned off.

Furthermore, during the write operation, the write path voltage V_{_PASS} is supplied to the non-selected character line W_L _U. The write path voltage V_{_PASS} is greater than the read path voltage V_{_READ} . Also, the voltage difference between the write path voltage V _{_PASS} and the voltage V_{_SRC} is unrelated to the data recorded in the memory cell MC and is greater than the threshold voltage of the memory cell MC. Therefore, an electron-containing channel is formed in the channel region of the non-selected memory cell MC, transmitting the voltage V _{_SRC} to the written memory cell MC.

Furthermore, during the write operation, the program voltage V _PGM is supplied to the selection character line _WLS . The program voltage V _PGM is greater than the write path voltage V _PASS .

Therefore, a voltage V _{_SRC} is supplied to the channel of the semiconductor pillar 120 connected to the bit line BL _W. A relatively large electric field is generated between the semiconductor pillar 120 and the select word line _WLS . As a result, electrons in the channel of the semiconductor pillar 120 tunnel into the charge storage membrane in the gate insulating film 130 (Figure 5). This increases the threshold voltage for writing to the memory cell MC.

On the other hand, the channel of the semiconductor pillar 120 connected to the bit line BL _P becomes electrically floating. The potential of this channel rises to approximately the write path voltage V _PASS through capacitive coupling with the non-selection word line _WLU . Between the semiconductor pillar 120 and the selection word line _WLS , only a smaller electric field than the aforementioned electric field is generated. Therefore, electrons in the channel of the semiconductor pillar 120 do not tunnel into the charge storage membrane in the gate insulating film 130 (FIG. 5). Therefore, the threshold voltage of the inhibited memory cell MC does not increase.

Figure 8 is a schematic cross-sectional view used to illustrate the erasure action.

During the erase operation, an erase voltage _VERA is supplied to the bit line BL and the source line SL. The erase voltage _VERA can be greater than or equal to _{the program voltage VPGM .}

Furthermore, during the erasure operation, a voltage V _{_SG '} is supplied to the drain-side selective gate line (SGDT). This voltage V _{_SG '} is smaller than the erasure voltage V _{_ERA}. Consequently, GIDL (Gate Induced Drain Leakage) is generated in the drain-side selective transistor (STDT), producing electron-hole pairs. Electrons then move towards the bit line (BL), and holes move towards the memory cell (MC).

Furthermore, during the erasure operation, a voltage V _{_SG} '' is supplied to the selective gate line SGD on the drain side. This voltage V_SG'' is smaller than the erasure voltage V _{_ERA} but larger than the voltage V _{_SG}'. This creates a hole-containing channel in the channel region of the selective transistor STD on the drain side, allowing holes to be transmitted to the memory cell MC side.

Furthermore, during the erasure operation, a voltage V _{_SG} is supplied to the source-side selective gate line SGSB. This generates a GIDL in the source-side selective transistor STSB, producing electron-hole pairs. Electrons then move towards the source line SL, and holes move towards the memory cell MC.

Furthermore, during the erasure process, a voltage _VSG '' is supplied to the source-side selective gate line SGS. This creates a hole-containing channel in the channel region of the source-side selective transistor STS, transmitting the hole to the memory cell MC side.

Furthermore, during the erase operation, a ground voltage _VSS is supplied to the character line WL. This allows the holes in the channels of the semiconductor pillar 120 to tunnel through the charge storage membrane in the gate insulation film 130 (Figure 5). Consequently, the critical voltage of the memory cell MC is reduced.

Figure 9 is a schematic cross-sectional view used to illustrate the erase verification action. The erase verification action is used to determine whether the erase action has been performed optimally on the memory block BLK.

The erase verification operation is performed for each string of units SU as illustrated in Figure 4. For example, in the case where the memory block BLK has 5 strings of units SU, after performing one erase operation on the memory block BLK, 5 erase verification operations corresponding to each string of units SU are performed.

The erase verification action is performed in essentially the same way as the read action.

However, during the erase verification operation, the word line WL is not supplied with the read voltage _VCGR or the read path voltage _VREAD , but rather with the erase verification voltage _VVFYEr . The erase verification voltage _VVFYEr is smaller than the read voltage _VCGR . The voltage difference between the erase verification voltage _VVFYEr and the voltage _VSRC is smaller than the threshold voltage of all memory cells MC except those in the erased state. Therefore, memory cells MC that have reached the erased state become on, and memory cells MC that have not reached the erased state become off. Therefore, current flows through the bit line BL of all memory cells MC in the corresponding memory string MS that have reached the erased state. On the other hand, no current flows through the bit lines BL of the memory cells MC that have not reached the erase state in the corresponding memory string MS.

Furthermore, during the erase verification process, the current or voltage of each bit line BL is detected by the sensing amplifier SA (described later). When the current flows through all bit lines BL or a certain number of bit lines BL, it is determined that the erase operation has been performed optimally. On the other hand, when the current does not flow through all bit lines BL or a certain number of bit lines BL, it is determined that the erase operation has not been performed optimally.

[Structure of Peripheral Circuit PC] Figure 10 is a schematic block diagram showing the structure of a peripheral circuit PC.

Furthermore, Figure 10 illustrates a plurality of control terminals, etc. These control terminals may be represented as corresponding to a high active signal (positive logic signal), a low active signal (negative logic signal), or both a high active signal and a low active signal. In Figure 10, the symbol for the control terminal corresponding to a low active signal includes an overline. In this specification, the symbol for the control terminal corresponding to a low active signal includes a slash ("/"). Furthermore, the illustration in Figure 10 is illustrative, and the specific configuration can be adjusted accordingly. For example, it is possible to set some or all of the high active signals to low active signals, or some or all of the low active signals to high active signals.

Furthermore, next to the plurality of control terminals shown in Figure 10, arrows indicating the input/output directions are illustrated. In Figure 10, control terminals marked with arrows from left to right can be used for data or other signal input from the controller die CD to the memory die MD. Control terminals marked with arrows from right to left in Figure 10 can be used for data or other signal output from the memory die MD to the controller die CD. Control terminals marked with arrows in both left and right directions in Figure 10 can be used for both data or other signal input from the controller die CD to the memory die MD and data or other signal output from the memory die MD to the controller die CD.

The peripheral circuit PC includes a column decoder RD and a sensing amplifier SA connected to the memory cell array MCA, and a cache memory CM connected to the sensing amplifier. Furthermore, the peripheral circuit PC includes a voltage generation circuit VG and a sequencer SQC. Additionally, the peripheral circuit PC includes input/output control circuits I/O, a logic circuit CTR, an address register ADR, an instruction register CMR, and a status register STR.

The column decoder RD, for example, includes: a block decoder that decodes the block address in the column address RA contained in the address data Add; and a voltage transmission circuit that, according to the output signal of the block decoder, enables a plurality of character lines WL (Figure 4) contained in one of the plurality of memory blocks BLK to conduct with a plurality of voltage supply lines (not shown). The detailed structure of the column decoder RD will be described later with reference to Figures 11 to 14.

The sensing amplifier SA has multiple sensing circuits and multiple voltage transmission circuits connected to multiple bit lines BL, as well as a data latch circuit. For example, the sensing circuits latch data ("0" or "1") based on the voltage or current of bit line BL into the data latch circuit according to a control signal from the sequencer SQC. Furthermore, the voltage transmission circuits adjust the voltage of bit line BL to "H" or "L" based on the "0" or "1" data latched in the data latch circuit, according to the control signal from the sequencer SQC. The user data Dat in the data latch circuit is output to the input/output control circuit (I/O) via the cache memory CM and the data bus DB. Furthermore, the user data Dat output from the input/output control circuit I/O is latched in the data latch circuit of the sensing amplifier SA via the data bus DB and cache memory CM.

The voltage generating circuit VG includes, for example, a boost circuit such as a charge pump circuit and a buck circuit such as a regulator. These boost and buck circuits are respectively connected to voltage supply lines supplied with the power supply voltage _VCC and the ground voltage _VSS . These voltage supply lines are, for example, connected to the pad electrode P illustrated with reference to Figures 2 and 3. The voltage generating circuit VG, for example, generates multiple operating voltages applied to the bit line BL, source line SL, word line WL, and selector gate lines SGD and SGS for read, write, and erase operations of the memory cell array MCA, according to control signals from the sequencer SQC. These operating voltages are supplied to the bit line BL, source line SL, word line WL, and selector gate lines SGDT, SGD, SGS, and SGSB via multiple voltage supply lines. The operating voltages output from the voltage supply lines are appropriately adjusted according to the control signals from the sequencer SQC. Furthermore, the voltage generating circuit VG also generates an operating voltage _VDD , which is supplied to each circuit via the voltage supply lines.

The sequencer SQC outputs internal control signals to the nematic decoder RD, the sensing amplifier module SAM, and the voltage generator circuit VG according to the instruction data Cmd input to the instruction register CMR. Furthermore, the sequencer SQC appropriately outputs the status data Stt, representing the status of the memory chip MD, to the status register STR.

Furthermore, the sequencer SQC generates a ready/busy signal and outputs it to the RY//BY terminal. The RY//BY terminal is in the "L" state, for example, during operations such as read, write, and erase that supply voltage to the memory cell array MCA; otherwise, it is in the "H" state. During the period when the RY//BY terminal is in the "L" state (busy period), access to the memory die MD is essentially disabled. During the period when the RY//BY terminal is in the "H" state (ready period), access to the memory die MD is permitted. Moreover, the RY//BY terminal is implemented, for example, by a pad P as described with reference to Figures 2 and 3.

As shown in Figure 10, the address register (ADR) is connected to the input/output control circuit (I/O) and stores the address data Add input from the I/O. The address register ADR, for example, has multiple 8-bit register rows. Each register row, for example, holds the address data Add corresponding to the internal operation being performed, such as a read, write, or erase operation.

Furthermore, the address data Add includes, for example, row address CA and column address RA. The column address RA includes, for example, the block address of a specific memory block BLK (Figure 4), the page address of a specific string unit SU and word line WL, the face address of a specific memory cell array MCA, and the chip address of a specific memory die MD.

The instruction register CMR is connected to the input/output control circuit (I/O), and instruction data Cmd is input from the I/O. When instruction data Cmd is input to the instruction register CMR, a control signal is sent to the sequencer SQC.

The status register STR is connected to the input/output control circuit (I/O) and stores status data Stt output to the I/O. The status register STR, for example, has multiple 8-bit register rows. Each register row, for example, maintains status data Stt associated with an internal operation such as read, write, or erase. Furthermore, the register row, for example, holds ready/busy information for the memory array (MCA).

The input/output control circuit (I/O) has data signal input/output terminals DQ0-DQ7, data selection signal input/output terminals DQS and /DQS, a shift register, and multiple input and output circuits respectively connected to the data signal input/output terminals DQ0-DQ7. Input circuits are, for example, comparators or other input receivers, and output circuits are, for example, OCD (Off-Chip Driver) circuits or other drivers.

The data signal input/output terminals DQ0-DQ7 and the data selection signal input/output terminals DQS and /DQS are implemented, for example, by the pad P described with reference to Figures 2 and 3. Data input through the data signal input/output terminals DQ0-DQ7 is input to the cache memory CM, the address register ADR, or the instruction register CMR according to the internal control signals from the logic circuit CTR. Similarly, data output through the data signal input/output terminals DQ0-DQ7 is output from the cache memory CM or the status register STR according to the internal control signals from the logic circuit CTR.

Signals input via data selection signal input/output terminals DQS, /DQS (e.g., data selection signals and their complementary signals) are used when data is input via data signal input/output terminals DQ0 to DQ7.

The Logic Circuit (CTR) has a plurality of external control terminals /CE, CLE, ALE, /WE, /RE, RE, and logic circuits connected to these external control terminals /CE, CLE, ALE, /WE, /RE, RE. The CTR receives external control signals from the controller chip (CD) via the external control terminals /CE, CLE, ALE, /WE, /RE, RE, and outputs internal control signals to the input/output control circuits (I/O) accordingly. In the following description, the external control terminal /CE is sometimes referred to as the "chip enable signal input terminal /CE".

Furthermore, the external control terminals /CE, CLE, ALE, /WE, /RE, and RE are implemented, for example, by the pad P illustrated with reference to Figures 2 and 3.

Signals input via the external control terminal /CE (e.g., chip enable signal) are used when selecting the memory chip MD. A memory chip MD with "L" input to the external control terminal /CE is in a state where it can perform input/output of user data Dat, instruction data Cmd, and address data Add (hereinafter sometimes referred to as "data"). A memory chip MD with "H" input to the external control terminal /CE is in a state where it cannot perform data input/output.

Signals input via the external control terminal CLE (e.g., instruction latch enable signal) are used when the instruction register CMR is used. When "H" is input to the external control terminal CLE, data input via the data signal input/output terminals DQ0 to DQ7 is stored as instruction data Cmd in the cache memory of the input/output control circuit I/O and transmitted to the instruction register CMR.

Signals input via the external control terminal ALE (e.g., address latch enable signal) are used when the address register ADR is in use. When "H" is input to the external control terminal ALE, the data input via the data signal input/output terminals DQ0 to DQ7 is stored as address data Add in the cache memory of the input/output control circuit I/O and transmitted to the address register ADR.

Furthermore, when "L" is input at either the external control terminals CLE or ALE, the data input via the data signal input/output terminals DQ0 to DQ7 is stored as user data Dat in the cache memory of the input/output control circuit (I/O). The user data Dat stored in the cache memory is then transmitted to the cache memory CM via the bus DB.

Signals input via external control terminals /WE (e.g., write enable signals) are used when data is input via data input/output terminals DQ0 to DQ7. Data input via data input/output terminals DQ0 to DQ7 is captured into a shift register within the I/O input/output control circuit during the timing of voltage rise (input signal switching) at external control terminals /WE.

Furthermore, when inputting data, external control terminals /WE can be used, or data selection signal input/output terminals DQS and /DQS can be used.

Signals input via external control terminals /RE, RE (e.g., reading the enable signal and its complementary signal) are used when outputting data via data signal input/output terminals DQ0 to DQ7.

[Structure of Column Decoder RD] Next, referring to Figures 11-14, the structure of the column decoder RD will be explained in more detail. Figures 11-14 are schematic circuit diagrams showing the structure of the column decoder RD.

As described above, the column decoder RD includes a block decoder and a voltage transmission circuit. Figure 11 shows the structure of the voltage transmission circuit XFER. Figure 12 shows the structure of the block decoder BLKD. Figure 13 shows the structure of the block decoder unit blkd. Figure 14 shows the structure of the latch circuit CBL.

[Structure of the Voltage Transmission Circuit XFER] As shown in Figure 11, the voltage transmission circuit XFER has a plurality of voltage transmission units xfer. The plurality of voltage transmission units xfer correspond to a plurality of memory blocks BLK in the memory cell array MCA. Each voltage transmission unit xfer has a plurality of transistors T _BLK . The plurality of transistors T _BLK correspond to a plurality of word lines WL in the memory block BLK. The transistors T _BLK are, for example, field-effect NMOS transistors. The drain electrode of the transistor T _BLK is connected to the word line WL. The source electrode of the transistor T _BLK is connected to the voltage supply line CG. The voltage supply line CG is connected to all voltage transmission units xfer in the voltage transmission circuit XFER. The gate electrode of transistor T _BLK is connected to the signal supply line BLKSEL. Multiple signal supply lines BLKSEL are provided corresponding to all voltage transmission units xfer. Furthermore, the signal supply line BLKSEL is connected to all transistors T _BLK in the voltage transmission unit xfer.

During read and write operations, for example, one signal supply line BLKSEL corresponding to a block address in the address register ADR (Figure 10) becomes "H" state, and the other signal supply lines BLKSEL become "L" state. For example, a specified drive voltage of positive magnitude is supplied to one signal supply line BLKSEL, and a ground voltage _VSS is supplied to the other signal supply lines BLKSEL. This turns on all word lines WL and all voltage supply lines CG in the memory block BLK corresponding to that block address. Meanwhile, all word lines WL in the other memory blocks BLK become floating.

[Composition of Block Decoder BLKD] As shown in Figure 12, the block decoder BLKD comprises: a plurality of block decoder units blkd, corresponding to a plurality of signal supply lines BLKSEL in the voltage transmission circuit XFER; a plurality of level shifters LS, connected to the output terminals (signal supply lines RDEC_SEL described later) of the plurality of block decoder units blkd, outputting signals to the signal supply lines BLKSEL; and an inverting signal generation circuit IAG, connected to the plurality of block decoder units blkd.

The block decoder unit BLKD, as shown in Figure 13, includes: a block address receiving circuit (CAR), a selection information holding circuit (CSL), and a latch circuit (CBL). When the block address input to the block decoder BLKD matches its own block address, the block address receiving circuit (CAR) enables the drain electrode of node n11 to conduct with the transistor N16 (described later). The selection information holding circuit (CSL) holds the signal information of node n11 and outputs it via the signal supply line RDEC_SEL.

The block address receiver circuit (CAR) has a plurality of transistors N11, N12, N13, N14, and N15 connected in series. Transistors N11, N12, N13, N14, and N15 are, for example, field-effect NMOS transistors. The gate electrodes of transistors N11, N12, N13, N14, and N15 are connected to address supply lines AROWA, AROOWB, AROOWC, AROOWD, and AROWE, respectively. In the following description, address supply lines AROWA, AROOWB, AROOWC, AROOWD, and AROWE are sometimes referred to as "address supply line AROW".

One end of the block address receiver circuit CAR (the drain of transistor N11) is connected to transistor P11 via node n11. Transistor P11 is, for example, a field-effect PMOS transistor. The source of transistor P11 is connected to the voltage supply line supplied with the operating voltage _VDD . The drain of transistor P11 is connected to node n11. The gate of transistor P11 is connected to the signal supply line RDEC.

The other end of the block address receiver circuit CAR (the source terminal of transistor N15) is connected to node n12 via transistor N16. Transistor N16 is, for example, a field-effect NMOS transistor. The source terminal of transistor N16 is connected to node n12. The drain terminal of transistor N16 is connected to the source terminal of transistor N15. The gate terminal of transistor N16 is connected to the signal supply line RDEC.

Transistors N17 and N18 are connected at node n12. Transistors N17 and N18 are, for example, field-effect NMOS transistors.

The source electrode of transistor N17 is connected to the voltage supply line that provides the ground voltage _VSS . The drain electrode of transistor N17 is connected to node n12. The gate electrode of transistor N17 is connected to the signal supply line ROMBAEN.

The source electrode of transistor N18 is connected to the voltage supply line that provides the ground voltage _VSS . The drain electrode of transistor N18 is connected to node n12. The gate electrode of transistor N18 is connected to node GOOD, which will be described later with reference to Figure 14.

The selection information holding circuit CSL has transistor P12 and inverter circuit INV1.

Transistor P12 is, for example, a field-effect PMOS transistor. The source electrode of transistor P12 is connected to the voltage supply line supplying the operating voltage _VDD . The drain electrode of transistor P12 is connected to node n11. The gate electrode of transistor P11 is connected to the signal supply line RDEC_SEL. Furthermore, the on-state current of transistor P12 is smaller than that of transistors N11, N12, N13, N14, N15, N16, and N18. Also, the on-state current of transistor P12 is smaller than that of transistors N11, N12, N13, N14, N15, N16, and N17.

The input terminals of inverter circuit INV1 are connected to node n11. The output terminals of inverter circuit INV1 are connected to the signal supply line RDEC_SEL.

The latch circuit CBL holds information about faulty blocks. Here, among the multiple memory blocks BLK in the memory cell array MCA, there are sometimes memory blocks BLK that cannot be used due to events such as short circuits in the wiring. In this manual, such memory blocks BLK are referred to as "faulty blocks".

The latch circuit CBL is normally in a reset state. In the reset state, node GOOD in latch circuit CBL is in the "H" state, and node BAD (Figure 14) in latch circuit CBL is in the "L" state. In the reset state, transistor N18 becomes conductive. In the latch circuit CBL corresponding to the faulty block, the setting operation described later is performed when the memory system 10 is started. This puts the latch circuit CBL into a setting state. In the setting state, node GOOD in latch circuit CBL is in the "L" state, and node BAD (Figure 14) in latch circuit CBL is in the "H" state. In the setting state, transistor N18 becomes deactivated.

The latching circuit CBL, as shown in Figure 14, includes transistors P21, P22, P23, P24, N21, N22, N23, N24, and N25. Transistors P21, P22, P23, and P24 are, for example, field-effect PMOS transistors. Transistors N21, N22, N23, N24, and N25 are, for example, field-effect NMOS transistors.

The source electrode of transistor P21 is connected to the voltage supply line that provides the operating voltage _VDD . The drain electrode of transistor P21 is connected to the source electrode of transistor P22. The gate electrode of transistor P21 is connected to the voltage supply line that provides the ground voltage _VSS .

The source electrode of transistor P22 is connected to the drain electrode of transistor P21 as described above. The drain electrode of transistor P22 is connected to node GOOD. The gate electrode of transistor P22 is connected to node BAD.

The source electrode of transistor P23 is connected to the voltage supply line that provides the operating voltage _VDD . The drain electrode of transistor P23 is connected to the source electrode of transistor P24. The gate electrode of transistor P23 is connected to the voltage supply line that provides the ground voltage _VSS .

The source electrode of transistor P24 is connected to the drain electrode of transistor P23 as described above. The drain electrode of transistor P24 is connected to node BAD. The gate electrode of transistor P24 is connected to node GOOD.

The source electrode of transistor N21 is connected to the voltage supply line that provides the ground voltage _VSS . The drain electrode of transistor N21 is connected to node GOOD. The gate electrode of transistor N21 is connected to node BAD.

The source electrode of transistor N22 is connected to the voltage supply line that provides the ground voltage _VSS . The drain electrode of transistor N22 is connected to node BAD. The gate electrode of transistor N22 is connected to node GOOD.

Furthermore, transistors P22 and N21 constitute an inverter circuit. Similarly, transistors P24 and N22 also constitute an inverter circuit. Moreover, these two inverter circuits constitute a latch circuit.

The source electrode of transistor N23 is connected to node n21. The drain electrode of transistor N23 is connected to node GOOD. The gate electrode of transistor N23 is connected to the signal supply line RST.

The source electrode of transistor N24 is connected to node n21. The drain electrode of transistor N24 is connected to node BAD. The gate electrode of transistor N24 is connected to the signal supply line SET.

The source electrode of transistor N25 is connected to the voltage supply line that provides the ground voltage _VSS . The drain electrode of transistor N25 is connected to node n21. The gate electrode of transistor N25 is connected to the signal supply line RDEC_SEL.

Furthermore, as shown in Figure 12, the signal supply lines RDEC, ROMBAEN, RST, and SET are commonly connected to all block decoder units blkd.

[Structure of the Inverting Signal Generator Circuit IAG] The inverting signal generator circuit IAG, as shown in Figure 12, has five nodes nAA, nAB, nAC, nAD, and nAE, each receiving a 5-bit address signal corresponding to each bit in a 5-bit block address. The corresponding bits from the block address are input to nodes nAA, nAB, nAC, nAD, and nAE. Hereinafter, these five nodes nAA, nAB, nAC, nAD, and nAE are sometimes referred to as "node nA".

Furthermore, the inverting signal generating circuit IAG has five inverter circuits INV3 corresponding to the five nodes nA. The input terminals of the inverter circuits INV3 are connected to the nodes nA. The inverter circuits INV3 output the inverted signal of the corresponding bit in the block address.

Furthermore, the inversion signal generating circuit IAG has 10 OR circuits COR corresponding to a 5-bit address signal and a corresponding 5-bit inversion signal. One input terminal of the OR circuit COR receives either a 5-bit address signal or a 5-bit inversion signal. The other input terminal of the OR circuit COR is connected to the signal supply line ALLBLK.

Here, the self-inverting signal generating circuit IAG typically outputs a 5-bit address signal and a corresponding 5-bit inverted signal (i.e., "L" is usually input into the signal supply line ALLBLK). Furthermore, the address supply lines AROW in the multiple block decoder units blkd are connected to the output terminals of the OR circuit COR in such a way that all bits become "H" when the block address input to the 5 nodes nA matches its own block address.

For example, in the block decoder unit blkd corresponding to block address "11101" (the second block decoder unit blkd from the top in Figure 12), the address supply lines AROWA, AROWB, AROWC, and AROWE are connected to the output terminal of the OR circuit COR corresponding to the address signal. On the other hand, the address supply line AROWD is connected to the output terminal of the OR circuit COR corresponding to the inversion signal. Therefore, when block address "11101" is input into the inversion signal generation circuit IAG, transistors N11, N12, N13, N14, and N15 (Figure 13) in the corresponding block decoder unit blkd are all turned on. On the other hand, in other decoder units blkd, at least one of transistors N11, N12, N13, N14, and N15 (Figure 13) is in the off state.

[Operation of Block Decoder BLKD] Next, the operation of the block decoder BLKD will be explained. The block decoder BLKD of this embodiment is configured to perform memory block selection, all memory block selection, setting of latch circuit CBL (Figure 14), reset, all setting, and all reset operations.

[Memory Block Selection Action] Figure 15 is a schematic waveform diagram illustrating the memory block selection action. The controller chip (CD) sets the memory chip (MD) by sending a command containing instruction data (Cmd) and address data (Add), thereby causing the memory chip (MD) to perform an action. For example, when the memory chip (MD) receives the command setting, the block decoder (BLKD) performs a memory block selection action based on the block address information contained in the address data (Add). During the memory block selection operation, from a plurality of memory block BLKs in the memory cell array (MCA), one memory block BLK corresponding to the input block address is selected as the selected memory block BLK, and the other memory block BLKs become non-selected memory block BLKs.

Before the memory block selection operation begins, the signals on the signal supply lines RDEC, ROMBAEN, SET, and RST are all in the "L" state. In this state, transistor P11 (Figure 13) is in the ON state, and transistor N16 (Figure 13) is in the OFF state. Therefore, the voltage of node n11 is charged to the operating voltage _VDD , and the signal supply line RDEC_SEL outputs "L".

At timing t101, the block decoder BLKD receives a signal from the address supply line AROW, which corresponds to the selected memory block BLK. Simultaneously, in the block address receiving circuit CAR (Figure 13) corresponding to the selected memory block BLK, transistors N11, N12, N13, N14, and N15 are all turned on. Conversely, in other block address receiving circuits CAR, at least one of transistors N11, N12, N13, N14, and N15 is turned off.

At timing t102, the signal of the signal supply line RDEC rises to the "H" state. At the same time, transistor P11 (Figure 13) becomes off and transistor N16 (Figure 13) becomes on.

Therefore, in the block decoder unit blkd corresponding to the selected memory block BLK, nodes n11 and n12 are connected to each other. When the corresponding memory block BLK is a faulty block, the latch circuit CBL contained in the block decoder unit blkd is reset. As a result, transistor N18 (Fig. 13) becomes on, and node n11 is connected to the voltage supply line supplying the ground voltage _VSS , reducing the voltage of node n11 to the ground voltage _VSS . Furthermore, when the self-signal supply line RDEC_SEL outputs "H", the signal supply line BLKSEL connected to the corresponding level shifter LS (Figure 12) also becomes "H", and multiple character lines WL and multiple voltage supply lines CG (Figure 11) in the selected memory block BLK are turned on.

On the other hand, in the block decoder unit blkd corresponding to the non-selected memory block BLK, nodes n11 and n12 are not connected to each other. Therefore, the voltage of node n11 is maintained at the operating voltage _VDD , and the output of the signal supply line RDEC_SEL is also maintained at "L".

Furthermore, even when memory block BLK is selected as a faulty block, nodes n11 and n12 in the block decoder unit blkd corresponding to the faulty block are still connected to each other. However, the latch circuit CBL contained in the block decoder unit blkd corresponding to the faulty block is in the set state. Therefore, transistor N18 (Fig. 13) is in the off state, and nodes n11 and n12 are not connected to each other. Therefore, the voltage of node n11 is maintained at the operating voltage _VDD , and the output of the signal supply line RDEC_SEL is also maintained at "L".

Furthermore, when the RDEC_SEL output is "L", node n11 is charged via transistor P12. Therefore, if the on-state current of transistor P12 is the same as that of transistors N11, N12, N13, N14, N15, N16, and N18, there is a risk that the voltage at node n11 may not be reduced to the ground voltage _VSS . Therefore, in this embodiment, as described above, the on-state current of transistor P12 is made smaller than that of transistors N11, N12, N13, N14, N15, N16, and N18.

During timing t102 to timing t103, multiple character lines WL and multiple voltage supply lines CG in the selected memory block BLK are turned on, thus enabling the read operation (described with reference to Figure 6), the write operation (described with reference to Figure 7), and the erase operation (described with reference to Figure 8). In this way, each block decoder unit blkd in the block decoder BLKD has the following function: corresponding to whether the address data Add (block address) indicates the corresponding memory block BLK, it turns on or electrically disconnects multiple character lines WL and multiple voltage supply lines CG in the corresponding memory block BLK. Furthermore, even when the latch circuit CBL is set to a state indicating, for example, that the corresponding memory block BLK is a faulty block, and the address data Add (block address) represents the corresponding memory block BLK, each decoder unit blkd maintains the multiple character lines WL and multiple voltage supply lines CG in the memory block BLK in an electrically disconnected state. That is, each decoder unit blkd has the following function: based on the state of the latch circuit CBL, it maintains the multiple character lines WL and multiple voltage supply lines CG in the corresponding memory block BLK in an electrically disconnected state.

At timing t103, the signal on the signal supply line RDEC drops to the "L" state. Simultaneously, transistor P11 (Fig. 13) becomes on, and transistor N16 (Fig. 13) becomes off. Consequently, in the block decoder unit blkd corresponding to the selected memory block BLK, node n11 is charged to the operating voltage _VDD . Furthermore, since the signal supply line RDEC_SEL outputs "L", the signal supply line BLKSEL connected to the corresponding level shifter LS (Fig. 12) also becomes "L", and the multiple character lines WL in the selected memory block BLK are electrically disconnected from the multiple voltage supply lines CG (Fig. 11).

[All Memory Block Selection Action] Figure 16 is a schematic waveform diagram illustrating the all memory block selection action. In the all memory block selection action, from among the plurality of memory block BLKs in the memory cell array MCA, all memory block BLKs except those corresponding to the latch circuit CBL in the set state are selected. In other words, in the all memory block selection action, all memory block BLKs corresponding to the latch circuit CBL in the reset state become selected memory block BLKs, and all memory block BLKs corresponding to the latch circuit CBL in the set state become non-selected memory block BLKs.

Before any memory block selection action begins, the signals on the signal supply lines RDEC, ROMBAEN, SET, and RST are all in the "L" state.

At timing t201, the signal supply line ALLBLK, as illustrated in Figure 12, is raised to "H". Simultaneously, transistors N11, N12, N13, N14, and N15 in the block address receiving circuit (CAR) (Figure 13), corresponding to all memory blocks BLK in the memory cell array MCA, are all turned on.

At timing t202, the signal of the signal supply line RDEC rises to the "H" state. At the same time, transistor P11 (Figure 13) becomes off and transistor N16 (Figure 13) becomes on.

Therefore, in the block decoder unit blkd where the latch circuit CBL is in the reset state, node n11 is connected to the voltage supply line supplying the ground voltage _VSS , and the voltage of node n11 is reduced to the ground voltage _VSS . Furthermore, when the signal supply line RDEC_SEL outputs "H", the signal supply line BLKSEL connected to the corresponding level shifter LS also becomes "H", and multiple character lines WL and multiple voltage supply lines CG in the selected memory block BLK are connected.

On the other hand, in the block decoder unit blkd where the latch circuit CBL is in the set state, the voltage supply lines of nodes n11 and n12, which are supplied with the ground voltage _VSS by transistor N18 (Figure 13), are electrically disconnected. Therefore, the voltage of node n11 is maintained at the operating voltage _VDD , and the output of the signal supply line RDEC_SEL is also maintained at "L". As a result, the multiple character lines WL in the non-selected memory block BLK are not connected to the multiple voltage supply lines CG.

During the time interval t202 to t203, multiple character lines WL and multiple voltage supply lines CG in all memory blocks BLK corresponding to the block decoder unit blkd, which is in the reset state of the latch circuit CBL, are turned on.

At timing t203, the signal on the signal supply line RDEC drops to the "L" state. Simultaneously, transistor P11 (Figure 13) becomes on, and transistor N16 (Figure 13) becomes off. Consequently, in the block decoder unit blkd, where the latch circuit CBL is in the reset state, node n11 is charged to the operating voltage _VDD . Furthermore, with the signals on the signal supply lines RDEC_SEL and BLKSEL in the "L" state, the multiple character lines WL in the selected memory block BLK are electrically disconnected from the multiple voltage supply lines CG.

[Setting Operation of Latch Circuit CBL] Figure 17 is a schematic waveform diagram illustrating the setting operation of the latch circuit CBL. During the setting operation, the latch circuit CBL contained in one of the plurality of block decoder units blkd is set to the set state.

Before the setup process begins, the signals on the signal supply lines RDEC, ROMBAEN, SET, and RST are all in the "L" state.

At timing t301, the block address corresponding to the latch circuit CBL that performs the setting action is input to the block decoder BLKD, and the signal of the address supply line AROW is switched. At the same time, in the block address receiving circuit CAR (Figure 13) corresponding to the block decoder unit blkd that performs the setting action, transistors N11, N12, N13, N14, and N15 all become in the on state.

At timing t302, the signals on the signal supply lines RDEC and ROMBAEN rise to the "H" state. At the same time, transistor P11 (Figure 13) becomes off, and transistors N16 and N17 (Figure 13) become on.

Therefore, in the block decoder unit blkd that performs the setup operation, node n11 is connected to the voltage supply line supplying the ground voltage _VSS , and the voltage of node n11 is reduced to the ground voltage _VSS . Furthermore, the signal supply line RDEC_SEL outputs "H". Also, transistor N25 (Figure 14) becomes active.

At timing t303, the signal on the SET signal supply line rises to the "H" state. Simultaneously, transistor N23 (Figure 14) becomes active. This connects node GOOD to the voltage supply line supplying ground voltage _VSS , reducing the voltage at node GOOD to ground voltage _VSS . Consequently, node GOOD becomes "L" and node BAD becomes "H". That is, the latch circuit CBL becomes set.

Furthermore, in the reset state, node GOOD is charged via transistors P21 and P22. Therefore, when the conduction current of transistors P21 and P22 is the same as that of transistors N23 and N25, there is a risk that the voltage of node GOOD may not be reduced to the ground voltage _VSS . Therefore, in this embodiment, as described above, the conduction current of transistors P21 and P22 is made smaller than the conduction current of transistors N23 and N25.

At timing t304, the signal on the signal supply line SET drops to the "L" state. At the same time, transistor N23 (Figure 14) becomes off.

At timing t305, the signals on the signal supply lines RDEC and ROMBAEN drop to the "L" state. Simultaneously, transistor P11 (Figure 13) becomes on, and transistor N16 (Figure 13) becomes off. This charges node n11 to the operating voltage _VDD in the block decoder unit blkd, which has undergone a setup operation. Furthermore, the signals on the signal supply lines RDEC_SEL and BLKSEL become "L".

[Reset Operation of Latch Circuit CBL] Figure 18 is a schematic waveform diagram illustrating the reset operation of the latch circuit CBL. During the reset operation, the latch circuit CBL contained in one of the multiple block decoder units blkd is set to a reset state.

The reset action is performed in a largely similar manner to the setting action.

However, during the reset operation at timing t303, the signal on the signal supply line RST rises to the "H" state, not the SET signal supply line. This causes the latch circuit CBL to enter the reset state.

Furthermore, during the reset operation at timing t304, the signal of the signal supply line RST, not SET, drops to the "L" state.

Furthermore, in the set state, node BAD is charged via transistors P23 and P24. Therefore, when the conduction current of transistors P23 and P24 is the same as that of transistors N24 and N25, there is a risk that the voltage of node BAD may not be reduced to the ground voltage _VSS . Therefore, in this embodiment, as described above, the conduction current of transistors P23 and P24 is made smaller than the conduction current of transistors N24 and N25.

[All Setting Operations of Latch Circuit CBL] Figure 19 is a schematic waveform diagram illustrating all setting operations of the latch circuit CBL. In all setting operations, the latch circuits CBL contained in all block decoder units (blkd) within the block decoder (BLKD) are set to the set state.

All setup actions are performed in a largely identical manner. However, at timing t301 of all setup actions, instead of inputting the block address to the block decoder BLKD, the signal supply line ALLBLK, as illustrated in Figure 12, is raised to "H".

[All Reset Operations of Latch Circuit CBL] Figure 20 is a schematic waveform diagram illustrating all reset operations of latch circuit CBL. In all reset operations, the latch circuits CBL contained in all block decoder units blkd contained in block decoder BLKD are set to a reset state.

All reset actions are performed in a manner largely identical to the reset actions. However, instead of inputting the block address to the block decoder BLKD at timing t301 of all reset actions, the signal supply line ALLBLK, as illustrated in Figure 12, is raised to "H".

[Multiple Memory Block Erasure Operation] The erasure operation described with reference to FIG. 8 takes longer than the read operation described with reference to FIG. 6 and the write operation described with reference to FIG. 7, and therefore, higher speed is desired. Therefore, the semiconductor memory device of this embodiment is configured to simultaneously select multiple memory blocks BLK contained in the memory cell array MCA and perform erasure operations on these multiple memory blocks BLK in parallel. In this specification, such an operation is referred to as a "multiple memory block erasure operation".

Figure 21 is a flowchart illustrating the process of erasing multiple memory blocks.

In step S101, all setting actions described with reference to FIG19 are performed, and all latch circuits CBL in the block decoder BLKD are set to the setting state.

In step S102, select one of the multiple memory blocks BLK contained in the memory cell array MCA, and perform the reset operation as described in Figure 18 on the corresponding latch circuit CBL.

In step S103, it is determined whether a reset operation has been performed for all memory blocks (BLKs) that have become the objects of multiple memory block erase operations. If the reset operation has been performed, proceed to step S104. If the reset operation has not been performed, return to step S102.

In step S104, the loop count _nE is set to 1. The loop count _nE is a variable that represents the number of times the loop is erased.

In step S105, by referring to all memory block selection actions as explained in FIG16, a plurality of selected memory blocks BLK selected in step S102 are selected, and the erasure action is performed on the plurality of selected memory blocks BLK in parallel.

In step S106, by referring to the memory block selection action described in Figure 15, one of the plurality of selected memory blocks (BLK) is selected, and an erase verification action is performed on the selected memory block (BLK).

In step S107, the result of the erase verification action is determined for the selected memory block BLK that has already undergone the erase verification action. If it is determined that the erase action was performed optimally, proceed to step S108. If it is determined that the erase action was not performed optimally, proceed to step S109.

In step S108, the state data indicating the normal completion of the erasure operation is stored in the state register STR (Figure 10). Furthermore, the state data is output to the controller chip CD via the state readout operation.

In step S109, state data indicating that the erasure operation did not end properly is stored in the state register STR (Figure 10).

In step S110, determine whether the erase verification operation has been performed on all selected memory block BLKs. If it has been performed, proceed to step S111. If it has not been performed, return to step S106.

In step S111, it is determined whether to terminate the multiple memory block erasure operation. The determination of whether to terminate the multiple memory block erasure operation can be appropriately adjusted. For example, if it is determined that the erasure operation has not been performed optimally on all selected memory block BLKs, the multiple memory block erasure operation is considered not to be terminated. Or, for example, if it is determined that the erasure operation has been performed optimally on at least one selected memory block BLK, the multiple memory block erasure operation is considered to be terminated. If the multiple memory block erasure operation is not terminated, proceed to step S112. If terminated, proceed to step S114.

In step S112, determine whether the loop count _nE has reached the specified count _NE . If not, proceed to step S113. If it has, proceed to step S114.

In step S113, 1 is incremented by the loop count _nE , and the process returns to step S105. Also, in step S110, for example, a specified voltage ΔV is incremented by the erase voltage _VERA . Therefore, the erase voltage _VERA increases along with the loop count _nE .

In step S114, a reset operation is performed. During the reset operation, for example, all reset operations described with reference to FIG20 are performed, setting all latch circuits CBL in the block decoder BLKD to a reset state. Furthermore, in the case where the memory cell array MCA contains one or more faulty blocks, the setting operations described with reference to FIG17 are sequentially performed on one or more latch circuits CBL corresponding to those one or more faulty blocks.

Figure 22 is a schematic waveform diagram illustrating an example of performing multiple memory block erase operations. The following shows an example of performing multiple memory block erase operations on two memory blocks BLK in the memory cell array MCA.

Furthermore, as explained with reference to Figure 10, the memory chip (MD) has eight data input/output terminals DQ0 to DQ7. In the following explanation, sometimes two-digit hexadecimal representations are used to represent the eight bits of data input to the eight data input/output terminals DQ0 to DQ7. For example, when "0, 0, 0, 0, 0, 0, 0, 0, 0" is input to the eight data input/output terminals DQ0 to DQ7, the data may be represented as data 00h, etc. Similarly, when "1, 1, 1, 1, 1, 1, 1, 1, 1" is input, the data may be represented as data FFh, etc.

Furthermore, the 8-bit data constituting the data XXh, YYh, and ZZh described later can be either "0" or "1". Also, the data in the 8-bit data constituting XXh, YYh, and ZZh, from the first to the fourth bit and from the fifth to the eighth bit, can be the same or different.

Figure 22 illustrates the instruction setting CS11 input to the memory die MD during multiple memory block erase operations. This instruction setting includes data 60h, A101, A102...A1XX, XXh.

At timing t401, the controller chip CD (Figure 1) inputs data 60h as instruction data Cmd to the memory chip MD. That is, the voltage of the data signal input/output terminals DQ0 to DQ7 (Figure 10) is set to "H" or "L" according to each bit of data 60h. When "H" is input to the external control terminal CLE (Figure 10) and "L" is input to the external control terminal ALE (Figure 10), the external control terminal /WE is changed from "L" to "H". Data 60h is an instruction input when multiple memory block erase operations are performed, and it is the first data input in the instruction setting CS11.

At timing t402, the controller chip CD (Figure 1) inputs data A101 as address data Add to the memory chip MD. That is, the voltage of the data signal input/output terminals DQ0 to DQ7 (Figure 10) is set to "H" or "L" according to each bit of data A101. When "L" is input to the external control terminal CLE (Figure 10) and "H" is input to the external control terminal ALE (Figure 10), the external control terminal /WE is changed from "L" to "H". Data A101 includes a portion of the address data Add corresponding to the first selected memory block BLK.

Similarly, at timings t403 to t404, the controller die CD (Figure 1) inputs data A102 to data A1XX as address data Add to the memory die MD. Data A102 to data A1XX each contain a portion of the address data Add corresponding to the first selected memory block BLK.

At timing t405, the controller die CD (Figure 1) inputs data XXh to the memory die MD as instruction data Cmd. In this embodiment, data XXh is an instruction input when multiple memory block erase operations are performed, and it is the last data input in instruction setting CS11.

At timing t406, the terminal RY//BY changes from the "H" state to the "L" state, disabling access to the memory chip MD. Furthermore, in the memory chip MD, all setting actions and the reset action corresponding to the first selected memory block BLK are performed.

At timing t407, the reset operation corresponding to the first selected memory block BLK ends. Also, the terminal RY//BY changes from the "L" state to the "H" state, allowing access to the memory die MD.

Furthermore, Figure 22 illustrates the instruction setting CS12 input to the memory die MD during multiple memory block erase operations. This instruction setting includes data 60h, A201, A202…A2XX, YYh.

At timing t411, the controller chip CD (Figure 1) inputs data 60h as instruction data Cmd to the memory chip MD.

At timing t412, the controller die CD (Figure 1) inputs data A201 as address data Add to the memory die MD. Data A201 contains a portion of the address data Add corresponding to the second selected memory block BLK.

Similarly, during timings t413 to t414, the controller die CD (Figure 1) inputs data A202 to data A2XX into the memory die MD as address data Add. Data A202 to data A2XX each contain a portion of the address data Add corresponding to the second selected memory block BLK.

At timing t415, the controller die CD (Figure 1) inputs data YYh to the memory die MD as instruction data Cmd. Data YYh is the instruction input when multiple memory block erase operations are performed, and it is the last data input in instruction setting CS12.

At timing t416, the RY//BY terminal changes from the "H" state to the "L" state, disabling access to the memory die MD. Furthermore, within the memory die MD, a reset operation corresponding to the second selected memory block BLK and an erase operation for all selected memory block BLKs are performed.

At timing t417, the erase operation ends. Also, the RY//BY terminal changes from the "L" state to the "H" state, allowing access to the memory die MD.

Furthermore, Figure 22 illustrates the instruction setting CS13 input to the memory die MD during multiple memory block erase operations. This instruction setting includes data 60h, A101, A102...A1XX, AFh.

At timing t421, the controller chip CD (Figure 1) inputs data 60h as instruction data Cmd to the memory chip MD.

At timing t422, the controller die CD (Figure 1) inputs data A101 as address data Add to the memory die MD.

Similarly, during timings t423 to t424, the controller chip CD (Figure 1) inputs data A102 to data A1XX into the memory chip MD as address data Add.

At timing t425, the controller die CD (Figure 1) inputs data AFh to the memory die MD as instruction data Cmd. Data AFh is the instruction input when the erase verification operation is performed, and it is the last data input in instruction setting CS13.

At timing t426, the RY//BY terminal changes from the "H" state to the "L" state, disabling access to the memory die MD. Furthermore, in the memory die MD, the erase verification operation corresponding to the first selected memory block BLK is performed.

At timing t427, the erase operation ends. Also, the RY//BY terminal changes from the "L" state to the "H" state, allowing access to the memory die MD.

At timing t428, the controller chip CD (Figure 1) inputs data 7Xh as instruction data Cmd to the memory chip MD. Data 7Xh is an instruction requesting the output of the status data Stt latched in the status register STR (Figure 10). After the input of data 7Xh, the controller chip CD retrieves the status data Stt from the memory chip MD.

Next, the actions to be performed on the second selected memory block BLK are explained with reference to timings t421 to t428, and the diagrams are omitted.

Next, the controller die CD (Figure 1) determines whether the multiple memory block erasure operations have ended (step S111 in Figure 21) and whether the loop count _nE has reached the specified number _NE (step S112 in Figure 21). If the erasure operation is further executed, the operations corresponding to timings t411 to t428 are executed again.

At timing t431, the controller die CD (Figure 1) inputs data ZZh as instruction data Cmd to the memory die MD. Data ZZh is the last instruction input in a plurality of memory block erase operations.

At timing t432, the terminal RY//BY changes from the "H" state to the "L" state, disabling access to the memory die MD. Furthermore, in the memory die MD, a reset operation is performed (step S114 in Figure 21).

At timing t433, the reset operation ends. Also, the RY//BY terminal changes from the "L" state to the "H" state, allowing access to the memory die MD.

[Second Embodiment] Next, the semiconductor memory device of the second embodiment will be described.

Figures 23 and 24 are schematic circuit diagrams showing the configuration of the column decoder RD2 of the second embodiment. In the following description, the same symbols are assigned to the parts that are the same as those in the first embodiment, and the descriptions are omitted.

The semiconductor memory device of the second embodiment is configured in the same way as the semiconductor memory device of the first embodiment. However, as shown in FIG23, the semiconductor memory device of the second embodiment has a column decoder RD2 instead of column decoder RD.

The column decoder RD2 is constructed in essentially the same way as the column decoder RD. However, the column decoder RD2 has a block decoder BLKD2 instead of the block decoder BLKD.

The block decoder BLKD2 is basically constructed the same as the block decoder BLKD. However, the block decoder BLKD2 has multiple block decoder units blkd2 instead of multiple block decoder units blkd.

The block decoder unit blkd2 is basically constructed the same as the block decoder unit blkd. However, as shown in Figure 24, the block decoder unit blkd2 has a block address receiving circuit CAR2 and a selection information holding circuit CSL2 replacing the block address receiving circuit CAR and the selection information holding circuit CSL.

The block address receiver circuit CAR2 is basically constructed the same as the block address receiver circuit CAR. However, in the block address receiver circuit CAR2, the gate electrode of transistor P11 is not connected to the signal supply line RDEC, but to the signal supply line RDECP. Also, the gate electrode of transistor N16 is not connected to the signal supply line RDEC, but to the signal supply line RDECN.

As shown in Figure 23, the signal supply lines RDECP and RDECN are commonly connected to all block decoder units blkd2.

The selection information hold circuit CSL2 is essentially the same as the selection information hold circuit CSL. However, the selection information hold circuit CSL2 has an inverter circuit INV2 replacing transistor P12. The input terminals of the inverter circuit INV2 are connected to the signal supply line RDEC_SEL. The output terminals of the inverter circuit INV2 are connected to node n11.

Furthermore, the conduction current of the inverter circuit INV2 when it outputs "H" is smaller than the conduction current of transistors N11, N12, N13, N14, N15, N16, and N18. Also, the conduction current of the inverter circuit INV2 when it outputs "H" is smaller than the conduction current of transistors N11, N12, N13, N14, N15, N16, and N17.

The block decoder BLKD2 of this embodiment can perform the operations that the block decoder BLKD can perform. When the block decoder BLKD2 performs the same operations as the block decoder BLKD, the signal supply lines RDECP, RDECN and RDEC operate in the same way as the signal supply line RDEC.

Furthermore, the block decoder BLKD2 of this embodiment is configured to perform multiple memory block selection operations.

Figure 25 is a schematic waveform diagram illustrating the multiple memory block selection action. In the multiple memory block selection action, from the multiple memory block BLKs in the memory cell array MCA, the multiple memory block BLKs corresponding to the multiple block addresses entered multiple times are selected as the selected memory block BLKs, and the other memory block BLKs become non-selected memory block BLKs. The following shows an example of selecting two memory block BLKs.

Before the start of multiple memory block selection actions, the signals on the signal supply lines RDECP, RDECN, ROMBAEN, SET, and RST are all in the "L" state.

At timing t501, the first block address is input to the block decoder BLKD2, and the address supply line AROW signal is switched. Simultaneously, in the block address receiving circuit CAR2 (Figure 24) corresponding to the first selected memory block BLK, transistors N11, N12, N13, N14, and N15 are all turned on. On the other hand, in other block address receiving circuits CAR2, at least one of transistors N11, N12, N13, N14, and N15 is turned off.

At timing t502, the signals on the signal supply lines RDECP and RDECN rise to the "H" state. At the same time, transistor P11 (Figure 24) becomes off and transistor N16 (Figure 24) becomes on.

Therefore, in the block decoder unit blkd2 corresponding to the first select memory block BLK, if transistor N18 (Fig. 24) is in the on state, the voltage of node n11 is reduced to the ground voltage _VSS . Furthermore, when the signal supply lines RDEC_SEL and BLKSEL output "H", the multiple character lines WL and multiple voltage supply lines CG in the first select memory block BLK are turned on.

At timing t503, the signal on the signal supply line RDECN drops to the "L" state. Simultaneously, transistor N16 (Figure 24) becomes off. Consequently, in the block decoder unit blkd2 corresponding to the first select memory block BLK, the voltage supply line of node n11 to the self-supply ground voltage _VSS is electrically disconnected.

Here, for example, in the case where the block decoder unit blkd2 in the second embodiment has a selection information holding circuit CSL instead of a selection information holding circuit CSL2, there is a risk that node n11 will become floating at timing t503, and the voltage of node n11 will change. Therefore, in this embodiment, the voltage of node n11 is fixed at the ground voltage _VSS by the inverter circuit INV2.

At timing t504, the second block address is input into the block decoder BLKD2, and the address supply line AROW signal is switched. Simultaneously, in the block address receiving circuit CAR2 (Figure 24) corresponding to the second selected memory block BLK, transistors N11, N12, N13, N14, and N15 all become active. On the other hand, in the other memory blocks BLK, at least one of transistors N11, N12, N13, N14, and N15 becomes in the off state.

At timing t505, the signal on the signal supply line RDECN rises to the "H" state. At the same time, transistor P11 (Figure 24) becomes off and transistor N16 (Figure 24) becomes on.

Therefore, in the block decoder unit blkd2 corresponding to the second selection memory block BLK, if transistor N18 (Fig. 24) is in the ON state, the voltage of node n11 is reduced to the ground voltage _VSS . Furthermore, when the signal supply lines RDEC_SEL and BLKSEL output "H", the multiple character lines WL and multiple voltage supply lines CG in the second selection memory block BLK are turned on.

At timing t506, the signal on the signal supply line RDECN drops to the "L" state. Simultaneously, transistor N16 becomes off. Consequently, in the block decoder unit blkd2 corresponding to the second select memory block BLK, the voltage supply line of node n11 to the self-supply ground voltage _VSS is electrically disconnected.

During timing t505 to t507, multiple character lines WL and multiple voltage supply lines CG in the two selected memory blocks BLK are turned on. Therefore, by performing the erase operation described with reference to FIG8 in this state, for example, the same operation as the multiple memory block erase operation in the first embodiment can be performed.

Furthermore, when selecting three or more memory blocks (BLK), the actions corresponding to timings t504 to t506 are repeated.

At timing t507, the signal on the signal supply line RDECP drops to the "L" state. Simultaneously, transistor P11 (Figure 24) becomes active, and node n11 in the block decoder unit blkd2, corresponding to the multiple select memory blocks BLK, is charged to the operating voltage _VDD . Furthermore, since the signal supply line RDEC_SEL outputs "L", the signal supply line BLKSEL connected to the corresponding level shifter LS also becomes "L", and the multiple character lines WL in the two select memory blocks BLK are electrically disconnected from the multiple voltage supply lines CG.

Figure 26 is a flowchart illustrating the multiple memory block erasure actions of the second implementation.

The multiple memory block erasure operations of the second implementation are performed in essentially the same way as the multiple memory block erasure operations of the first implementation.

However, in the multiple memory block erasure actions of the second implementation, steps S101 to S103 of Figure 21 are not performed.

Furthermore, in the plurality of memory block erasure operations of the second embodiment, step S205 replaces step S105. In step S205, a plurality of selected memory blocks (BLKs) are selected by the plurality of memory block selection operation described with reference to FIG25, and the erasure operation is performed on the plurality of selected memory blocks (BLKs) in parallel.

Furthermore, in the multiple memory block erasure actions of the second implementation, step S114 of Figure 21 is not performed.

Figure 27 is a schematic waveform diagram illustrating an example of performing multiple memory block erase operations. The following shows an example of performing multiple memory block erase operations on two memory blocks BLK in the memory cell array MCA.

The multiple memory block erasure operations of the second implementation are performed in essentially the same way as the multiple memory block erasure operations of the first implementation.

However, at timing t406, the actions of selecting multiple memory blocks as described in Figure 25 up to timing t503 are performed to replace all setting actions and the reset action corresponding to the first selected memory block BLK.

At timing t416, the actions of selecting multiple memory blocks as described in Figure 25 up to timing t506 are performed, replacing the reset action corresponding to the second selected memory block BLK.

Furthermore, the reset action corresponding to the timing t431 (Fig. 22) of the first implementation form is not performed.

According to the semiconductor memory device of the second embodiment, multiple memory block erasure operations can be performed without operating the latch circuit CBL. Therefore, compared with the semiconductor memory device of the first embodiment, multiple memory block erasure operations can be performed at high speed.

[Third Embodiment] Next, the semiconductor memory device of the third embodiment will be described.

Figure 28 is a schematic circuit diagram showing the configuration of the column decoder of the third embodiment. In the following description, the same symbols are assigned to the parts that are the same as those in the second embodiment, and the descriptions are omitted.

The semiconductor memory device of the third embodiment is basically constructed the same as that of the semiconductor memory device of the second embodiment. However, as shown in FIG28, the block decoder unit blkd3 of the third embodiment has a selection information holding circuit CSL3 instead of the selection information holding circuit CSL2.

The selection information hold circuit CSL3 is basically the same as the selection information hold circuit CSL2. However, the selection information hold circuit CSL3 has an inverter circuit INV3 instead of the inverter circuit INV2.

The inverter circuit INV3 has transistors P12, N31, and N32. Transistors N31 and N32 are, for example, field-effect NMOS transistors.

The source electrode of transistor N31 is connected to the drain electrode of transistor N32. The drain electrode of transistor N31 is connected to node n11. The gate electrode of transistor N31 is connected to the signal supply line RDEC_SEL.

The source electrode of transistor N32 is connected to the voltage supply line supplied with the ground voltage _VSS . The drain electrode of transistor N32 is connected to the source electrode of transistor N31 as described above. The gate electrode of transistor N32 is connected to the signal supply line RDECP.

[Fourth Embodiment] Next, the semiconductor memory device of the fourth embodiment will be described.

Figure 29 is a schematic block diagram showing the configuration of the peripheral circuit PC4 in the fourth embodiment. The same symbols are assigned to the parts that are the same as those in the first embodiment, and the descriptions are omitted.

The semiconductor memory device of the fourth embodiment is basically constructed the same as that of the semiconductor memory device of the first embodiment. However, as shown in FIG29, the semiconductor memory device of the fourth embodiment has a peripheral circuit PC4 replacing the peripheral circuit PC.

Peripheral circuit PC4 is basically constructed the same as peripheral circuit PC. However, peripheral circuit PC4 has address register ADR4 instead of address register ADR.

Address register ADR4 is basically constructed the same as address register ADR. However, address register ADR4 is constructed to store more address data than address register ADR.

Figure 30 is a schematic waveform diagram illustrating an example of the action of performing multiple memory block erasure operations in the fourth implementation. The following shows an example of performing multiple memory block erasure operations on two memory blocks BLK in the memory cell array MCA.

Figure 30 illustrates the instruction setting CS51 input to the memory die MD during multiple memory block erase operations. This instruction setting includes data XXh, A101, A102…A1XX, A201, A202…A2XX, D0h.

At timing t501, the controller die CD (Figure 1) inputs data XXh to the memory die MD as instruction data Cmd. In this embodiment, data XXh is an instruction input when multiple memory block erase operations are performed, and it is the first data input in instruction setting CS51.

At timing t502, the controller die CD (Figure 1) inputs data A101 as address data Add to the memory die MD.

Similarly, in timings t503 to t504, the controller chip CD (Figure 1) inputs data A102 to data A1XX into the memory chip MD as address data Add.

At timing t506, the controller die CD (Figure 1) inputs data A201 as address data Add to the memory die MD.

Similarly, in timings t507 to t508, the controller chip CD (Figure 1) inputs data A202 to data A2XX into the memory chip MD as address data Add.

At timing t509, the controller die CD (Figure 1) inputs data D0h to the memory die MD as instruction data Cmd. Data D0h is the instruction input when executing multiple memory block erase operations in this embodiment, and is the last data input in instruction setting CS51.

At timing t510, the terminal RY//BY changes from the "H" state to the "L" state, prohibiting access to the memory chip MD. Furthermore, within the memory chip MD, the following actions are performed: determining whether all setting actions have ended; resetting actions corresponding to the first and second selected memory blocks BLK; erasing actions for all selected memory block BLKs; multiple erasure verification actions corresponding to multiple selected memory block BLKs; multiple memory block erasure actions (step S111 in Figure 21); determining whether the loop count _nE has reached the specified number _NE (step S112 in Figure 21); and a reset action.

At timing t511, the erase operation ends. Also, the RY//BY terminal changes from the "L" state to the "H" state, allowing access to the memory die MD.

At timing t512, the controller chip CD (Figure 1) inputs data 70h as instruction data Cmd to the memory chip MD. Data 70h is an instruction requesting the output of the status data Stt latched in the status register STR (Figure 10). After the input of data 70h, the controller chip CD retrieves the status data Stt from the memory chip MD.

In the semiconductor memory device of the fourth embodiment, a single instruction CS51 is used to select all memory blocks BLK that are the objects of a plurality of memory block erase operations. Therefore, the address register ADR4 of the fourth embodiment is configured to store more address data Add compared to the address register ADR of the first embodiment.

[Other Embodiments] The semiconductor memory device of embodiments 1 to 4 has been described above. However, the above configuration is merely illustrative, and the specific configuration can be appropriately adjusted.

For example, in the plurality of memory block erasure operations of the first embodiment, as explained with reference to FIG21, all setting operations are performed in step S101, and in steps S102 and S103, a plurality of reset operations are performed corresponding to the plurality of memory blocks BLK that are the objects of the plurality of memory block erasure operations.

However, for example, it is also possible to perform all reset actions instead of all setting actions in step S101, and to perform setting actions instead of reset actions in steps S102 and S103.

Furthermore, the semiconductor memory device of the fourth embodiment may also have the column decoder RD2 of the second embodiment (Fig. 23) or the column decoder of the third embodiment instead of the column decoder RD. Also, in the plurality of memory block erase operations of the fourth embodiment, an erase operation utilizing a plurality of memory block selection operations can be performed, replacing all setting operations, a reset operation corresponding to the first and second selected memory blocks BLK, an erase operation utilizing all memory block selection operations, and a reset operation.

[Other] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented using various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention described in the patent application and its equivalents.

10: Memory System 20: Mainframe 100: Semiconductor Substrate 101: Insulation Layer 110: Conductive Layer 112: Semiconductor Layer 120: Semiconductor Pillar 121: Impurity Region 125: Insulation Layer 130: Gate Insulation Film Add: Address Data ADR, ADR4: Address Registers ALE, CLE, RE, /CE, /RE, /WE: External Control Terminals ALLBLK: Signal Supply Lines AROW, AROWA, AROWB, AROWC, AROWD, AROWE: Address Supply Lines blkd, blkd2, blkd3: Block Decoder Unit B: Junction Line BAD: Node BL, BL _P , BL _W : Bit lines BLK: Memory block BLKD, BLKD2: Block decoder BLKSEL: Signal supply lines Cb, Ch: Contacts CA: Row address CAR, CAR2: Block address receiver circuit CBL: Latch circuit CC: Contact CD: Controller chip CG: Voltage supply line CTR: Logic circuit CM: Cache memory Cmd: Instruction data CMR: Instruction register COR: OR circuit CS11~CS13, CS51: Instruction setting CSL, CSL2, CSL3: Select Selectable Information Holding Circuit Dat: User Data DB: Data Bus/Bus DQ0~DQ7: Data Signal Input/Output Terminals DQS,/DQS: Data Selector Signal Input/Output Terminals GOOD: Node IAG: Inverting Signal Generation Circuit INV1, INV2, INV3: Inverter Circuit I/O: Input/Output Control Circuit LS: Level Shifter MC: Memory Cell MCA: Memory Cell Array MD: Memory Diode MS: Memory String MSB: Mounting Substrate n11, n12 nAA, nAB, nAC, nAD, nAE: Nodes N11~N18, P11, P12, P21~P24, N21~N25, N31, N32: Transistors P: Pads PC, PC4: Peripheral circuits RA: Column addresses RD, RD2: Column decoders RDEC, RDECP, RDECN, RDEC_SEL, ROMBAEN, RST, SET: Signal supply lines RY//BY: Terminals S101~S114, S205: Steps SA: Sensing Amplifier; SGD, SGDT, SGS, SGSB: Select Gate Line; SL: Source Line; SQC: Sequencer; ST: Inter-block Insulation Layer; STD, STDT, STS, STSB: Select Transistor; STR: State Register; Stt: State Data; SU: Serial Unit; t101~t103, t201~t203, t301~t305, t401~t407, t411~t417, t421~t433, t501~t512: Timing T _BLK : Transistor; Tr: Transistor; _VCC : Power Supply Voltage; _VCGR : Read Voltage; _VDD : Operating Voltage; _VERA : Erase Voltage; VG: Voltage Generation Circuit; _VPASS : Write Circuit Voltage; _VPGM : Program Voltage; _VREAD : Read Circuit Voltage; _VSG , _VSG´ , _VSG´´ , _VSGD , _VSRC : Voltage; _VSS : Ground Voltage; _VFYEr : Erase Verification Voltage; WL: Character Line; _WLS : Select Character Line; _WLU : Non-Select Character Line; xfer: Voltage Transmission Unit; X, Y, Z: Direction; XFER: Voltage Transmission Circuit.

Figure 1 is a schematic block diagram showing the configuration of the memory system 10. Figure 2 is a schematic side view showing an example of the configuration of the memory system 10. Figure 3 is a schematic plan view showing this example configuration. Figure 4 is a schematic circuit diagram showing the configuration of a portion of the memory die MD. Figure 5 is a schematic perspective view showing the configuration of a portion of the memory cell array MCA. Figure 6 is a schematic cross-sectional view illustrating the read operation. Figure 7 is a schematic cross-sectional view illustrating the write operation. Figure 8 is a schematic cross-sectional view illustrating the erase operation. Figure 9 is a schematic cross-sectional view illustrating the erase verification operation. Figure 10 is a schematic block diagram showing the configuration of the peripheral circuit PC. Figure 11 is a schematic circuit diagram showing the configuration of the voltage transmission circuit XFER, which is part of the column decoder RD. Figure 12 is a schematic circuit diagram showing the configuration of the block decoder BLKD, which is part of the column decoder RD. Figure 13 is a schematic circuit diagram showing the configuration of the block decoder unit blkd. Figure 14 is a schematic circuit diagram showing the configuration of the latch circuit CBL. Figure 15 is a schematic waveform diagram illustrating the memory block selection operation. Figure 16 is a schematic waveform diagram illustrating all memory block selection operations. Figure 17 is a schematic waveform diagram illustrating the setting operation of latch circuit CBL. Figure 18 is a schematic waveform diagram illustrating the reset operation of latch circuit CBL. Figure 19 is a schematic waveform diagram illustrating all setting operations of latch circuit CBL. Figure 20 is a schematic waveform diagram illustrating all reset operations of latch circuit CBL. Figure 21 is a flowchart illustrating multiple memory block erase operations. Figure 22 is a schematic waveform diagram illustrating an example of performing multiple memory block erase operations. Figure 23 is a schematic circuit diagram showing the configuration of column decoder RD2 in the second embodiment. Figure 24 is a schematic circuit diagram showing the configuration of the column decoder RD2 in the second embodiment. Figure 25 is a schematic waveform diagram illustrating the selection of multiple memory blocks. Figure 26 is a flowchart illustrating the erasure of multiple memory blocks in the second embodiment. Figure 27 is a schematic waveform diagram illustrating an example of the operation of performing the erasure of multiple memory blocks. Figure 28 is a schematic circuit diagram showing the configuration of the column decoder in the third embodiment. Figure 29 is a schematic block diagram showing the configuration of the peripheral circuit PC4 in the fourth embodiment. Figure 30 is a schematic waveform diagram illustrating an example of the actions involved in performing the erase operation of multiple memory blocks in the fourth implementation mode.

S101~S114: Steps

Claims (10)

A semiconductor memory device includes: a plurality of memory blocks, each having a memory cell and a character line connected to the memory cell; bit lines and source lines, all commonly electrically connected to a plurality of memory cells corresponding to the plurality of memory blocks; a first voltage supply line, commonly electrically connected to a plurality of character lines corresponding to the plurality of memory blocks; a plurality of first transistors, each corresponding to the plurality of memory blocks, and electrically connected between the character lines and the first voltage supply line; A plurality of first signal supply lines, each corresponding to one of the aforementioned plurality of memory blocks, are respectively connected to the gate terminals of the plurality of first transistors; A plurality of block decoder units, each corresponding to one of the aforementioned plurality of memory blocks, are capable of outputting a signal to any of the plurality of first signal supply lines based on the input of a signal corresponding to a block address; and A control circuit that controls the plurality of block decoder units; and Each of the plurality of block decoder units includes: A plurality of second transistors, electrically connected in series between a second voltage supply line and a third voltage supply line, each having a signal corresponding to a block address input at its gate terminal; A third transistor, electrically connected between the aforementioned plurality of second transistors and the aforementioned second voltage supply line; a fourth transistor, electrically connected between the aforementioned plurality of second transistors and the aforementioned third voltage supply line; and a latching circuit connected to the gate electrode of the aforementioned fourth transistor; and the aforementioned control circuit, is configured to perform a plurality of memory block erasure operations, wherein the plurality of memory block erasure operations select two or more memory blocks from the aforementioned plurality of memory blocks as a plurality of selected memory blocks, and perform erasure operations on the plurality of selected memory blocks in parallel, In the aforementioned plurality of memory block erasure operations, before performing the aforementioned erasure operation, the data of the plurality of latch circuits corresponding to the plurality of selected memory blocks is overwritten. As in the semiconductor memory device of claim 1, wherein during the aforementioned plurality of memory block erase operations, before the execution of the aforementioned erase operation, the aforementioned control circuit performs all setting operations that set the aforementioned plurality of latches to a setting state, and performs a plurality of reset operations that set one of the aforementioned plurality of latches to a reset state. As in the semiconductor memory device of claim 1, wherein, during the aforementioned plurality of memory block erase operations, after the execution of the aforementioned erase operation, the aforementioned control circuit executes all reset operations that set the aforementioned plurality of latch circuits to a reset state. As in the semiconductor memory device of claim 1, the aforementioned control circuit selects all of the aforementioned plurality of memory blocks when performing the aforementioned erase operation in the aforementioned plurality of memory block erase operation. The semiconductor memory device of claim 1 includes: a plurality of inverter circuits, each configured to correspond to a plurality of address signals corresponding to each bit in the aforementioned block address, and outputting a plurality of inverted signals of the aforementioned plurality of address signals; and a plurality of OR circuits, each configured to correspond to the aforementioned plurality of address signals and the aforementioned plurality of inverted signals, having one of the aforementioned plurality of address signals and the aforementioned plurality of inverted signals input to one input terminal, and another input terminal electrically connected to a second signal supply line, outputting a signal corresponding to the aforementioned block address; and during the aforementioned erase operation of the aforementioned plurality of memory blocks, the aforementioned control circuit, switches the signal of the aforementioned second signal supply line, When the signal on the aforementioned second signal supply line is switched, an erase voltage is supplied to at least one of the aforementioned bit line and the aforementioned source line, and a voltage smaller than the aforementioned erase voltage is supplied to the aforementioned first voltage supply line. A semiconductor memory device includes: a plurality of memory blocks, each having a memory cell and a character line connected to the memory cell; bit lines and source lines, all commonly electrically connected to a plurality of memory cells corresponding to the plurality of memory blocks; a first voltage supply line, commonly electrically connected to a plurality of character lines corresponding to the plurality of memory blocks; a plurality of first transistors, each corresponding to the plurality of memory blocks, and electrically connected between the character lines and the first voltage supply line; A plurality of first signal supply lines, each corresponding to one of the aforementioned plurality of memory blocks, are respectively connected to the gate terminals of the plurality of first transistors; A plurality of block decoder units, each corresponding to one of the aforementioned plurality of memory blocks, are capable of outputting a signal to any of the plurality of first signal supply lines based on the input of a signal corresponding to a block address; and A control circuit that controls the plurality of block decoder units; and Each of the plurality of block decoder units includes: A plurality of second transistors, electrically connected in series between a second voltage supply line and a third voltage supply line, each having a signal corresponding to a block address input at its gate terminal; A third transistor, electrically connected between the aforementioned plurality of second transistors and the aforementioned second voltage supply line; A fourth transistor, electrically connected between the aforementioned plurality of second transistors and the aforementioned third voltage supply line; A latching circuit connected to the gate electrode of the aforementioned fourth transistor; and A fifth transistor, electrically connected between the aforementioned plurality of second transistors and the aforementioned fourth transistor; and configured to independently control the signal input to the gate electrode of the aforementioned third transistor and the signal input to the gate electrode of the aforementioned fifth transistor. As in the semiconductor memory device of claim 6, the aforementioned control circuit is configured to perform a plurality of memory block selection operations, selecting two or more memory blocks from the plurality of memory blocks. In the aforementioned plurality of memory block selection operations, in a first timing sequence, a signal corresponding to the aforementioned block address is supplied to the aforementioned plurality of block decoder units. In a second timing sequence, a signal is supplied to the gate electrode of the aforementioned third transistor to set the aforementioned third transistor to a turned-off state, and a signal is supplied to the gate electrode of the aforementioned fifth transistor to set the aforementioned fifth transistor to a turned-on state. In the third timing sequence, a signal to set the fifth transistor to the off state is supplied to its gate electrode. In the fourth timing sequence, other signals corresponding to the block address are supplied to the plurality of block decoder units. In the fifth timing sequence, the aforementioned signal to set the fifth transistor to the on state is supplied to its gate electrode. In the sixth timing sequence, the aforementioned signal to set the fifth transistor to the off state is supplied to its gate electrode. As in the semiconductor memory device of claim 7, the aforementioned control circuit is configured to perform a plurality of memory block erase operations, wherein each memory block erase operation selects two or more memory blocks as a plurality of selected memory blocks, and performs erase operations on these plurality of selected memory blocks in parallel; within the aforementioned plurality of memory block erase operations, the aforementioned plurality of memory block selection operations are performed. Following the fifth timing sequence described above, while the aforementioned signal, intended to turn off the third transistor, is input to the gate electrode of the third transistor, an erase voltage is supplied to at least one of the bit line and the source line, and a voltage smaller than the erase voltage is supplied to the first voltage supply line. As in claim 6, the semiconductor memory device further comprises: a first node electrically connected between the plurality of second and third transistors; a first inverter circuit with its input terminals electrically connected to the first node; and a second inverter circuit with its input terminals electrically connected to the output terminals of the first inverter circuit, and its output terminals electrically connected to the first node. As in claim 6, the semiconductor memory device further comprises: a first node electrically connected between the plurality of second and third transistors; a first inverter circuit with its input terminals electrically connected to the first node; a sixth transistor with its source terminal electrically connected to the second voltage supply line, its drain terminal electrically connected to the first node, and its gate terminal connected to the output terminal of the first inverter circuit; a seventh transistor with its source terminal electrically connected to the third voltage supply line, its drain terminal electrically connected to the first node, and its gate terminal connected to the output terminal of the first inverter circuit; and The eighth transistor is electrically connected between the aforementioned third voltage supply line and the aforementioned seventh transistor, and its gate electrode is electrically connected to the gate electrode of the aforementioned third transistor.