TWI910944B - Method of manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes the following steps. Providing a substrate including, from bottom to top, a bottom semiconductor layer, an insulating layer, and a top semiconductor layer, where the insulating layer and the top semiconductor layer together have a first total thickness. Forming a patterned mask layer on the substrate, where the patterned mask layer includes a bottom mask layer and a top mask layer. Etching the top semiconductor layer and the insulating layer under the coverage of the patterned mask layer to form a patterned top semiconductor layer and a patterned insulating layer. Forming a first epitaxial layer on the bottom semiconductor layer, where the top surface of the first epitaxial layer is lower than the bottom surface of the top mask layer. Removing the patterned mask layer. Forming a second epitaxial layer on the top semiconductor layer and the first epitaxial layer, where the second epitaxial layer has a second thickness, and the ratio of the second thickness to the first total thickness is from 2 to 30.

Description

Manufacturing method of semiconductor device and semiconductor device

This disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a patterned insulating layer and the semiconductor device thereof.

In power or electronic systems, power transistors are commonly used as power components such as power switches and converters. Power transistors are transistors that operate under high voltage and high current conditions. The most common type of power transistor is the power metal-oxide-semiconductor field-effect transistor (power MOSFET). Types of power transistors include horizontal structures, such as lateral double-diffused MOSFETs (LDMOS), and vertical structures, such as vertical double-diffused MOSFETs (VDMOS). The gate of a VDMOS can be a planar gate, a trench gate, or a combination of both.

In order to increase the integration of transistor components, the industry currently needs to integrate horizontal and vertical power transistors on the same wafer. Therefore, it is necessary to propose a semiconductor structure and its manufacturing method to meet the above requirements.

In view of this, this disclosure proposes a semiconductor device manufacturing method that avoids stage height differences during epitaxial layer formation, reducing the complexity of subsequent processes. This disclosure also proposes a semiconductor device that can simultaneously house horizontal and vertical power metal-oxide-semiconductor field-effect transistors within the device, with an oxide layer at the bottom of the horizontally structured power metal-oxide-semiconductor field-effect transistor, thereby reducing the gate-drain capacitance (Cgd) below it.

According to one embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: providing a substrate, wherein the substrate sequentially includes a bottom semiconductor layer, an insulating layer, and a top semiconductor layer from bottom to top, wherein the insulating layer and the top semiconductor layer together comprise a first overall thickness; forming a patterned mask layer on the substrate, wherein the patterned mask layer includes a bottom mask layer and a top mask layer; and etching the top semiconductor layer and the insulating layer under the cover of the patterned mask layer to form a patterned top semiconductor layer and a pattern. An insulating layer is formed; a first epitaxial layer is formed on a bottom semiconductor layer under the cover of a patterned masking layer, and the first epitaxial layer covers the sidewalls of the patterned top semiconductor layer and the sidewalls of the patterned insulating layer, wherein the top surface of the first epitaxial layer is lower than the bottom surface of the top masking layer; the patterned masking layer is removed to expose the top surface of the top semiconductor layer; and a second epitaxial layer is formed on the top semiconductor layer and the first epitaxial layer, wherein the second epitaxial layer includes a second thickness, and the ratio of the second thickness to the first overall thickness is 2 to 30.

According to one embodiment of this disclosure, a semiconductor device is provided, including a bottom semiconductor layer; a patterned insulating layer disposed on the bottom semiconductor layer and covering a portion of the bottom semiconductor layer, wherein the patterned insulating layer includes concave curved sidewalls; a patterned top semiconductor layer disposed on the bottom semiconductor layer; and a first epitaxial layer disposed on the bottom semiconductor layer, wherein the first epitaxial layer... The sidewalls are adjacent to the sidewalls of the patterned insulating layer and the sidewalls of the patterned top semiconductor layer; the second epitaxial layer is disposed on the patterned top semiconductor layer and includes: a first region located directly above the patterned insulating layer; a second region laterally separated from the patterned insulating layer; and a boundary region located between the first region and the second region, and located directly above the concave curved sidewall of the patterned insulating layer.

This disclosure provides several different embodiments for implementing various features of this disclosure. For the sake of simplicity, this disclosure also describes examples of specific components and arrangements. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "the first feature is formed on or above the second feature" could mean "the first feature and the second feature are in direct contact," or it could mean "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, the various embodiments in this disclosure may use repeated reference numerals and/or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any relationship between different embodiments and/or configurations.

Furthermore, the spatially related terms used in this disclosure, such as "below," "low," "down," "above," "above," "up," "top," "bottom," and similar terms, are used for ease of description to depict the relative relationship between one element or feature and another (or more) elements or features in the diagram. In addition to the orientations shown in the diagram, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. The spatially related descriptions used to describe the orientation of the semiconductor device, depending on its orientation (rotation 90 degrees or other orientations), should be interpreted in a similar manner.

Although this disclosure uses terms such as "first," "second," and "third" to describe various elements, components, regions, layers, and/or sections, it should be understood that such elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, and/or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the order of arrangement of one element with another, or the order of manufacturing methods. Therefore, without departing from the specific embodiments of this disclosure, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

The terms “about” or “substantially” used in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of “about” or “substantially” may be implied even without specific mention of it.

The terms “coupled,” “coupled,” and “electrically connected” used in this disclosure include any means of direct or indirect electrical connection. For example, if the text describes a first component as coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below through specific embodiments, the principles of the invention disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details have been omitted, and these omitted details are within the knowledge of those skilled in the art.

This disclosure relates to a method for manufacturing a semiconductor device and the semiconductor device itself. An embodiment of this disclosure first forms a patterned mask layer on a patterned top semiconductor layer, and then forms a first epitaxial layer, preventing the formation of the first epitaxial layer on the patterned top semiconductor layer. This avoids the first epitaxial layer simultaneously forming on the top surface and periphery of the patterned top semiconductor layer, thus preventing step height differences in the first epitaxial layer and ensuring that both the first epitaxial layer and the patterned top semiconductor layer have a flat top surface. This eliminates the need for subsequent steps to remove step height differences in different regions of the first epitaxial layer, such as a planarization process. Furthermore, the above process can be used to manufacture semiconductor devices including partial silicon insulated (SOI). Therefore, in the corresponding semiconductor device, the horizontal transistors and vertical transistors are respectively set in different regions, which can increase the design flexibility of the semiconductor device for different application requirements.

Figure 1 is a schematic cross-sectional view illustrating a stage of a semiconductor device manufacturing method according to an embodiment of the present disclosure, wherein the substrate includes at least a bottom semiconductor layer, an insulating layer, a top semiconductor layer, and a masking layer. Referring to Figure 1, a substrate 110 is first provided, which includes, from bottom to top, a substrate 101, a bottom semiconductor layer 102, an insulating layer 103, and a top semiconductor layer 104.

In one embodiment, the material of substrate 101 may include ceramic, silicon carbide (SiC), aluminum nitride (AlN), sapphire, or silicon. When substrate 101 is a material with high hardness, high thermal conductivity, and low electrical conductivity, such as a ceramic substrate, it is more suitable for high-voltage semiconductor devices. The aforementioned high hardness, high thermal conductivity, and low electrical conductivity are relative to single-crystal silicon substrates, and high-voltage semiconductor devices refer to semiconductor devices with an operating voltage higher than 50V. In another embodiment, substrate 101 may be a composite substrate (also known as a QST substrate) consisting of a core substrate (not shown) encapsulated by a composite material layer (not shown), wherein the core substrate comprises ceramic, silicon carbide, aluminum nitride, sapphire, or silicon, and the composite material layer comprises an insulating material layer and a semiconductor material layer. The insulating material layer may be a single layer or multiple layers of silicon oxide, silicon nitride, or silicon oxynitride, and the semiconductor material layer may be silicon or polycrystalline silicon. During the fabrication of the semiconductor device, the composite material layer located on the back side of the core substrate is removed by a thinning process, such as by a grinding or etching process, so that the back side of the core substrate is exposed.

The composition of the bottom semiconductor layer 102 may include silicon, germanium, gallium nitride, or other suitable semiconductor materials, but is not limited thereto. The composition of the insulating layer 103 may be, for example, a silicon oxide layer, and the material of the top semiconductor layer 104 may be the same as that of the bottom semiconductor layer 102, but is not limited thereto. In one embodiment, the substrate 110 may be an SOI wafer, which is prepared by using a wafer on which the insulating layer 103 is formed on a top surface, and after attaching another wafer on the insulating layer 103, the attached wafer is then thinned. The insulating layer 103 and the top semiconductor layer 104 together have a first overall thickness D1. In one embodiment, the first overall thickness D1 of the insulating layer 103 and the top semiconductor layer 104 may be about 0.6 micrometers (μm).

Subsequently, a masking layer 200 is formed on the substrate 110. The masking layer 200 includes a top masking layer 220 and a bottom masking layer 210. In one embodiment, the composition of the top masking layer 220 includes silicon nitride ( _Si3N4 ), titanium nitride ( _TiN ), or silicon oxide ( _SiO2 ), but is not limited thereto. The composition of the bottom masking layer 210 may include a silicon oxide layer. The top masking layer 220 of the present invention can be formed on the substrate 110 by chemical deposition, and the bottom masking layer 210 can be formed on the top semiconductor layer 104 by, for example, oxidation before the top masking layer 220 is deposited, to reduce the stress formed between the foreign material and the substrate 110 during the deposition of the foreign material.

Figure 2 is a cross-sectional schematic diagram illustrating a stage of a semiconductor device manufacturing method according to an embodiment of this disclosure, wherein the mask layer includes at least a photoresist layer. Following the process stage shown in Figure 1, referring to Figure 2, a photoresist layer 300 is formed on the mask layer 200. The photoresist layer 300 may be a multi-layer structure, for example, comprising, from bottom to top, a bottom photoresist layer (not shown), an intermediate photoresist layer and a bottom anti-reflective coating (BARC) layer (not shown), and a top photoresist layer (not shown). In one embodiment, the bottom layer of the photoresist can be a spin-on carbon (SOC) layer, which provides a relatively flat surface for the photoresist deposited or coated thereon to facilitate subsequent exposure and development processes. The material of the intermediate layer of the photoresist can be silicon oxynitride. A bottom anti-reflective coating is disposed below the top layer of the photoresist to reduce reflected light between the photoresist and the mask layer 200 during the exposure process.

Figure 3 is a cross-sectional schematic diagram illustrating a stage of a semiconductor device manufacturing method according to an embodiment of this disclosure, wherein a top semiconductor layer and an insulating layer are patterned to form a patterned top semiconductor layer and a patterned insulating layer. Referring to Figure 3, a photoresist layer 300 is subjected to an exposure and development process to form a patterned photoresist layer 300p on a mask layer 200, and the mask layer 200 is etched under the cover of the patterned photoresist layer 300p to obtain a patterned mask layer 200p.

Referring again to Figure 3, after the patterned mask layer 200p is formed, an appropriate etching process is performed under the cover of the patterned mask layer 200p to etch the top semiconductor layer 104 and the insulating layer 103 exposed on the patterned mask layer 200p, so as to form the patterned top semiconductor layer 104p and the patterned insulating layer 103p. In one embodiment, the etching degree of the insulating layer 103 can be adjusted, for example, by controlling the etching time, so that after etching, in addition to forming the patterned mask layer 200p, the insulating layer 103 not covered by the mask layer 200p is thinned to form a thinned insulating layer 103a. The presence of the thinned insulating layer 103a can protect the underlying bottom semiconductor layer 102 from etching and subsequent steps. In another embodiment, the patterned photoresist layer 300p used to form the patterned mask layer 200p can be removed after the patterned top semiconductor layer 104p and the patterned insulating layer 103p are formed.

Figure 4 is a cross-sectional schematic diagram illustrating a stage of a semiconductor device manufacturing method according to an embodiment of this disclosure, wherein an oxide layer is formed on the sidewalls of the patterned top semiconductor layer. Referring again to Figure 4, in one embodiment, after forming the patterned top semiconductor layer 104p and the patterned insulating layer 103p, the sidewalls of the patterned top semiconductor layer 104p are oxidized to form an oxide layer 104a. The oxide layer 104a can be formed by thermal oxidation, but is not limited thereto. By forming the oxide layer 104a on the sidewalls of the patterned top semiconductor layer 104p, lattice defects adjacent to the sidewalls can be converted into part of the oxide layer 104a. Therefore, when the oxide layer 104a is subsequently removed, these lattice defects can be removed at the same time, thus eliminating the lattice defects that originally existed on the sidewalls of the patterned top semiconductor layer 104p.

Figure 5 is a cross-sectional schematic view illustrating a stage of a semiconductor device manufacturing method according to an embodiment of this disclosure, wherein the sidewalls of the patterned insulating layer include curved sidewalls. Referring to Figure 5, in one embodiment, after an oxide layer 104a is formed on the sidewalls of the patterned top semiconductor layer 104p, an appropriate etching process, such as wet etching, can be performed to etch the oxide layer 104a and the patterned insulating layer 103p, thereby exposing the sidewalls of the patterned top semiconductor layer 104p. Furthermore, the insulating layer 103a can be simultaneously removed and thinned to expose the top surface of the underlying bottom semiconductor layer 102. In one embodiment, because wet etching is a non-anisotropic etching process, it simultaneously causes lateral erosion of the bottom mask layer 210, resulting in the shrinkage of the sidewalls of the bottom mask layer 210 to form shrinkage sidewalls 210s. In another embodiment, the patterned insulating layer 103p is also affected by lateral erosion, causing its sidewalls to shrink. Furthermore, the degree of lateral erosion on the upper half of the sidewalls of the patterned insulating layer 103p is greater than that on the lower half, resulting in an undercut structure. For example, after a wet etching process is performed, the sidewalls of the patterned insulating layer 103p will include concave curved sidewalls 103s.

Figure 6 is a cross-sectional schematic diagram illustrating a stage of a semiconductor device manufacturing method according to an embodiment of the present disclosure, wherein a first epitaxial layer covers the sidewalls of the patterned top semiconductor layer and the sidewalls of the patterned insulating layer. Referring to Figure 6, after the patterned top semiconductor layer 104p and the patterned insulating layer 103p are formed as described above, a first epitaxial layer 410 is formed on the bottom semiconductor layer 102 under the cover of the patterned masking layer 200p. The first epitaxial layer 410 can be formed by methods such as molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydrogen vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable methods. The epitaxy time can be appropriately controlled to determine the height of the first epitaxial layer 410 for subsequent epitaxial processes. At this time, the top surface 410t of the first epitaxial layer 410 is lower than the bottom surface 220b of the top masking layer 220. In one embodiment, the top surface 410t of the first epitaxial layer 410 can be higher than the bottom surface 104b of the patterned top semiconductor layer 104p. The presence of the patterned masking layer 200p prevents the formation of the first epitaxial layer 410 on the top surface of the patterned masking layer 200p, thereby avoiding the formation of a step difference in different regions of the first epitaxial layer 410.

The material or doping concentration of the first epitaxial layer 410 can be substantially the same as one or both of the bottom semiconductor layer 102 and the patterned top semiconductor layer 104p. Therefore, there may not be a significant interface between the first epitaxial layer 410, the bottom semiconductor layer 102, and the patterned top semiconductor layer 104p. However, if the material or doping concentration of the first epitaxial layer 410 and one or both of the bottom semiconductor layer 102 and the patterned top semiconductor layer 104p are substantially different, then there is an interface between the first epitaxial layer 410, the bottom semiconductor layer 102, and the patterned top semiconductor layer 104p. For example, the interface can be identified by analyzing the first epitaxial layer 410, the bottom semiconductor layer 102, and the patterned top semiconductor layer 104p using secondary ion mass spectrometry (SIMS).

Figure 7 is a cross-sectional schematic diagram illustrating a stage of a semiconductor device manufacturing method according to an embodiment of the present disclosure, wherein a second epitaxial layer is formed on a patterned top semiconductor layer and a first epitaxial layer. Referring to Figure 7, in one embodiment, during the formation of the first epitaxial layer 410, since the patterned insulating layer 103p includes concave curved sidewalls 103s, and the epitaxial deposition rates of the bottom semiconductor layer 102 and the concave curved sidewalls 103s are different, a pore 103v is formed between the first epitaxial layer 410 and the concave curved sidewalls 103s of the patterned insulating layer 103p. In one embodiment, the maximum size of the pore 103v may be less than 50 nanometers (nm).

After the first epitaxial layer 410 is formed, the patterned masking layer 200p can be removed to expose a top surface of the patterned top semiconductor layer 104p. In one embodiment, the thickness of the first epitaxial layer 410 can be approximately equal to the first overall thickness D1 of the top semiconductor layer 104 and the insulating layer 103 to obtain a substantially flat surface and avoid the formation of significant step differences. Generally, in order to eliminate the step differences generated by the epitaxial layer, the thickness of the epitaxial layer that needs to be removed by the chemical mechanical polishing process is typically 6 to 12 times the step difference height. By making the thickness of the first epitaxial layer 410 substantially equal to the first overall thickness D1 of the top semiconductor layer 104 and the insulating layer 103, the planarization process, such as chemical mechanical planarization (CMP), for the first epitaxial layer 410 can be omitted, thereby reducing the complexity of the process.

Referring again to Figure 7, after removing the patterned masking layer 200p, a second epitaxial layer 420 is formed on top of the patterned top semiconductor layer 104p and the first epitaxial layer 410. The material used to form the second epitaxial layer 420 can be the same as, but is not limited to, the material used to form the first epitaxial layer 410. The method for forming the second epitaxial layer 420 can be, for example, molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydroxide vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable methods, but is not limited to these. The second epitaxial layer 420 has a second thickness D2, wherein the difference between the second thickness D2 and the first overall thickness D1 is not too significant, and the ratio of the second thickness D2 to the first overall thickness D1 is between 2 and 30. In one embodiment, the second thickness D2 of the second epitaxial layer 420 can be, for example, 6.4 micrometers (μm). Regarding the second thickness D2, if the ratio of the second thickness D2 to the first overall thickness D1 is greater than 30, the thickness of the second epitaxial layer 420 is much greater than the first overall thickness D1 and the step difference that may be formed by the aforementioned steps. Therefore, even if the second epitaxial layer 420 is formed directly without the patterned masking layer 200p, the corresponding step difference will not significantly cause surface unevenness of the second epitaxial layer 420.

Because the epitaxial conditions of the concave curved sidewall 103s of the patterned insulating layer 103p are inconsistent with the epitaxial conditions of the surface of the bottom semiconductor layer 102, or because there are lattice defects or pores 103v next to the concave curved sidewall 103s of the patterned insulating layer 103p, it is not easy to form a lattice arrangement consistent with other regions when the first epitaxial layer 410 is deposited near the concave curved sidewall 103s of the patterned insulating layer 103p. In one embodiment, a lattice defect (not shown) is formed in the first epitaxial layer 410 next to the concave curved sidewall 103s of the patterned insulating layer 103p, and the lattice defect extends along the deposition direction of the second epitaxial layer 420, so that a longitudinally extending lattice defect 430 is formed in the region of the second epitaxial layer 420 located directly above the concave curved sidewall 103s.

Figure 8 is a cross-sectional view of a semiconductor device 10 according to one embodiment of the present invention. As shown in Figure 8, the semiconductor device 10 includes, from bottom to top, a substrate 101, a bottom semiconductor layer 102, a patterned insulating layer 103p, and a patterned top semiconductor layer 104p. A first epitaxial layer 410 is disposed on the bottom semiconductor layer 102, and the sidewalls of the first epitaxial layer 410 are adjacent to the sidewalls of the patterned insulating layer 103p and the sidewalls of the patterned top semiconductor layer 104p. A second epitaxial layer 420 is disposed on the patterned top semiconductor layer 104p and the first epitaxial layer 410.

Referring to Figure 8, the second epitaxial layer 420 can be divided into three regions: the first region 510 is located directly above the patterned insulating layer 103p; the second region 520 is located directly above the first epitaxial layer 410 and is laterally separated from the patterned insulating layer 103p; and the boundary region 530 is located between the first region 510 and the second region 520, and is located directly above the concave curved sidewall 103s of the patterned insulating layer 103p. In one embodiment, due to their different structures, the first region 510 and the second region 520 can be provided with semiconductor devices of different properties. Additionally, as mentioned earlier, the second epitaxial layer 420 located directly above the concave curved sidewall 103s of the patterned insulating layer 103p has a lattice defect 430. Therefore, the junction region 530 has a longitudinally extending lattice defect, which means that no semiconductor device will be placed in the junction region 530.

Referring again to Figure 8, in one embodiment, by providing a patterned insulating layer 103p directly below the first region 510, leakage current can be avoided between the bottom semiconductor layer 102 and the second epitaxial layer 420. Therefore, the first semiconductor element 610 provided in the first region 510 can be a planar transistor. As shown in Figure 8, the first semiconductor element 610a and the first semiconductor element 610b can be the same or different types of semiconductor elements. For example, the first semiconductor element 610a can be a P-type metal-oxide-semiconductor field-effect transistor (PMOS), whose source S, gate G and drain D are all provided on the surface of the first semiconductor element 610a, and the source S and drain D are respectively provided on both sides of the gate G. The first semiconductor element 610b can be an N-type metal-oxide-semiconductor field-effect transistor (NMOS). According to one embodiment, its source S, gate G, and drain D are also disposed on the surface of the first semiconductor element 610b, with the source S and drain D respectively disposed on both sides of the gate G. When the channels of the first semiconductor elements 610a and 610b are turned on, the current flows horizontally between the source S and the drain D. There is no patterned insulating layer 103p below the second region 520, allowing the current to flow vertically in the second region 520. Therefore, the second semiconductor element 620 disposed in the second region 520 can be a vertical transistor. According to one embodiment, the source S and gate G are disposed on the surface of the device, while the drain D is disposed within the bottom semiconductor layer 102. When the channel of the second semiconductor device 620 is turned on, the current flows vertically between the source S and the drain D in a vertical direction. The term "planar transistor" as used in this disclosure refers to a transistor in which both the source and drain are located on the surface of the device, and the current flows in a planar direction during operation. In some embodiments, planar transistors include N-type double-diffused metal-oxide-semiconductor field-effect transistors (N-DMOS), P-type double-diffused metal-oxide-semiconductor field-effect transistors (P-DMOS), complementary metal-oxide-semiconductor field-effect transistors (CMOS), horizontally double-diffused metal-oxide-semiconductor field-effect transistors (LDMOS), or N-type/P-type metal-oxide-semiconductor field-effect transistors (N/PMOS), but are not limited thereto. The term "vertical transistor" as used in this disclosure refers to a transistor in which the source and drain are respectively disposed on the surface and bottom of the device, and the current flows in the vertical direction during operation. In some embodiments, vertical transistors include, but are not limited to, vertical dual-diffusion MOSFETs (VDMOS), trench MOSFETs, split-gate trench MOSFETs (SGT MOSFETs), or super-junction MOSFETs.

Referring again to Figure 8, in one embodiment, a deep trench isolation structure 515 may be further provided on both sides of the first semiconductor element 610 in the first region 510. The deep trench isolation structure 515 can be formed by first forming a patterned trench mask layer 200 on the second epitaxial layer 420, then etching the second epitaxial layer 420 under the trench mask layer 200 to form a deep trench, and finally filling it with an insulating material (e.g., silicon oxide). The deep trench isolation structure 515 can prevent leakage current from occurring between the first semiconductor elements 610 in the first region 510, especially between planar transistors, during operation.

According to the embodiments disclosed herein, when forming a semiconductor device with a partial SOI in a certain region, by covering the top semiconductor layer and the insulating layer with a masking layer, a step difference can be avoided on the top semiconductor layer during the formation of the epitaxial layer, thus reducing the complexity of subsequent processes. This effect is particularly significant when the ratio of the second thickness of the second epitaxial layer to the first overall thickness of the top semiconductor layer and the insulating layer is 2 to 30. The semiconductor device of this invention can simultaneously accommodate different types of semiconductor elements, such as planar transistors and vertical transistors. Furthermore, the insulation layer disposed within the semiconductor device effectively prevents leakage current between the bottom semiconductor layer and the second epitaxial layer, facilitating the design of semiconductor devices for various applications. The above description is merely a preferred embodiment of the invention, and all equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention.

10: Semiconductor Device 101: Substrate 102: Bottom Semiconductor Layer 103: Insulation Layer 103a: Thinned Insulation Layer 103p: Patterned Insulation Layer 103s: Concave Sidewall 103v: Pore 104: Top Semiconductor Layer 104a: Oxide Layer 104b: Bottom Surface 104p: Patterned Top Semiconductor Layer 110: Substrate 200: Mask Layer 200p: Patterned Mask Layer 210: Bottom Mask Layer 210s: Sidewall 220: Top Mask Layer 220b: Bottom Surface 300: Photoresist Layer 300p: Patterned Photoresist Layer 410: First epitaxial layer; 410t: Top surface; 420: Second epitaxial layer; 430: Lattice defect; 510: First region; 515: Deep trench isolation structure; 520: Second region; 530: Junction region; 610, 610a, 610b: First semiconductor device; 620: Second semiconductor device; D1: First overall thickness; D2: Second thickness; D: Drain; G: Gate; S: Source.

To facilitate understanding of the following text, the figures and detailed descriptions should be consulted while reading this disclosure. Specific embodiments herein, along with corresponding figures, are used to explain in detail the specific embodiments of this disclosure and to elucidate the working principles of these embodiments. Furthermore, for clarity, features in the figures may not be drawn to scale, and the dimensions of some features in certain figures may be intentionally enlarged or reduced. Figure 1 is a schematic cross-sectional view illustrating a stage of a semiconductor device manufacturing method according to an embodiment of this disclosure, wherein the substrate includes at least a bottom semiconductor layer, an insulating layer, a top semiconductor layer, and a masking layer. Figure 2 is a schematic cross-sectional view of a stage of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein the masking layer includes at least a photoresist layer. Figure 3 is a schematic cross-sectional view of a stage of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein the top semiconductor layer and the insulating layer are patterned to form a patterned top semiconductor layer and a patterned insulating layer. Figure 4 is a schematic cross-sectional view of a stage of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein an oxide layer is formed on the sidewalls of the patterned top semiconductor layer. Figure 5 is a schematic cross-sectional view of a stage of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein the sidewalls of the patterned insulating layer include curved sidewalls. Figure 6 is a schematic cross-sectional view of a stage of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a first epitaxial layer covers the sidewalls of the patterned top semiconductor layer and the sidewalls of the patterned insulating layer. Figure 7 is a schematic cross-sectional view of a stage of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a second epitaxial layer is formed on the patterned top semiconductor layer and the first epitaxial layer. Figure 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

10: Semiconductor Devices

101: Base

102: Bottom Semiconductor Layer

103p: Patterned Insulation Layer

103s: Concave sidewalls

104p: Patterned top semiconductor layer

110:Substrate

410: First epitaxial layer

420: Second epitaxial layer

430: Lattice Defects

510: District 1

515: Deep trench isolation structure

520: Second District

530: Border Area

610a, 610b: First semiconductor device

620: Second Semiconductor Component

D: Dījī

G: Gate Extreme

S: source

Claims (20)

A method for manufacturing a semiconductor device includes: providing a substrate, wherein the substrate sequentially includes a bottom semiconductor layer, an insulating layer, and a top semiconductor layer from bottom to top, wherein the insulating layer and the top semiconductor layer together include a first overall thickness; forming a patterned mask layer on the substrate, wherein the patterned mask layer includes a bottom mask layer and a top mask layer; and etching the top semiconductor layer and the insulating layer under the cover of the patterned mask layer to form a patterned top semiconductor layer and a patterned insulating layer. Under the cover of the patterned masking layer, a first epitaxial layer is formed on the bottom semiconductor layer, and the first epitaxial layer covers the sidewalls of the patterned top semiconductor layer and the sidewalls of the patterned insulating layer, wherein a top surface of the first epitaxial layer is lower than a bottom surface of the top masking layer; the patterned masking layer is removed to expose a top surface of the patterned top semiconductor layer; and a second epitaxial layer is formed on the patterned top semiconductor layer and the first epitaxial layer, wherein the second epitaxial layer includes a second thickness, and the ratio of the second thickness to the first overall thickness is 2 to 30. The method of manufacturing a semiconductor device as described in claim 1, further comprising, before forming the first epitaxial layer above the bottom semiconductor layer, oxidizing the sidewalls of the patterned top semiconductor layer to form an oxide layer. The method of manufacturing a semiconductor device as described in claim 2, wherein after forming the oxide layer, further includes: performing a wet etching process to etch the oxide layer and the patterned insulating layer. The method of manufacturing a semiconductor device as described in claim 3, wherein the sidewalls of the bottom mask layer are etched inward during the wet etching process. The method of manufacturing a semiconductor device as described in claim 3, wherein after performing the wet etching process, the insulating layer includes a concave curved sidewall. The method of manufacturing a semiconductor device as described in claim 1, wherein after the first epitaxial layer is formed, a pore is included between the sidewall of the patterned insulating layer and the first epitaxial layer. The method of manufacturing a semiconductor device as described in claim 1 further includes: forming a mask layer on the substrate; forming a patterned photoresist layer on the mask layer; etching the mask layer under the cover of the patterned photoresist layer to form a patterned mask layer; and removing the patterned photoresist layer after forming the patterned top semiconductor layer and the patterned insulating layer. The method of manufacturing a semiconductor device as described in claim 1, wherein the patterned insulating layer and a thinned insulating layer are formed when the insulating layer is etched. The method of manufacturing a semiconductor device as described in claim 8, wherein after removing the patterned mask layer, further includes removing the thinned insulating layer to expose a top surface of the bottom semiconductor layer. The method of manufacturing a semiconductor device as described in claim 1, wherein the second epitaxial layer includes a first region and a second region, the first region being located directly above the patterned insulating layer, the second region being laterally separated from the patterned insulating layer, and the manufacturing method further includes: forming a first semiconductor element and a second semiconductor element, respectively located within the first region and the second region, wherein the first semiconductor element is different from the second semiconductor element. The method of manufacturing a semiconductor device as described in claim 10 further includes: forming a plurality of deep trench isolation structures in the first region. A semiconductor device includes: a bottom semiconductor layer; a patterned insulating layer disposed on the bottom semiconductor layer and covering a portion of the bottom semiconductor layer, wherein the patterned insulating layer includes an upwardly concave curved sidewall; and a patterned top semiconductor layer disposed on the bottom semiconductor layer; a first epitaxial layer disposed on the bottom semiconductor layer, wherein the sidewall of the first epitaxial layer is adjacent to the sidewall of the patterned insulating layer and the sidewall of the patterned top semiconductor layer; and a second epitaxial layer disposed on the patterned top semiconductor layer and the first epitaxial layer, and including: A first region is located directly above the patterned insulating layer; a second region is located directly above the first epitaxial layer and is laterally separated from the patterned insulating layer; and a boundary region is located between the first region and the second region and is located directly above the concave curved sidewall of the patterned insulating layer. The semiconductor device as described in claim 12 further includes: a first semiconductor element disposed in the first region; and a second semiconductor element disposed in the second region and different from the first semiconductor element. The semiconductor device as described in claim 13 further includes a plurality of deep trench isolation structures disposed on opposite sides of the first semiconductor element. The semiconductor device as described in claim 13, wherein the first semiconductor element includes a planar transistor and the second semiconductor element includes a vertical transistor. The semiconductor device as described in claim 15, wherein the planar transistor is selected from N-type double-diffused metal-oxide-semiconductor field-effect transistor (N-DMOS), P-type double-diffused metal-oxide-semiconductor field-effect transistor (P-DMOS), complementary metal-oxide-semiconductor field-effect transistor (CMOS), laterally double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS), or N-type/P-type metal-oxide-semiconductor field-effect transistor (N/PMOS). The semiconductor device as described in claim 15, wherein the vertical transistor is selected from a vertical double-diffusion MOSFET (VDMOS), a trench MOSFET, a split-gate trench MOSFET (SGT MOSFET), or a super-junction MOSFET. The semiconductor device as described in claim 12 further includes a pore or a lattice defect located between the concave curved sidewall of the patterned insulating layer and the first epitaxial layer. The semiconductor device as described in claim 18, wherein the maximum size of the pore is less than 50 nanometers. The semiconductor device as described in claim 12, wherein the junction region includes longitudinally extending lattice defects.