TWI910770B - Semiconductor structure and its preparation method - Google Patents

Abstract

This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate; and multiple resistive switching devices (RSDs) disposed on the substrate. Each RSD includes: a lower electrode disposed on the substrate; multiple resistive switching layers disposed around the lower electrode and in contact with its sidewalls; and multiple upper electrodes enclosed by the resistive switching layers and isolated from the lower electrode by the resistive switching layers. This method increases the resistive switching area while reducing the planar area occupied by the Resistive Random Access Memory (RRAM), which is beneficial for increasing RRAM density.

Description

Semiconductor structure and its preparation method

This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method.

Resistive Random Access Memory (RRAM) is a type of non-volatile memory that uses the variable resistance of materials to store information. It has advantages such as low power consumption, high density, fast read and write speed, and good durability.

Existing RRAMs are planar RRAMs, and the resistive switching area is determined by the planar area of the RRAM. The resistive switching area is limited by the size of the RRAM itself, which is not conducive to miniaturizing the RRAM size while obtaining a large resistive switching area. Furthermore, achieving a 1TnR device structure would significantly increase the area.

This invention provides a semiconductor structure and a method for its fabrication, thereby at least solving the above-mentioned technical problems existing in the prior art.

According to a first aspect of the present invention, a semiconductor structure is provided, comprising: a substrate; and a plurality of resistive switching devices disposed on the substrate, wherein each of the resistive switching devices comprises: a lower electrode disposed on the substrate; a plurality of resistive switching layers disposed around the lower electrode and in contact with the sidewalls of the lower electrode; and a plurality of upper electrodes encapsulated by the resistive switching layers and isolated from the lower electrode by the resistive switching layers.

In one embodiment, multiple resistive switching devices are arranged along a first direction and a second direction, wherein the multiple resistive switching devices are arranged in a row along the first direction, and multiple resistive switching devices are arranged in a column along the second direction, with adjacent columns and adjacent rows of resistive switching devices staggered, and resistive switching devices separated by a column and a row respectively aligned with each other; the semiconductor structure further includes: multiple first bit lines extending along the first direction and arranged along the second direction, each first bit line being connected to one upper electrode of multiple resistive switching devices in each row, and the opposite upper electrodes of resistive switching devices in adjacent rows being connected to the same first bit line; multiple second bit lines extending along the second direction and arranged along the first direction, each second bit line being connected to one upper electrode of multiple resistive switching devices in each column, and the opposite upper electrodes of resistive switching devices in adjacent columns being connected to the same second bit line.

In one embodiment, the method further includes: a first dielectric layer and a second dielectric layer sequentially stacked on the substrate; the lower electrode penetrates the first dielectric layer and the second dielectric layer, and the resistive switching layer penetrates the second dielectric layer and is located on the first dielectric layer; wherein the materials of the first dielectric layer and the second dielectric layer have a high selectivity.

In one embodiment, the method further includes: a third dielectric layer located on the lower electrode, the third dielectric layer completely covering the lower electrode; and a fourth dielectric layer, the fourth dielectric layer at least covering the surfaces of the third dielectric layer, the resistive switching layer, and the upper electrode; wherein the materials of the third dielectric layer and the fourth dielectric layer have a high selectivity.

In one embodiment, in a projection perpendicular to the plane of the substrate, the shape of the lower electrode includes a rectangle or a circle, and the shape of the upper electrode includes a rectangle, a circle, or an ellipse.

According to a second aspect of the present invention, a method for fabricating a semiconductor structure is provided, the method comprising: providing a substrate; forming a plurality of resistive switching devices on the substrate, wherein forming each resistive switching device comprises: forming a lower electrode on the substrate; forming a plurality of resistive switching layers around the lower electrode, the resistive switching layers contacting the sidewalls of the lower electrode; and forming a plurality of upper electrodes enclosed by the resistive switching layers, the upper electrodes being isolated from the lower electrodes through the resistive switching layers.

In one embodiment, multiple resistive switching devices are arranged along a first direction and a second direction, wherein the multiple resistive switching devices are arranged in a row along the first direction, and multiple resistive switching devices are arranged in a column along the second direction, with adjacent columns and adjacent rows of resistive switching devices staggered, and resistive switching devices separated by a column and a row respectively aligned with each other; the method includes: after forming the resistive switching devices, forming multiple first bit lines extending along the first direction and arranged along the second direction, each first bit line being connected to an upper electrode of the multiple resistive switching devices in each row, and the opposite upper electrodes of the resistive switching devices in adjacent rows being connected to the same first bit line. Multiple second bit lines are formed that extend along the second direction and are arranged along the first direction. Each second bit line is connected to one upper electrode of each column of multiple resistive switching devices, and the opposite upper electrodes of adjacent columns of resistive switching devices are connected to the same second bit line.

In one embodiment, the preparation method includes: after providing the substrate, forming a first dielectric layer and a second dielectric layer stacked sequentially on the substrate; wherein the materials of the first dielectric layer and the second dielectric layer have a high selectivity.

In one embodiment, forming the lower electrode includes: forming a first trench penetrating the first dielectric layer and the second dielectric layer; forming the lower electrode filling the first trench; and forming the resistive switching layer includes: forming a second trench penetrating the second dielectric layer, the second trench ending on the first dielectric layer; and forming the resistive switching layer covering the sidewalls and bottom of the second trench.

In one embodiment, the method further includes: forming a third dielectric layer on the lower electrode, the third dielectric layer completely covering the lower electrode; forming a fourth dielectric layer, the fourth dielectric layer at least covering the surfaces of the third dielectric layer, the resistive switching layer, and the upper electrode; wherein the materials of the third dielectric layer and the fourth dielectric layer have a high selectivity.

In one embodiment, in a projection perpendicular to the plane of the substrate, the shape of the lower electrode includes a rectangle or a circle, and the shape of the upper electrode includes a rectangle, a circle, or an ellipse.

The semiconductor structure and its fabrication method of this invention form multiple resistive switching layers around the lower electrode, and then form the upper electrode within the resistive switching layers. Thus, the resistive switching area is determined by the area of the region in contact between the resistive switching layer and the lower electrode. Because multiple resistive switching layers are formed in this invention, it is equivalent to forming a 1TnR structure, thereby increasing the resistive switching area and reducing the planar area occupied by the variable resistive memory (RRAM), which is beneficial to improving the RRAM density.

It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description.

To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art to which this invention pertains without making progressive changes are within the scope of protection of this invention.

This invention provides a semiconductor structure. Figure 1 is a top view of the semiconductor structure provided by this invention, Figure 2 is a cross-sectional view along the A-A’ direction in Figure 1, and Figure 3 is a cross-sectional view along the B-B’ direction in Figure 1.

As shown in Figures 1 to 3, the semiconductor structure includes:

Substrate 10;

Multiple resistive switching devices 20 are located on the substrate 10, wherein each resistive switching device 20 includes:

The lower electrode 21 is located on the substrate 10;

Multiple resistive switching layers 22 are respectively located around the lower electrode 21 and in contact with the sidewall of the lower electrode 21;

Multiple upper electrodes 23 are wrapped by a resistive switching layer 22 and isolated from the lower electrode 21 by the resistive switching layer 22.

In one embodiment, the substrate 10 may be a single-element semiconductor material substrate (e.g., silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., germanium-silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, etc.

Multiple active regions 101 are formed within the substrate 10.

As shown in Figures 2 and 3, the semiconductor structure further includes a first interlayer dielectric layer 31 and a second interlayer dielectric layer 32 sequentially stacked on the substrate 10. The material of the first interlayer dielectric layer 31 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and the second interlayer dielectric layer 32 can be a metal interlayer dielectric layer, such as aluminum oxide or zinc oxide.

The semiconductor structure also includes: a first contact plug 40 located within the first interlayer dielectric layer 31; a metal layer 51 and a source line 52 located within the second interlayer dielectric layer 32, wherein the metal layer 51 and the source line 52 are connected to the substrate 10 through the first contact plug 40, the metal layer 51 is connected to the lower electrode 21 of the resistive switching device 20, and the source line 52 is isolated from the resistive switching device 20.

As shown in Figure 2, the semiconductor structure further includes a gate structure 102 located on the surface of the substrate 10. The gate structure 102 is located within the first interlayer dielectric layer 31. The gate structure 102 includes a gate dielectric layer (not shown in the figure) and a gate conductive layer (not shown in the figure) located on the gate dielectric layer. The sidewalls of the gate structure 102 may also be covered by a sidewall structure (not shown in the figure).

In one embodiment, the semiconductor structure further includes: a first dielectric layer 61 and a second dielectric layer 62 stacked sequentially on a substrate 10; a lower electrode 21 penetrating the first dielectric layer 61 and the second dielectric layer 62; a resistive switching layer 22 penetrating the second dielectric layer 62 and located on the first dielectric layer 61; wherein the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity.

As shown in Figure 2, specifically, the first medium layer 61 is located on the second interlayer medium layer 32.

In this embodiment of the invention, the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity. Thus, when the trenches for forming the resistive switching layer 22 are etched into the second dielectric layer 62, the first dielectric layer 61 can act as an etching stop layer, preventing over-etching to the underlying metal layer 51, and effectively controlling the uniformity of the trench depth.

In one embodiment, the material of the first dielectric layer 61 includes, but is not limited to, silicon nitride, and the material of the second dielectric layer 62 includes, but is not limited to, silicon dioxide. However, it should be explained that the materials of the first dielectric layer 61 and the second dielectric layer 62 are not limited to these, as long as the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity and have an insulating effect.

As shown in Figure 2, each resistive switching device 20 includes a lower electrode 21, multiple resistive switching layers 22, and multiple upper electrodes 23.

The materials of the lower electrode 21 and the upper electrode 23 include conductive materials such as titanium nitride or tungsten, and the materials of the resistive switching layer 22 include transition metal oxides, specifically, such as iron oxide, aluminum monoxide, etc.

Figure 4a is a top view of the resistive switching device provided in the embodiment of the present invention.

In one embodiment, as shown in Figure 4a, the resistive switching device 20 has a 1T4R structure, which includes four resistive switching layers 22, thus forming four resistors. In other embodiments, the resistive switching device 20 can have a 1T3R or 1T2R structure, meaning that only three or two resistive switching layers 22 can be formed around the lower electrode 21. In still other embodiments, the resistive switching device 20 can have more than four resistive switching layers 22.

In traditional planar RRAM, forming an nR structure requires n transistors, which increases the device structure area by almost n times. In this embodiment of the invention, multiple resistors (R) can be integrated on a single transistor (T), which is equivalent to forming an nR structure. The area of the RRAM in this invention is only one-nth of that of a planar RRAM, reducing the planar area occupied by the RRAM and thus improving the RRAM density.

As shown in Figure 4a, multiple resistive switching devices 20 are arranged along a first direction and a second direction. The multiple resistive switching devices 20 are arranged in a row along the first direction and in a column along the second direction. The resistive switching devices 20 in adjacent columns and rows are staggered, and the resistive switching devices 20 that are separated by a column and a row are aligned with each other.

As shown in Figure 4a, the distance h1 between two resistive switching devices 20 arranged diagonally in two adjacent columns or two adjacent rows is equal to the distance h2 between two adjacent source lines 52.

The angle between the extending directions of two adjacent columns or rows of diagonally arranged resistive switching devices 20 and the first direction is α, where α ranges from 30° to 60°, and in a preferred embodiment, α is 45°. When the angle α is within this range, the packing density of the resistive switching devices 20 can be increased.

Figures 4b to 4d are top views of resistive switching devices provided in other embodiments of the present invention.

In one embodiment, in a projection perpendicular to the plane of the substrate 10, the shape of the lower electrode 21 includes a rectangle or a circle, and the shape of the upper electrode 23 includes a rectangle, a circle, or an ellipse.

Specifically, as shown in Figure 4a, the lower electrode 21 is rectangular and the upper electrode 23 is also rectangular; as shown in Figure 4b, the lower electrode 21 is circular and the upper electrode 23 is rectangular; as shown in Figure 4c, the lower electrode 21 is rectangular and the upper electrode 23 is elliptical; as shown in Figure 4d, the lower electrode 21 is circular and the upper electrode 23 is circular.

In one embodiment, the shape of the resistive switching layer 22 is the same as that of the upper electrode 23.

As shown in Figure 2, the semiconductor structure also includes a third dielectric layer 63 located on the lower electrode 21, the third dielectric layer 63 completely covering the lower electrode 21;

The fourth dielectric layer 64 covers at least the surfaces of the third dielectric layer 63, the resistive switching layer 22, and the upper electrode 23; wherein the materials of the third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity.

Because the resistive switching layer 22 is generally thin, without the third dielectric layer 63, the upper electrode 23 and the lower electrode 21 would easily come into contact, leading to a short circuit. In this embodiment, the third dielectric layer 63 completely covers the lower electrode 21, thus isolating the upper electrode 23 and the lower electrode 21 and preventing a short circuit.

The third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity ratio. Thus, when the trench for forming the first line is etched into the fourth dielectric layer 64, the third dielectric layer 63 will not be etched away. Therefore, the third dielectric layer 63 can still isolate the upper electrode 23 and the lower electrode 21.

In one embodiment, the material of the third dielectric layer 63 includes, but is not limited to, silicon nitride, and the material of the fourth dielectric layer 64 includes, but is not limited to, silicon dioxide. However, it should be explained that the materials of the third dielectric layer 63 and the fourth dielectric layer 64 are not limited to these, as long as the materials of the third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity and have an insulating function.

In one embodiment, the fourth medium layer 64 also covers the surface of the second medium layer 62.

As shown in Figures 1 and 2, the semiconductor structure further includes: a plurality of first lines 71 extending along a first direction and arranged along a second direction, each first line 71 being connected to an upper electrode 23 of a plurality of resistive switching devices 20 in each row, and the opposite upper electrodes 23 of adjacent resistive switching devices 20 being connected to the same first line 71.

The first line 71 penetrates the fourth medium layer 64.

The materials of the first line 71 include, but are not limited to, metals such as tungsten and copper.

As shown in Figures 1 and 3, the semiconductor structure also includes a plurality of second contact plugs 80, which are located on the upper electrode 23 that is not in contact with the first line 71.

In one embodiment, the upper surface of the second contact plug 80 is higher than the upper surface of the first line 71, which ensures that there is a certain gap between the second line 72 formed on the second contact plug 80 and the first line 71, so that they will not come into contact and cause a short circuit.

As shown in Figures 1 and 3, the semiconductor structure also includes: a fifth dielectric layer 65, located on the fourth dielectric layer 64;

Multiple second bit lines 72 extending along a second direction and arranged along a first direction are provided. Each second bit line 72 is connected to an upper electrode 23 of multiple resistive switching devices 20 in each column. The opposite upper electrodes 23 of adjacent columns of resistive switching devices 20 are connected to the same second bit line 72.

Specifically, the second position line 72 penetrates the fifth dielectric layer 65 and is located on the second contact plug 80.

The materials for the second line 72 include, but are not limited to, metals such as tungsten and copper.

In one embodiment, the first bit line 71 and the second bit line 72 can enable the interconnection and array operation of the resistive switching device 20.

This invention provides a 1TnR structure, which significantly increases device density. However, the interconnection of n RRAMs requires n layers of metal interconnects. To ensure that each resistive switching device 20 can be connected without short-circuiting, the 1TnR structure typically requires n layers of bit line interconnects. For example, to form a 1T4R structure, four resistors typically require four layers of bit lines, which in turn require four layers of interconnects. The 1T4R structure in this invention uses a layered staggered arrangement of the first bit line 71 and the second bit line 72, requiring only two layers of bit lines to connect the four resistors without short circuits. This reduces the number of n/2 layers of bit lines, which in turn reduces the number of n/2 layers of interconnections. Since each layer of interconnection involves a complex and costly process with numerous photomask steps, reducing interconnections significantly reduces the process and cost.

This invention also provides a method for fabricating a semiconductor structure. Figure 5 is a flowchart of the method for fabricating the semiconductor structure provided by this invention. Referring to Figure 5, the fabrication method includes the following steps:

Step S501: Provide the substrate;

Step S502: Forming multiple resistive switching devices on a substrate, wherein forming each resistive switching device includes: forming a lower electrode on the substrate; forming multiple resistive switching layers around the lower electrode, the resistive switching layers being in contact with the sidewalls of the lower electrode; forming multiple upper electrodes wrapped by the resistive switching layers, the upper electrodes being isolated from the lower electrodes through the resistive switching layers.

The method for fabricating the semiconductor structure provided by the present invention will be further described in detail below with reference to specific embodiments. Figures 6a to 18c are schematic diagrams of the semiconductor structure provided by the present invention during the fabrication process, wherein Figures 6a, 7a, 8a to 18a are top views of the semiconductor structure during the fabrication process, and Figures 6b, 7b, 8b to 17b, 17c, 18b and 18c are cross-sectional views of the semiconductor structure during the fabrication process.

First, referring to Figures 6a and 6b, perform step S501 to provide substrate 10.

As shown in Figure 3, multiple active regions 101 are formed within the substrate 10.

In one embodiment, the substrate 10 may be a single-element semiconductor material substrate (e.g., silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., germanium-silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, etc.

Referring again to FIG6b, the fabrication method further includes: forming a grid structure 102 on the surface of a substrate 10. The grid structure 102 includes a grid dielectric layer (not shown in the figure) and a grid conductive layer (not shown in the figure) located on the grid dielectric layer. A sidewall structure (not shown in the figure) may also be covered at the sidewall of the grid structure 102.

A first interlayer dielectric layer 31 is formed on the surface of the substrate 10, and the first interlayer dielectric layer 31 covers the grid structure 102. The material of the first interlayer dielectric layer 31 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

A first contact plug 40 is formed within the first interlayer medium layer 31.

A second interlayer 32 is formed on the first interlayer 31. The second interlayer 32 can be a metal interlayer, such as aluminum oxide, zinc oxide, or other materials.

A metal layer 51 and a source line 52 are formed in the second interlayer dielectric layer 32. The metal layer 51 and the source line 52 are connected to the substrate 10 through the first contact plug 40. The metal layer 51 is connected to the lower electrode of the subsequently formed resistive switching device, and the source line 52 is isolated from the resistive switching device.

Referring again to FIG6b, the method further includes: after providing the substrate 10, forming a first dielectric layer 61 and a second dielectric layer 62 stacked sequentially on the substrate 10; wherein the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity.

Specifically, the first medium layer 61 is located on the second interlayer medium layer 32.

In this embodiment of the invention, the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity. Thus, when the trenches for forming the resistive switching layer are subsequently etched into the second dielectric layer 62, the first dielectric layer 61 can act as an etching stop layer, preventing over-etching to the underlying metal layer and effectively controlling the uniformity of the trench depth.

In one embodiment, the material of the first dielectric layer 61 includes, but is not limited to, silicon nitride, and the material of the second dielectric layer 62 includes, but is not limited to, silicon dioxide. However, it should be explained that the materials of the first dielectric layer 61 and the second dielectric layer 62 are not limited to these, as long as the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity and have an insulating effect.

Next, referring to Figures 7a to 13b, step S502 is performed to form a plurality of resistive switching devices 20 on the substrate 10. The formation of each resistive switching device 20 includes: forming a lower electrode 21 on the substrate 10; forming a plurality of resistive switching layers 22 around the lower electrode 21, with the resistive switching layers 22 in contact with the sidewalls of the lower electrode 21; and forming a plurality of upper electrodes 23 wrapped by the resistive switching layers 22, with the upper electrodes 23 isolated from the lower electrode 21 through the resistive switching layers 22.

Referring to Figures 7a to 9b, forming a lower electrode 21 includes: forming a first trench 201 that penetrates the first dielectric layer 61 and the second dielectric layer 62; and forming a lower electrode 21 that fills the first trench 201.

Referring to Figures 7a and 7b, the first trench 201 is first formed.

In actual operation, a mask layer can be formed on the second dielectric layer 62, and then the mask layer is patterned by photolithography to form the position of the first trench on the mask layer. According to the position of the first trench, the second dielectric layer 62 and the first dielectric layer 61 are etched to transfer the position of the first trench into the second dielectric layer 62 and the first dielectric layer 61 to form the first trench 201.

In one embodiment, the etching process can be a wet etching process or a dry etching process. A dry etching process is preferred. Dry etching processes include, but are not limited to, at least one of ion milling, plasma etching, reactive ion etching, and laser ablation.

Next, referring to Figures 8a and 8b, an initial lower electrode 210 is formed within the first trench 201 and on the surface of the second dielectric layer 62.

Referring to Figures 9a and 9b, the initial lower electrode 210 located on the surface of the second dielectric layer 62 is etched away to form a lower electrode 21 located within the first trench 201.

The material of the lower electrode 21 includes conductive materials such as titanium nitride or tungsten.

Next, referring to Figures 10a to 13b, a resistive switching layer 22 is formed, including: forming a second groove 202 that penetrates the second dielectric layer 62 and stops on the first dielectric layer 61; and forming a resistive switching layer 22 that covers the sidewalls and bottom of the second groove 202.

Specifically, referring to Figures 10a and 10b, a second groove 202 is formed, which is located around the lower electrode 21.

In actual operation, a mask layer can be formed on the second dielectric layer 62, and then the mask layer is patterned by photolithography to form the second trench position on the mask layer. According to the second trench position, the second dielectric layer 62 is etched to transfer the second trench position into the second dielectric layer 62 to form the second trench 202.

In one embodiment, the etching process can be a wet etching process or a dry etching process. A dry etching process is preferred. Dry etching processes include, but are not limited to, at least one of ion milling, plasma etching, reactive ion etching, and laser ablation.

In one embodiment, the materials of the second dielectric layer 62 and the lower electrode 21 have a high selectivity, so that the lower electrode will not be etched off when the second trench is etched.

Next, referring to Figures 11a and 11b, an initial resistive switching layer 220 is formed, which covers the sidewalls and bottom of the second trench 202 and the surface of the second dielectric layer 62.

Next, referring to Figures 12a and 12b, an initial upper electrode 230 is formed, which covers the surface of the initial resistive switching layer 220 and fills the second groove 202.

Next, referring to Figures 13a and 13b, the initial resistive switching layer 220 and the initial upper electrode 230 located on the surface of the second dielectric layer 62 are removed to form the resistive switching layer 22 and the upper electrode 23 located in the second trench 202, thereby forming the resistive switching device 20.

The material of the upper electrode 23 includes conductive materials such as titanium nitride or tungsten, and the material of the resistive switching layer 22 includes transition metal oxides, specifically, such as iron oxide, aluminum monoxide, etc.

In one embodiment, as shown in Figure 13a, the resistive switching device 20 has a 1T4R structure, meaning it includes four resistive switching layers 22. In other embodiments, the resistive switching device 20 can have a 1T3R or 1T2R structure, meaning that only three or two resistive switching layers 22 can be formed around the lower electrode 21. In still other embodiments, the resistive switching device 20 can have more than four resistive switching layers 22.

As shown in Figure 4a, multiple resistive switching devices 20 are arranged along a first direction and a second direction. The multiple resistive switching devices 20 are arranged in a row along the first direction and in a column along the second direction. The resistive switching devices 20 in adjacent columns and rows are staggered, and the resistive switching devices 20 that are separated by a column and a row are aligned with each other.

As shown in Figure 4a, the distance h1 between two resistive switching devices 20 arranged diagonally in two adjacent columns or two adjacent rows is equal to the distance h2 between two adjacent source lines 52.

The angle between the extending directions of two adjacent columns or rows of diagonally arranged resistive switching devices 20 and the first direction is α, where α ranges from 30° to 60°, and in a preferred embodiment, α is 45°. When the angle α is within this range, the packing density of the resistive switching devices 20 can be increased.

In one embodiment, in a projection perpendicular to the plane of the substrate 10, the shape of the lower electrode 21 includes a rectangle or a circle, and the shape of the upper electrode 23 includes a rectangle, a circle, or an ellipse.

Specifically, as shown in Figure 4a, the lower electrode 21 is rectangular and the upper electrode 23 is also rectangular; as shown in Figure 4b, the lower electrode 21 is circular and the upper electrode 23 is rectangular; as shown in Figure 4c, the lower electrode 21 is rectangular and the upper electrode 23 is elliptical; as shown in Figure 4d, the lower electrode 21 is circular and the upper electrode 23 is circular.

In one embodiment, the shape of the resistive switching layer 22 is the same as that of the upper electrode 23.

In this embodiment of the invention, the resistive switching area is determined by the area of the region where the resistive switching layer contacts the lower electrode. Since multiple resistive switching layers are formed in this invention, which is equivalent to forming a 1TnR structure, the resistive switching area is increased while the planar area occupied by the RRAM is reduced, which is beneficial to improving the RRAM density.

Next, referring to Figures 14a to 15b, the fabrication method further includes: forming a third dielectric layer 63 on the lower electrode 21, the third dielectric layer 63 completely covering the lower electrode 21.

Specifically, a third dielectric layer 63 is first formed that covers the second dielectric layer 62, the lower electrode 21, the resistive switching layer 22, and the upper electrode 23. Then, part of the third dielectric layer 63 is removed, so that the remaining third dielectric layer 63 completely covers the lower electrode 21, but does not cover or partially covers the upper electrode 23.

Because the resistive switching layer 22 is generally thin, without the third dielectric layer 63, the upper electrode 23 and the lower electrode 21 would easily come into contact, leading to a short circuit. In this embodiment, the third dielectric layer 63 completely covers the lower electrode 21, thus isolating the upper electrode 23 and the lower electrode 21 and preventing a short circuit.

Next, referring to Figures 16a and 16b, a fourth dielectric layer 64 is formed, which at least covers the surfaces of the third dielectric layer 63, the resistive switching layer 22, and the upper electrode 23; wherein the materials of the third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity.

The third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity ratio. Thus, when the trench for forming the first line is etched into the fourth dielectric layer 64, the third dielectric layer 63 will not be etched away. Therefore, the third dielectric layer 63 can still isolate the upper electrode 23 and the lower electrode 21.

In one embodiment, the material of the third dielectric layer 63 includes, but is not limited to, silicon nitride, and the material of the fourth dielectric layer 64 includes, but is not limited to, silicon dioxide. However, it should be explained that the materials of the third dielectric layer 63 and the fourth dielectric layer 64 are not limited to these, as long as the materials of the third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity and have an insulating function.

In one embodiment, the fourth medium layer 64 also covers the surface of the second medium layer 62.

Next, referring to Figures 17a to 17c, wherein Figure 17b is a cross-sectional view along the A-A’ direction in Figure 17a, and Figure 17c is a cross-sectional view along the B-B’ direction in Figure 17a. The manufacturing method further includes: after forming the resistive switching device 20, forming a plurality of first line 71 extending along a first direction and arranged along a second direction, each first line 71 being connected to an upper electrode 23 of a plurality of resistive switching devices 20 in each row, and the opposite upper electrodes 23 of adjacent resistive switching devices 20 being connected to the same first line 71.

In actual operation, a mask layer can be formed on the fourth dielectric layer 64, and then the mask layer is patterned by photolithography to form the position of the first line trench on the mask layer. According to the position of the first line trench, the fourth dielectric layer 64 is etched to transfer the position of the first line trench into the fourth dielectric layer 64 to form the first line trench. Then, the first line trench is filled with metal material to form the first line 71.

The first line 71 penetrates the fourth medium layer 64.

The materials of the first line 71 include, but are not limited to, metals such as tungsten and copper.

As shown in Figures 17a and 17c, the method further includes: forming a second contact plug 80 while forming the first line 71, the second contact plug 80 being located on the upper electrode 23 that is not in contact with the first line 71.

In one embodiment, the upper surface of the second contact plug 80 is higher than the upper surface of the first line 71, which ensures that the second line formed subsequently on the second contact plug 80 has a certain gap with the first line and will not make contact leading to a short circuit.

Next, referring to Figures 18a to 18c, wherein Figure 18b is a cross-sectional view along the A-A' direction in Figure 18a, and Figure 18c is a cross-sectional view along the B-B' direction in Figure 18a. The manufacturing method further includes: forming a plurality of second bit lines 72 extending along a second direction and arranged along a first direction, each second bit line 72 being connected to an upper electrode 23 of a plurality of resistive switching devices 20 in each column, and the opposite upper electrodes 23 of adjacent columns of resistive switching devices 20 being connected to the same second bit line 72.

In actual operation, a mask layer can be formed on the fifth dielectric layer 65, and then the mask layer is patterned by photolithography to form the position of the second bit line trench on the mask layer. According to the position of the second bit line trench, the fifth dielectric layer 65 is etched to transfer the position of the second bit line trench into the fifth dielectric layer 65 to form the second bit line trench. Then, the second bit line trench is filled with metal material to form the second bit line 72.

Specifically, the second position line 72 penetrates the fifth dielectric layer 65 and is located on the second contact plug 80.

The materials for the second line 72 include, but are not limited to, metals such as tungsten and copper.

In one embodiment, the first bit line 71 and the second bit line 72 can enable the interconnection and array operation of the resistive switching device 20.

It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "multiple" means two or more, unless otherwise expressly and specifically defined.

The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of protection of the aforementioned patent application.

10: Substrate 101: Active Region 102: Gate Structure 20: Resistive Switch 201: First Groove 202: Second Groove 21: Lower Electrode 210: Initial Lower Electrode 22: Resistive Switching Layer 220: Initial Resistive Switching Layer 23: Upper Electrode 230: Initial Upper Electrode 31: First Interlayer Dielectric Layer 32: Second Interlayer Dielectric Layer 40: First Contact Plug 51: Metal Layer 52: Source Line 61: First Dielectric Layer 62: Second Dielectric Layer 63: Third Dielectric Layer 64: Fourth Dielectric Layer 65: Fifth Dielectric Layer 71: First Bit Line 72: Second Bit Line 80: Second Contact Plug a: Angle; h1, h2: Distance; S501～S502: Steps

The above and other objects, features, and advantages of the exemplary embodiments of the present invention will become readily apparent when the following detailed description is read with reference to the accompanying drawings. Several embodiments of the present invention are illustrated in the accompanying drawings by way of example and not limitation, wherein:

In the accompanying figures, the same or corresponding labels indicate the same or corresponding parts.

Figure 1 is a top view of the semiconductor structure provided in this embodiment of the invention;

Figure 2 is a cross-sectional view along the A-A’ direction in Figure 1;

Figure 3 is a cross-sectional view along the B-B’ direction in Figure 1;

Figures 4a to 4d are top views of the resistive switching device provided in the embodiments of the present invention;

Figure 5 is a flowchart of the method for fabricating a semiconductor structure provided in this embodiment of the invention; and

Figures 6a to 18c are schematic diagrams of the semiconductor structure provided in the present invention during the fabrication process.

10: Substrate

101: Active Area

20: Resistive switching devices

21: Lower electrode

22: Resistive Layer

23: Upper electrode

31: First interstitial layer

32: Second intermediate layer

52: Source line

61: First media layer

62: Second median layer

63: Third medial layer

64: Fourth medial layer

65: Fifth medial layer

72: Second line

80: Second contact plug

Claims (9)

A semiconductor structure includes: a substrate; and a plurality of resistive switching devices disposed on the substrate, wherein each resistive switching device includes: a lower electrode disposed on the substrate; the lower electrode being connected to a metal layer, the metal layer being connected to the substrate via a first contact plug; a plurality of mutually spaced resistive switching layers disposed around the lower electrode and in contact with the sidewalls of the lower electrode; and a plurality of upper electrodes being enclosed by the resistive switching layers and isolated from the lower electrode by the resistive switching layers. Multiple resistive switching devices are arranged along a first direction and a second direction, wherein multiple resistive switching devices are arranged in a row along the first direction, multiple resistive switching devices are arranged in a column along the second direction, and resistive switching devices in adjacent columns and adjacent rows are staggered, and resistive switching devices in a column and a row apart are aligned with each other; the semiconductor structure further includes: multiple first lines extending along the first direction and arranged along the second direction, each first line being connected to one of the upper electrodes of multiple resistive switching devices in each row, and the opposite upper electrodes of resistive switching devices in adjacent rows being connected to the same first line; The semiconductor structure includes multiple second bit lines extending along the second direction and arranged along the first direction, each second bit line being connected to one of the upper electrodes of multiple resistive switching devices in each column, and the opposite upper electrodes of adjacent columns of resistive switching devices being connected to the same second bit line; the semiconductor structure further includes multiple second contact plugs, each second contact plug being located on an upper electrode that is not in contact with the first bit line; the upper surface of the second contact plug is higher than the upper surface of the first bit line, and the second bit line is formed on the second contact plug. The semiconductor structure according to claim 1 further includes: a first dielectric layer and a second dielectric layer stacked sequentially on the substrate; the lower electrode penetrates the first dielectric layer and the second dielectric layer, and the resistive switching layer penetrates the second dielectric layer and is located on the first dielectric layer; wherein the materials of the first dielectric layer and the second dielectric layer have a high selectivity. The semiconductor structure according to claim 1 includes: a third dielectric layer located on the lower electrode, the third dielectric layer completely covering the lower electrode; and a fourth dielectric layer that at least covers the surfaces of the third dielectric layer, the resistive switching layer, and the upper electrode; wherein the materials of the third dielectric layer and the fourth dielectric layer have a high selectivity. According to the semiconductor structure of claim 1, the shape of the lower electrode in a projection perpendicular to the plane of the substrate includes a rectangle or a circle, and the shape of the upper electrode includes a rectangle, a circle, or an ellipse. A method for fabricating a semiconductor structure, comprising: providing a substrate; forming a plurality of resistive switching devices on the substrate, wherein forming each resistive switching device comprises: forming a lower electrode on the substrate; forming the lower electrode connected to the substrate through a metal layer and a first contact plug; forming a plurality of mutually spaced resistive switching layers around the lower electrode, the resistive switching layers contacting the sidewalls of the lower electrode; and forming a plurality of upper electrodes enclosed by the resistive switching layers, the upper electrodes being isolated from the lower electrodes through the resistive switching layers; Multiple resistive switching devices are arranged along a first direction and a second direction, wherein multiple resistive switching devices are arranged in a row along the first direction, multiple resistive switching devices are arranged in a column along the second direction, and resistive switching devices in adjacent columns and adjacent rows are staggered, and resistive switching devices in a column and a row are aligned with each other; the manufacturing method further includes: after forming the resistive switching device, forming multiple first lines extending along the first direction and arranged along the second direction, each first line being connected to one of the upper electrodes of multiple resistive switching devices in each row, and the opposite upper electrodes of resistive switching devices in adjacent rows being connected to the same first line; The method comprises forming multiple second bit lines extending along the second direction and arranged along the first direction, each second bit line being connected to one of the upper electrodes of multiple resistive switching devices in each column, and the opposite upper electrodes of adjacent columns of resistive switching devices being connected to the same second bit line; the manufacturing method further comprises forming a second contact plug while forming the first bit line, the second contact plug being located on the upper electrode that is not in contact with the first bit line; wherein the upper surface of the second contact plug is higher than the upper surface of the first bit line, and the second bit line is formed on the second contact plug. According to the manufacturing method of claim 5, the manufacturing method includes: after providing the substrate, forming a first dielectric layer and a second dielectric layer stacked sequentially on the substrate; wherein the materials of the first dielectric layer and the second dielectric layer have a high selectivity. According to the manufacturing method of claim 6, forming the lower electrode includes: forming a first trench penetrating the first dielectric layer and the second dielectric layer; forming the lower electrode filling the first trench; forming the resistive switching layer includes: forming a second trench penetrating the second dielectric layer, the second trench stopping on the first dielectric layer; forming the resistive switching layer covering the sidewalls and bottom of the second trench. According to the manufacturing method of claim 5, the manufacturing method includes: forming a third dielectric layer on the lower electrode, the third dielectric layer completely covering the lower electrode; forming a fourth dielectric layer, the fourth dielectric layer at least covering the surfaces of the third dielectric layer, the resistive switching layer and the upper electrode; wherein the materials of the third dielectric layer and the fourth dielectric layer have a high selectivity. According to the manufacturing method of claim 5, in a projection perpendicular to the plane of the substrate, the shape of the lower electrode includes a rectangle or a circle, and the shape of the upper electrode includes a rectangle, a circle, or an ellipse.