TWI909839B - Semiconductor device manufacturing method - Google Patents

Abstract

The method for manufacturing a semiconductor device according to the present invention involves injecting N-type impurities into a substrate low-concentration doped with N-type impurities in a WBG semiconductor from the main surface side of the substrate, thereby forming an N+ layer high-concentration doped with the N-type impurities (N+ layer formation step). Furthermore, in the aforementioned substrate, at a predetermined location deeper than the N+ layer formation area or a predetermined formation area from the main surface, a partition layer is formed that can partition the substrate at that predetermined location (partition layer formation step). Next, the main surface of the substrate is held using a substitute substrate (first holding step). Subsequently, the partition layer is used to partition the substrate at the predetermined location, thereby separating the portion on the main surface side from the substrate while it is held on the substitute substrate (partitioning step). In this way, the separated main surface portion becomes a semiconductor substrate containing N+ layers.

Description

Semiconductor device manufacturing method

This invention relates to the manufacturing technology of semiconductor devices.

As a semiconductor device manufacturing technology, there exists a process that allows semiconductor wafers (e.g., wafers with a thickness of about 350 μm) to be thinned to the required thickness (e.g., a thickness of less than 150 μm) by grinding.

In recent years, wide bandgap (WBG) semiconductors such as SiC have attracted attention as semiconductor materials that can operate normally even at temperatures exceeding 250°C. WBG semiconductors are also semiconductor materials that enable high-speed switching, and in this respect, they are expected to be used as semiconductor materials for high-speed communications. Furthermore, WBG semiconductors have an insulation withstand voltage that is more than 10 times higher than that of conventional Si semiconductors, making them suitable for thinning into N-type layers (drift layers) with low concentrations of N-type impurities. Therefore, WBG semiconductors are semiconductor materials that possess both low resistance (low on-resistance) and high voltage withstand capability, and are thus expected to be used as materials for high-voltage semiconductor devices. Accordingly, WBG semiconductors offer advantages in various aspects as materials for semiconductor devices. [Prior Art Documents] [Patent Documents]

[Patent Document 1] Japanese Patent Application Publication No. 2007-250576

(Problem to be solved by the invention) On the other hand, WBG semiconductors are high-priced semiconductor materials. Therefore, if semiconductor wafers are to be thinned by grinding as is commonly known, the portion of the semiconductor wafer removed by grinding becomes waste, leading to a significant increase in material costs.

Furthermore, in the manufacture of high-voltage semiconductor devices using WBG semiconductors, it is conventional to utilize epitaxial growth to form an N-type semiconductor layer (N-layer). However, epitaxial growth requires a relatively long time. Moreover, the higher the voltage withstand capability required for the semiconductor device, the greater the required thickness of the N-layer, and the longer the epitaxial growth time. Therefore, forming the N-layer via epitaxial growth is one of the reasons for the increased operating costs associated with manufacturing semiconductor devices.

Therefore, the purpose of this invention is to significantly reduce the manufacturing cost of semiconductor devices using WBG semiconductors. (Technical means to solve the problem)

The semiconductor device manufacturing method of the present invention includes: an N+ layer formation step, a partition layer formation step, a first holding step, and a partition step (Pattern 1). The N+ layer formation step involves injecting N-type impurities from the main surface side of a substrate in which N-type impurities are low-concentration doped in a WBG semiconductor, thereby forming an N+ layer with a high concentration of N-type impurities. The partition layer formation step involves forming a partition layer in the substrate at a predetermined location deeper than the N+ layer formation area or a predetermined formation area from the main surface, which can partition the substrate at that predetermined location. After the partition layer formation step, in the first holding step, the main surface of the substrate is held using a substitute substrate. Following the first holding step, in the splitting step, a splitting layer is used to split the substrate at a predetermined position, thereby separating the main surface portion from the substrate while it is held in place of a replacement substrate. In this way, the separated main surface portion becomes a semiconductor substrate containing N+ layers.

According to the above manufacturing method, a semiconductor substrate is formed comprising both an N+ layer and an N- layer (a semiconductor layer doped with N-type impurities at a low concentration). Moreover, in the above manufacturing method, by preparing a substrate (a die or a semiconductor wafer cut from the die) doped with the same concentration of N-type impurities as the portion forming the N- layer in the semiconductor substrate, the desired semiconductor substrate comprising both the N+ layer and the N- layer can be formed using only simple processes such as further implantation of N-type impurities into the substrate (formation of the N+ layer) and dicing of the substrate at the predetermined location (processes that can be performed in a short time). In other words, compared to the conventional manufacturing method of forming N-layers using epitaxial growth, the time required to manufacture semiconductor substrates can be significantly reduced.

Furthermore, in the above manufacturing method, compared to the separator layer, since the portion on the main surface side (the portion that becomes the semiconductor substrate) is held by a substitute substrate, even if the thickness of that portion is relatively thin, subsequent processing can be easily performed. Therefore, in the separator layer formation step, when determining the predetermined location for forming the separator layer, the thickness of the portion separated from the substrate (the portion that becomes the semiconductor substrate) can be set as small as possible (for example, as small as possible within the thickness range corresponding to the required withstand voltage). In other words, a thinner semiconductor substrate can be manufactured without performing the conventional process of cutting the WBG semiconductor by grinding to the required thickness. Therefore, it can reduce the waste of WBG semiconductors, which are precious materials (waste generated during the manufacturing process).

The manufacturing method of the above-described Form 1 can further include a device formation step, a second holding step, and a detachment step (Form 2). Specifically, it is as follows: After the dividing step, in the device formation step, at least a portion of the elements of a semiconductor device is inserted into the semiconductor substrate from the surface side opposite to the main surface. After the device formation step, in the second holding step, the surface of the semiconductor substrate is held using a holding portion different from that of the substitute substrate. After the second holding step, in the detachment step, the substitute substrate is detached from the semiconductor substrate. Then, when repeating the N+ layer formation step to the detachment step, in the first holding step, the alternative substrate that was detached in the detachment step is used as the alternative substrate used here.

In the above manufacturing method, the alternative substrate is preferably formed from a WBG semiconductor of the same type or with a similar coefficient of thermal expansion (e.g., a WBG semiconductor with a heat resistance temperature of 1800°C or higher). This is because it reduces the difference in the coefficient of thermal expansion between the alternative substrate and the semiconductor substrate, thereby suppressing warping that may occur during heating in subsequent steps due to the difference in the coefficient of thermal expansion. Furthermore, according to Example 2, the alternative substrate can be reused without waste, allowing for repeated and effective utilization. Therefore, a high-cost substrate formed from a WBG semiconductor in this manner can be used as the alternative substrate.

In the manufacturing method of the above-mentioned phenotype 2, in the first holding step, dot-shaped or line-shaped fixing parts for fixing the substitute substrate can also be formed in the surrounding area of the main surface of the substrate (phenotype 3).

According to the above-described pattern 3, by making the fixing portion into a dot or line shape, the fixing area can be reduced, resulting in easier separation of the replacement substrate from the semiconductor substrate. Furthermore, by forming the fixing portion in the surrounding area, the impact on the semiconductor components that may be affected during the separation of the replacement substrate (the stress or heat generated during separation) can be reduced.

In the manufacturing method of the above-mentioned sample 3, in the first holding step, a substrate with an bonding prevention layer formed in a region that is more inner than the region surrounding the main surface of the substrate can also be used as an alternative substrate (sample 4).

According to the above-mentioned pattern 4, it is possible to prevent the alternative substrate from being bonded to an inner area (the area that becomes a semiconductor device) that is not to be bonded in the main surface of the substrate.

In any of the manufacturing methods of the above-mentioned properties 1 to 3, in the first holding step, an annular substrate in the surrounding area of the main surface of the holding substrate can also be used as a substitute substrate (property 5).

The annular replacement substrate used in the above-described sample 5 can be formed by using a disc-shaped substrate and removing its inner portion. Then, the removed inner portion can be reused as a replacement substrate when manufacturing other semiconductor substrates of different sizes. In this way, the replacement substrate can be effectively utilized.

Any of the manufacturing methods described in States 1 to 5 may further include an electrode layer formation step (State 6) after the N+ layer formation step and before the first holding step, in which an electrode layer is formed on the main surface of the substrate.

According to the above-described form 6, by forming an electrode layer before the first holding step, and during the first holding step when the main surface of the substrate is held using a substitute substrate, the electrode layer is locally heated by laser irradiation. This allows a bonding portion for bonding the substitute substrate to be formed on the main surface of the substrate at the laser irradiation point. (Effect compared to prior art)

According to the present invention, the manufacturing cost can be significantly reduced in the manufacturing technology of semiconductor devices using WBG semiconductors.

The following describes in detail the embodiments and variations of the manufacturing method of the semiconductor device of the present invention. In addition, the manufacturing method described below can be implemented using various well-known devices.

[1] Embodiments Figures 1 to 5 are conceptual diagrams showing the manufacturing method of the embodiments in the order of processing. In this manufacturing method, the following steps are performed in sequence: N+ layer formation step S1, split layer formation step S2, first holding step S3, splitting step S4, element formation step S5, second holding step S6, delamination step S7, electrode layer formation step S8, transfer step S9, and monolithization step S10. Each step will be explained in detail below.

<N+ Layer Formation Step S1> In the N+ layer formation step S1 (refer to Figure 1), firstly, a substrate 1 is prepared in which N-type impurities are doped into the WBG semiconductor at a low concentration. Here, "low concentration" means that the concentration of N-type impurities in the WBG semiconductor is less than 1 × ^{10¹⁷ cm⁻³} . The WBG semiconductor can be made of semiconductor materials such as SiC, diamond, GaN, _Ga₂O₃ , AlN, BN, etc. Furthermore, as the substrate 1, a monocrystalline ingot formed from _the WBG semiconductor can be prepared, or a semiconductor wafer (e.g., a wafer with a thickness of about 350 μm) can be prepared from the ingot.

Then, by injecting N-type impurities into the prepared substrate 1 from the main surface 10a side of the substrate 1, an N+ layer 11S with a high concentration of N-type impurities is formed. Here, "high concentration" means that the concentration of N-type impurities in the WBG semiconductor is 1 × ^{10¹⁸ cm⁻³} or higher. Furthermore, the following surfaces can be used as the main surface 10a: When the substrate 1 is a tablet, the flat cut surface exposed from the end of the tablet or the ground surface can be used as the main surface 10a. When the substrate 1 is a semiconductor wafer, the flat cut surface formed when the semiconductor wafer is cut from the tablet or the ground surface can be used as the main surface 10a.

In this embodiment, the N+ layer 11S is formed in the electrode layer formation step S8 described later, during which the electrode layer 4 is formed on the main surface 10a (the back surface Kb of the semiconductor substrate K), and an ohmic bond can be formed between the electrode layer 4 and the semiconductor substrate K. Furthermore, this ohmic bond only requires the thickness Tc of the N+ layer 11S to be approximately a few micrometers.

<Separation Layer Formation Step S2> Separation layer formation step S2 (refer to FIG. 1) involves forming a separation layer 12 at a predetermined position Pt (at a predetermined depth Dt) in the substrate 1, at a depth deeper than the formation area of the N+ layer 11S than the main surface 10a. Here, the separation layer 12 is a layer that allows the semiconductor substrate K with a thickness Td of a predetermined depth Dt to be separated from the substrate 1 (refer to separation step S4 in FIG. 3), and can be formed by injecting hydrogen ions from the main surface 10a side of the substrate 1. Based on the implantation of hydrogen ions, a segmentation layer 12 can be formed at a depth of about 10 μm from the main surface 10a or at a shallower depth, resulting in a semiconductor substrate K with a thickness Td corresponding to its depth.

Alternatively, when forming the partition layer 12, instead of the hydrogen ion implantation method, a method of irradiating laser light from the main surface 10a side with a predetermined position Pt (at a predetermined depth Dt) as the focal point can be adopted. According to this method, the position of the focal point can be changed in the depth direction, so the partition layer 12 can be formed at the desired depth. Therefore, according to the laser irradiation method, the partition layer 12 can be formed at a deeper position than the hydrogen ion implantation method (for example, at a depth of about 50 to 150 μm from the main surface 10a), resulting in a semiconductor substrate K with a thickness Td corresponding to its depth.

Unlike conventional processes that grind WBG semiconductors to the required thickness Td using this type of layer-forming step S2, this method avoids wasting semiconductor material (here, the expensive WBG semiconductor) and allows for the formation of a very thin semiconductor substrate K. However, if the semiconductor substrate K becomes very thin in this way, it becomes difficult for it to maintain its flatness on its own. Therefore, in the layer-separation step S4 described later, before the semiconductor substrate K separates from the substrate 1, a holding portion is used to hold the portion of the substrate 1 that becomes the semiconductor substrate K. This holding portion is also needed to maintain the flatness of the semiconductor substrate K after separation. Therefore, the first holding step S3 is performed before the layer-separation step S4.

<First Holding Step S3> In the first holding step S3 (refer to FIG2), firstly, a substitute substrate 2 as the holding part is prepared.

Therefore, the alternative substrate 2 only needs to have the strength to maintain the flatness of the semiconductor substrate K after the portion of the substrate 1 that becomes the semiconductor substrate K is separated. Therefore, the alternative substrate 2 can be a material with inferior electrical properties compared to the substrate 1. On the other hand, the alternative substrate 2 is preferably formed of a material with a coefficient of thermal expansion close to that of the substrate 1. The reason for this is that the difference in the coefficient of thermal expansion between the alternative substrate 2 and the semiconductor substrate K can be reduced, and as a result, warping that may occur during heating in subsequent steps (such as the device formation step S5) due to the difference in the coefficient of thermal expansion can be suppressed.

In this embodiment, as an alternative substrate 2, a multi-junction semiconductor wafer is prepared, which is formed from a WBG semiconductor of the same type as the substrate 1 or a WBG semiconductor of a type with a similar coefficient of thermal expansion (for example, the heat resistance temperature of such WBG semiconductor is 1800°C or higher).

Then, by bonding the holding surface 20a of the substitute substrate 2 to the main surface 10a of the substrate 1, the portion of the substrate 1 that becomes the semiconductor substrate K is held by the substitute substrate 2.

Specifically, when preparing the replacement substrate 2, a metal layer 13 is pre-formed. This metal layer 13 is distributed throughout the area facing the periphery 10r of the main surface 10a of the main surface 10a of the replacement substrate 2, or the substrate 1 and the replacement substrate 2 are partially bonded only at predetermined bonding points (step S31). Here, the bonding between the substrate 1 and the replacement substrate 2 can be achieved by heating the metal layer 13 with laser light, and the metal layer 13 is a layer mainly composed of metals such as Cu, Al, Cr, Ti, Ta, and Au.

Next, by overlapping the substrate 1 and the substitute substrate 2, a metal layer 13 can be present between the surrounding area 10r of the main surface 10a and the holding surface 20a of the substitute substrate 2. In this state, the metal layer 13 is heated by irradiating with laser light (step S32). At this time, the substrate 1 and the substitute substrate 2 can be clamped together using a quartz plate or the like in a way that increases the tightness of contact with the metal layer 13.

According to the irradiation of this metal layer 13 by laser light, at the irradiation point (pre-determined bonding point) in the metal layer 13, a bonding portion Q for fixing the substitute substrate 2 to the main surface 10a of the substrate 1 can be formed (step S33). Specifically, at the irradiation point of the laser light, the metal layer 13, the substrate 1, and the substitute substrate 2 are melted together, or the metal, which is the main component of the metal layer 13, can diffuse towards the substrate 1 and the substitute substrate 2. As a result, at the respective interfaces of the substrate 1 and the substitute substrate 2 with the metal layer 13, compounds (metal silicates, etc.) or alloys (metal-Si alloys, etc.) of the main components of the substrate 1 and the substitute substrate 2 with metals are formed into bonding portions Q, and the substrate 1 (which becomes part of the semiconductor substrate K) and the substitute substrate 2 are bonded through the bonding portions Q.

In this embodiment, the bonding portion Q is formed in the peripheral region 10r of the main surface 10a in the substrate 1, and the substrate 2 is bonded to the main surface 10a of the substrate 1 via the bonding portion Q (step S33). Here, in subsequent steps (e.g., element formation step S5), the semiconductor element is embedded in a region of the semiconductor substrate K that is further inside than the peripheral region 10r after separation. Specifically, a plurality of element regions Rd for embedding semiconductor elements are provided in the inner region (see FIG6). Therefore, by first forming the fixing part Q in the surrounding area 10r, when the replacement substrate 2 is detached from the semiconductor substrate K in the detachment step S7 described later, the influence on the device area Rd (semiconductor device) that may be generated at this time (the influence of stress or heat generated during detachment) can be reduced.

Furthermore, in this embodiment, the bonding portion Q is formed into a linear shape by scanning laser light. The reason for this is that by making the bonding portion Q into a linear shape, the bonding area can be reduced. As a result, in the detachment step S7 described later, the replacement substrate 2 can be more easily detached from the semiconductor substrate K. In the example of FIG6, the linear bonding portion Q is shown to cover the entire periphery of the surrounding area 10r, forming a ring shape.

Furthermore, from the viewpoint of facilitating detachment, the bonding portion Q can be formed into a dot shape by irradiating laser light at a single point, thereby maintaining the semiconductor substrate K, and a plurality of such dot-shaped bonding portions Q can be formed. Moreover, the method of forming the bonding portion Q is not limited to the method using the metal layer 13; it can also be appropriately modified to not use the metal layer 13, but to allow the substrate 1 and the alternative substrate 2 to be in direct contact, and to irradiate laser light at the interface to form the bonding portion Q.

In this way, by using the substitute substrate 2 to retain the portion of the substrate 1 that becomes the semiconductor substrate K, even when the thickness Td of the separated semiconductor substrate K is very thin, the substitute substrate 2 can maintain the flatness of the semiconductor substrate K, making subsequent processing easier. Therefore, in the split layer formation step S2, when determining the predetermined position Pt for forming the split layer 12, the thickness Td (= predetermined depth Dt) of the portion separated from the substrate 1 can be set as small as possible (for example, as small as possible within the thickness range corresponding to the necessary withstand voltage) to determine the predetermined position Pt. In other words, a very thin semiconductor substrate K can be manufactured without performing the conventional process of cutting WBG semiconductors by grinding to the required thickness Td. Therefore, it can reduce the waste of WBG semiconductors, which are precious materials (waste generated during the manufacturing process).

<Segmentation Step S4> In segmentation step S4 (refer to FIG. 3), the substrate 1 is segmented at a predetermined position Pt (at a predetermined depth Dt) using the segmentation layer 12, thereby separating the portion on the main surface 10a side (which becomes the semiconductor substrate K) from the substrate 1 while it is held in place of the replacement substrate 2. This forms a semiconductor substrate K with a thickness Td of a predetermined depth Dt. Furthermore, as the semiconductor substrate K, a substrate comprising both an N+ layer 11S and an N- layer 11T (a semiconductor layer doped with a low concentration of N-type impurities) is formed.

According to the steps S1 to S4 of forming the N+ layer described above, by preparing a substrate 1 doped with the same concentration of N-type impurities as those forming the N-layer 11T in the semiconductor substrate K, the required semiconductor substrate K containing both the N+ layer 11S and the N-layer 11T can be formed simply by further implanting N-type impurities into the substrate 1 (forming the N+ layer 11S) and dividing the substrate 1 at the predetermined location using Pt (a process that can be performed in a short time). In other words, compared to the conventional manufacturing method that uses epitaxial growth to form the N-layer 11T, the manufacturing time required for the semiconductor substrate K can be significantly shortened.

Then, the component formation step S5 described below is performed on the divided semiconductor substrate K. Furthermore, the remaining portion 1R (the remaining portion after division) in the substrate 1 other than the semiconductor substrate K is reused in the manufacture of a new semiconductor substrate K and semiconductor components.

<Device Formation Step S5> Device formation step S5 (refer to FIG. 3) involves embedding at least a portion of the element Gd having a semiconductor element into a plurality of device regions Rd (also refer to FIG. 6) formed on the semiconductor substrate K. Specifically, for the semiconductor substrate K, the element Gd is embedded from the surface Ka (the surface exposed by the division of the dividing layer 12 (the surface exposing the N-type WBG semiconductor)) to the N-layer 11T. Although not particularly limited, a MOSFET or Schottky diode, etc., can be formed in the device region Rd as the element Gd.

The component formation step S5 is mostly performed at temperatures exceeding 1000°C. If there is a significant difference in the coefficient of thermal expansion between the semiconductor substrate K and the alternative substrate 2, this difference in coefficient of thermal expansion may cause warping on the semiconductor substrate K when heated to high temperatures. This warping can cause stress to be generated within the semiconductor substrate K, and this stress may lead to defects such as strain on the semiconductor substrate K. Furthermore, this stress can also cause defects to form in the MOSFET or Schottky diode components (Gd) formed on the semiconductor substrate K.

On the other hand, in this embodiment, as the alternative substrate 2, a semiconductor wafer formed from a WBG semiconductor of the same type as the substrate 1 or a WBG semiconductor of a type with a similar coefficient of thermal expansion can be used. Therefore, the difference in the coefficient of thermal expansion between the alternative substrate 2 and the semiconductor substrate K is reduced. Consequently, in the device formation step S5, even when the semiconductor substrate K and the alternative substrate 2 are heated to a high temperature together, warping is less likely to occur on the semiconductor substrate K. Therefore, stress is less likely to occur on the semiconductor substrate K, and consequently, defects are less likely to occur on the element Gd formed on the semiconductor substrate K.

<Second Holding Step S6> In the second holding step S6 (refer to FIG. 3), the surface Ka of the semiconductor substrate K is held using a holding portion 3, which is different from the alternative substrate 2. The holding portion 3 can be the same as the alternative substrate 2, or it can be a substrate formed of other materials not limited to semiconductors (Si, sapphire, quartz, etc.). Then, when using such a substrate as the holding portion 3, the holding surface 30a of the holding portion 3 is attached to the surface Ka of the semiconductor substrate K using a connecting component 31 (heat-resistant double-sided tape, etc.).

Alternatively, the retaining part 3 can be one that can hold the surface Ka of the semiconductor substrate K in place by vacuum adsorption. With this type of retaining part 3, the subsequent component 31 becomes unnecessary, and foreign matter can be prevented from adhering to the surface Ka of the semiconductor substrate K.

<Detachment Step S7> In detachment step S7 (refer to FIG4), while the semiconductor substrate K is held by the holding part 3, the replacement substrate 2 is detached from the semiconductor substrate K.

As a first specific example, the alternative substrate 2 can be detached from the semiconductor substrate K by driving a wedge between the semiconductor substrate K and the alternative substrate 2 to destroy the fixing part Q. As a second specific example, the alternative substrate 2 can be detached from the semiconductor substrate K by irradiating the fixing part Q with laser light to destroy the fixing part Q.

As a third specific example, the semiconductor substrate K can be irradiated with laser light to cut it in a ring shape at a position further inside the fixing portion Q, thereby detaching the replacement substrate 2 from the semiconductor substrate K. As a fourth specific example, the semiconductor substrate K and the replacement substrate 2 can be pulled apart vertically by utilizing the bonding force of the fixing portion Q, and the semiconductor substrate K can be broken in a ring shape at a position further inside the fixing portion Q, thereby detaching the replacement substrate 2 from the semiconductor substrate K.

In this embodiment, the substitute substrate 2 is reused after it is detached from the semiconductor substrate K. Specifically, after detachment from the semiconductor substrate K, the holding surface 20a of the substitute substrate 2 is ground to remove the attachment portion Q or the residue of the semiconductor substrate K from the holding surface 20a. Then, when repeating the steps starting from the N+ layer formation step S1, the substitute substrate 2 is reused in the first holding step S3.

In this embodiment, although an expensive alternative substrate 2 formed of WBG semiconductor is used, as described above, the alternative substrate 2 can be reused, so this expensive alternative substrate 2 is not wasted and can be reused effectively.

<Electrode Layer Formation Step S8> In electrode layer formation step S8 (refer to FIG. 4), an electrode layer 4 is formed on the back side Kb of the semiconductor substrate K exposed by the removal of the substitute substrate 2. As an example, sputtering can be used to form the electrode layer 4. At this time, the N+ layer 11S is exposed on the back side Kb of the semiconductor substrate K, so the electrode layer 4 can be formed on the back side Kb using ohmic bonding.

<Transfer Step S9> In transfer step S9 (refer to FIG. 4), the semiconductor substrate K is transferred from the holding portion 3 to the holding sheet 5 (such as cutting tape). Specifically, after holding the semiconductor substrate K from the back side Kb side using the holding sheet 5, the holding portion 3 is detached from the semiconductor substrate K.

In this embodiment, after the holding part 3 is detached from the semiconductor substrate K, when the steps starting from the N+ layer formation step S1 are repeated, the holding part 3 is reused in the second holding step S6.

<Monolithicization Step S10> In monolithicization step S10 (refer to FIG. 5), while holding the semiconductor substrate K in the holding sheet 5 state, a cutting process is performed on the semiconductor substrate K to monolithize a plurality of device regions Rd disposed on the semiconductor substrate K. Specifically, the semiconductor substrate K is cut along the boundary line Lb (refer to FIG. 6) that distinguishes the plurality of device regions Rd, thereby monolithizing the plurality of device regions Rd. The cutting method at this time can be blade cutting, plasma etching, laser peeling, etc. In this way, a plurality of semiconductor devices having elements Gd such as MOSFETs or Schottky diodes are manufactured.

According to the manufacturing method of this embodiment, as described above, compared with the conventional manufacturing method of forming an N-layer 11T using epitaxial growth, the time required to manufacture the semiconductor substrate K can be significantly shortened. Furthermore, a thinner semiconductor substrate K can be manufactured without performing the conventional process of cutting the WBG semiconductor by grinding to the required thickness Td. Therefore, waste of the valuable WBG semiconductor material (waste generated during the manufacturing process) can be reduced. Thus, in the manufacturing technology of semiconductor devices using WBG semiconductors, the manufacturing cost can be significantly reduced.

[2] Variation Example [2-1] First Variation Example Figure 7 is a conceptual diagram showing a portion of the manufacturing method of the first variation example in the order of processing. In the above manufacturing method, a split layer forming step S2 can be performed before the N+ layer forming step S1. At this time, in the split layer forming step S2, a substrate 1 with N-type impurities doped at a low concentration in the WBG semiconductor is prepared. Moreover, in the split layer forming step S2, a predetermined position Pt (position of predetermined depth Dt) is set such that the depth from the main surface 10a is deeper than the predetermined area Rx of the N+ layer 11S, and then a split layer 12 is formed at the predetermined position Pt. Subsequently, in the N+ layer formation step S1, an N+ layer 11S with a high concentration of the N-type impurity is formed in the predetermined area Rx by injecting N-type impurities from the main surface 10a side of the substrate 1.

[2-2] Second Variation Figure 8 is a conceptual diagram showing a portion of the manufacturing method of the second variation in the processing sequence. In the above manufacturing method, the electrode layer formation step S8 can also be performed after the N+ layer formation step S1 and before the first holding step S3. Specifically, the electrode layer 4 is formed on the main surface 10a of the substrate 1 (the surface that becomes the back surface Kb of the semiconductor substrate K). In this case, since the N+ layer 11S is exposed on the main surface 10a of the substrate 1, the electrode layer 4 can also be formed on the main surface 10a using ohmic bonding.

According to the second variation, the electrode layer 4 is formed before the first holding step S3, and in the first holding step S3, the electrode layer 4 can be used as the metal layer 13. In other words, the electrode layer 4 can be used to form the bonding portion Q. Specifically, by overlapping the substitute substrate 2 on the electrode layer 4, the electrode layer 4 exists between the main surface 10a of the substrate 1 and the holding surface 20a of the substitute substrate 2 (step S32). In this state, the electrode layer 4 is locally heated by laser light irradiation, thereby forming the bonding portion Q using the electrode layer 4 (step S33). At this time, by irradiating the portion of the peripheral area 10r of the main surface 10a in the electrode layer 4 with laser light, the fixing part Q can be formed in the peripheral area 10r that can reduce the influence on the component area Rd (step S33).

In addition, if other materials must be used on electrode layer 4 and metal layer 13, both electrode layer 4 and metal layer 13 are formed in electrode layer formation step S8, and the metal layer 13 can also be used to form the fixation part Q in the first holding step S3.

[2-3] Figure 9 is a conceptual diagram of the first holding step S3 performed in the third variation. In the above manufacturing method, in the first holding step S3, as a substitute substrate 2, a substrate with a bonding prevention layer 21 formed in an area that prevents the substitute substrate 2 from bonding with the substrate 1 (semiconductor substrate K) can also be used. This area is the area 20x that is more inner than the area 10r surrounding the main surface 10a of the substrate 1 (the area where the metal layer 13 is formed) in the holding surface 20a of the substitute substrate 2. Although not particularly limited, the bonding prevention layer 21 is, for example, a _SiO2 layer or a carbon (C) layer. The _SiO2 layer is formed by growing _SiO2 on the holding surface 20a of the substitute substrate 2 using the LOCOS method. The carbon layer is formed by depositing carbon on the holding surface 20a of the substitute substrate 2 using sputtering or CVD methods.

According to the third variation, the alternative substrate 2 can be prevented from bonding to the inner region (the region that becomes a semiconductor element) of the main surface 10a of the substrate 1 that is not to be bonded. Furthermore, by forming the bonding prevention layer 21 to the same height as the metal layer 13, the bonding prevention layer 21 can be embedded in the gap between the alternative substrate 2 and the substrate 1 in the region that is further inner than the region where the metal layer 13 is formed. As a result, strain (which may occur due to the aforementioned gap) can be prevented from occurring in the semiconductor substrate K formed thereafter.

[2-4] Fourth Variation Figure 10 is a conceptual diagram showing the first holding step S3 performed in the fourth variation. In the above manufacturing method, in the first holding step S3, as an alternative substrate 2, an annular substrate of the surrounding area 10r of the main surface 10a of the holding substrate 1 can be used.

This annular replacement substrate 2 can be formed by using a disc-shaped substrate and cutting out its inner portion. Then, the cut-out inner portion can be reused as replacement substrate 2 when manufacturing other semiconductor substrates K of different sizes. In this way, according to the fourth variation, the replacement substrate 2 can be effectively utilized.

[2-5] Fifth Variation Example Figure 11(A) is a conceptual diagram showing step S31 within the first holding step S3 performed in the fifth variation example. As shown in the figure, on the holding surface 20a of the alternative substrate 2, the metal layer 13 can also be formed in a region that is offset inward from the outer periphery of the holding surface 20a. According to this configuration, even if the metal layer 13 deforms due to heat or the like in subsequent steps, it is difficult for the metal layer 13 to flow outward.

Figures 11(B) and 11(C) are conceptual diagrams illustrating two further variations of step S31 shown in Figure 11(A). As shown in these figures, from the viewpoint of preventing the metal layer 13 from flowing outwards, an outflow prevention layer 22 can be formed on the holding surface 20a of the substitute substrate 2, between its outer periphery and the formation area of the metal layer 13. Here, the outflow prevention layer 22 is, for example, a _SiO2 layer or a carbon (C) layer. The _SiO2 layer can be formed by growing _SiO2 on the holding surface 20a of the substitute substrate 2 using the LOCOS method. The carbon layer can be formed by depositing carbon film on the holding surface 20a of the substitute substrate 2 using sputtering or CVD methods. Furthermore, this outflow prevention layer 22 can also be formed together with the bonding prevention layer 21 on the holding surface 20a of the alternative substrate 2 (see FIG11(C)).

[2-6] Sixth Variation As a sixth variation, the semiconductor device manufacturing method may include the device formation step S5, the second holding step S6, and the detachment step S7 in the above steps. The manufacturing method may be performed after the N+ layer formation step S1 to the splitting step S4.

[2-7] Seventh Variation As a seventh variation, the semiconductor device manufacturing method may include the N+ layer formation step S1, the split layer formation step S2, the first holding step S3, and the splitting step S4 in the above steps. After the manufacturing method is performed, the device formation step S5 to the separation step S7 may also be performed.

The above descriptions of embodiments and variations are illustrative and not limiting. The scope of this invention is not limited to the above embodiments or variations, but is defined by the scope of the patent application. Furthermore, the scope of this invention is intended to include all changes within the scope of the patent application and in the same sense.

Furthermore, based on the above embodiments or variations, as the object of the invention, several steps of the manufacturing method constituting a semiconductor device can be partially extracted, or each step can be extracted individually.

1: Substrate 1R: Remaining portion 2: Replacement substrate 3: Holding portion 4: Electrode layer 5: Holding sheet 10a: Main surface 10r: Peripheral area 11S: N+ layer 11T: N- layer 12: Separator layer 13: Metal layer 20a: Holding surface 20x: Inner area 21: Bonding prevention layer 22: Flow-out prevention layer 30a: Holding surface 31: Adhesion component Dt: Determined depth Gd: Element K: Semiconductor substrate Ka: Surface Kb: Back side Lb: Boundary line Pt: Determined position Q: Mounting portion Rd: Component area Rx: Forming predetermined area Tc, Td: Thickness S1: N+ layer formation step S2: Separator layer formation step S3: First holding step S4: Segmentation Step S5: Component Formation Step S6: Second Holding Step S7: Detachment Step S8: Electrode Layer Formation Step S9: Transfer Step S10: Monolithization Step S31: Step S32: Step S33: Step

Figure 1 is a conceptual diagram showing a portion of the manufacturing method of the implemented form in processing order. Figure 2 is a conceptual diagram showing a portion following Figure 1 in processing order. Figure 3 is a conceptual diagram showing a portion following Figure 2 in processing order. Figure 4 is a conceptual diagram showing a portion following Figure 3 in processing order. Figure 5 is a conceptual diagram showing the subsequent processing of Figure 4. Figure 6 is a top view showing the shape of the fixation part formed in the implemented form. Figure 7 is a conceptual diagram showing a portion of the manufacturing method of the first variant example in processing order. Figure 8 is a conceptual diagram showing a portion of the manufacturing method of the second variant example in processing order. Figure 9 is a conceptual diagram showing the first holding step performed in the third variant example. Figure 10 is a conceptual diagram showing the first holding step performed in the fourth variant example. Figure 11(A) is a conceptual diagram of a portion of the first holding step performed in the fifth variation. Figures 11(B) and 11(C) are conceptual diagrams of two further variations of a portion of the steps, respectively.

1: Substrate 10a: Main Surface 11S: N+ Layer 12: Separation Layer Dt: Determined Depth Pt: Determined Position Tc: Thickness S1: N+ Layer Formation Step S2: Separation Layer Formation Step

Claims (6)

A method for manufacturing a semiconductor device includes: an N+ layer formation step, wherein an N-type impurity is injected from the main surface side of a substrate doped with a low concentration of N-type impurity of 1× ^{10¹⁷ cm⁻³} or less in a WBG semiconductor, thereby forming an N+ layer doped with the N-type impurity at a high concentration of 1× ^{10¹⁸ cm⁻³} or more; and a segmentation layer formation step, wherein a segmentation layer is formed in the substrate at a predetermined location at a depth deeper than the formation area of the N+ layer or a predetermined formation area, which can segment the substrate at the predetermined location. The first holding step involves holding the aforementioned main surface of the substrate using a substitute substrate after the aforementioned dividing layer formation step; and the dividing step involves dividing the aforementioned substrate at the aforementioned predetermined position using the aforementioned dividing layer after the aforementioned first holding step, thereby separating the portion on the aforementioned main surface side from the substrate while it is held on the aforementioned substitute substrate, thereby making that portion a semiconductor substrate containing the aforementioned N+ layers. The method for manufacturing a semiconductor device as claimed in claim 1 further comprises: a device forming step, which, after the aforementioned dividing step, inserts at least a portion of the elements of the semiconductor device from the surface side opposite to the aforementioned main surface of the aforementioned semiconductor substrate; a second holding step, which, after the aforementioned device forming step, holds the aforementioned surface of the aforementioned semiconductor substrate using a holding portion different from the aforementioned alternative substrate; and a detachment step, which, after the aforementioned second holding step, detaches the aforementioned alternative substrate from the aforementioned semiconductor substrate; when repeating the steps from the aforementioned N+ layer forming step to the aforementioned detachment step, in the aforementioned first holding step, the aforementioned alternative substrate detached in the aforementioned detachment step is used again as the alternative substrate used herein. As in the method for manufacturing a semiconductor device according to claim 2, in the aforementioned first holding step, dot-shaped or line-shaped fixing portions for fixing the aforementioned alternative substrate are formed in the surrounding area of the aforementioned main surface. As in the method of manufacturing a semiconductor device according to claim 3, in the aforementioned first holding step, a substrate having an bonding prevention layer formed in a region that is more inner than the region opposite to the periphery of the aforementioned main surface is used as the aforementioned alternative substrate. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein, in the aforementioned first holding step, an annular substrate holding the periphery of the aforementioned main surface is used as the aforementioned alternative substrate. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, further comprising: an electrode layer forming step, wherein an electrode layer is formed on the aforementioned main surface after the aforementioned N+ layer forming step and before the aforementioned first holding step.