TWI909708B - Transistor structure with multiple vertical thin bodies - Google Patents

Abstract

A transistor structure includes a semiconductor body, a source region, a drain region and a gate region. The semiconductor body has a convex structure and the convex structure has at least four conductive channels extending upward. The source region contacts with a first end of the convex structure. The drain region contacts with a second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer is across over the convex structure. Two or four conductive channels are not parallel to each other, and there is no shallow trench isolation region among the at least four conductive channels.

Description

Transistor structure with multiple vertical thin bodies

This invention relates to a transistor structure, particularly a transistor structure having multiple vertical thin bodies (or “VTBs”), wherein the transistor structure with VTBs can not only effectively reduce the leakage current path of the transistor structure in the OFF state, but also significantly enhance the conduction current of the transistor structure in the ON state.

In 2021, silicon integrated circuits achieved single-chip integration with more than 50 billion transistors on a single die. This was called the transition from the Very Large Scale Integration (VLSI) era (with more than a few million transistors on a single die) to the Gigabit-Scale Integration (GSI) era (with more than a billion transistors on a single die). This achievement of higher integration on a single die has greatly enabled more powerful microsystems, significantly improving their performance, power, area, and cost (PPAC). This has led to the creation of many powerful chips, such as central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), systems on a chip (SOCs), static random-access memory (SRAM), and dynamic random-access memory (DRAM). These powerful chips enhance system capabilities and continue to support Moore's Law, laying the foundation for exponential economic growth.

The massive productivity generated by large-scale integrated circuits (MBI) to develop new applications, thereby stimulating rapid economic growth, has created a strong demand for integrating more transistors into a single die. Therefore, the semiconductor industry is expected to strive towards the TSI (Tera-Scale Integration) era, which involves integrating trillions of transistors onto a single die. Consequently, significantly improving transistors to meet this TSI challenge requires the invention and engineering of transistor structures that fundamentally change performance, power consumption, area, and cost. For example, if a single die does indeed integrate 1 trillion transistors, and each transistor is configured to have a standby current Ioff (or off current Ioff) of about 0.5 picoamperes (pA), then the standby current Ioff of 1 trillion transistors will be close to 0.5 amperes.

However, even the most advanced transistors using technology smaller than 20 nanometers (nm) struggle to achieve a standby current Ioff of 0.5 pA. Even with various transistor structures (such as FinFETs or three-gate transistors), some transistor structures still exhibit standby current Ioffs as high as 5 to 10 pA. Therefore, continuously shrinking transistor size and reducing its standby current Ioff (e.g., below 1 pA) remains a key challenge for the semiconductor industry.

Figure 1 is a schematic diagram illustrating a fin field-effect transistor (FinFET) with an active region formed as a fin structure in the prior art. As shown in Figure 1, the gate structure 5 of the fin field-effect transistor is formed above the fin structure or a three-dimensional convex silicon surface. The gate structure 5 includes conductive materials (e.g., metals, polysilicon, or polysides) on an insulator or dielectric layer (e.g., oxides, oxide/nitrides, or some high-k materials). Taking an N-type metal-oxide-semiconductor (MOS) transistor as an example, the source region 11 and drain region 12 of the fin field-effect transistor are formed by implanting a high concentration of n-type (n+) dopants into a p-type substrate (or p-well) through ion implantation and thermal annealing technique, thereby resulting in the formation of two separate heavily doped n+/p junctions in the p-type substrate (or p-well). Furthermore, to reduce impact ionization and hot carrier injection in front of the heavily doped n+/p junction, lightly doped drains (LDDs) 13 are typically formed in front of the source region 11 and drain region 12 via ion implantation and thermal annealing. However, as shown in Figure 1, this ion implantation and thermal annealing technique often causes the lightly doped drains 13 to penetrate into the active region beneath the gate structure 5. Consequently, the length of the effective channel 14 between the lightly doped drains 13 is inevitably shortened.

On the other hand, advancements in manufacturing technology are continuously reducing the geometry of N-type metal-oxide-semiconductors (e.g., the smallest feature size, known as Lamda(λ), has shrunk from 28 nanometers (nm) to 5 nm or 3 nm). However, this reduction in the geometry of finned field-effect transistors (FinFETs) introduces or exacerbates the following problems:

(1) As the length of the gate structure 5 decreases, its standby current Ioff becomes increasingly difficult to reduce. A higher leakage current path (as shown in the dashed rectangular area 16 in the cross-section of the fin structure in Figure 2) is formed within the fin structure, rather than just along the surface of the fin structure. Additionally, Figure 3 is a schematic diagram illustrating the evaluation and simulation of the leakage current path shown in Figure 2. Figure 3(a) is the structure of the 3D fin field-effect transistor under Technology Computer-Aided Design (TCAD) simulation; Figure 3(b) is a cross-sectional view of the structure of the 3D fin field-effect transistor corresponding to the red dashed rectangle 18 in Figure 3(a); and Figure 3(c) is the current distribution of the 3D fin field-effect transistor in the off state (i.e., the standby current Ioff) (see "Impact of Current Flow Shape in Tapered (Versus Rectangular) FinFET on Threshold Voltage Variation Induced by Work-Function Variation", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE). (2014).

(2) Because it is necessary to reduce the dimensions in both the horizontal and vertical directions at the same time, it is becoming increasingly difficult to align the junction edge of the lightly doped drain 13 (or the edge of the source region 11/drain region 12) with the edge of the gate structure 5 using only the traditional gate, spacer layer and ion implantation self-alignment method. In addition, the thermal annealing technique used to eliminate ion implantation damage must rely on high temperature treatment techniques (e.g., rapid thermal annealing methods using various energy sources or other thermal processes). One problem arising from this is that although the gate-induced drain leakage (GIDL) current should be minimized to reduce leakage current, its generation is difficult to control. Another problem is that the short-channel effect (SCE) is difficult to minimize because the length of the effective channel 14 is difficult to control. Furthermore, the relative positions between the edges of the source region 11/drain region 12 and the edge of the gate structure 5 are also difficult to adjust to control the gate-induced drain leakage (GIDL) current.

(3) Furthermore, since the ion implantation forming the lightly doped drain 13 (or the n+/p junction in an N-type metal-oxide-semiconductor or the p+/n junction in a P-type metal-oxide-semiconductor) is similar to bombardment in order to inject ions directly downward from the top of the silicon surface into the substrate, it is difficult to create a uniform material interface with low defects from the source region 11 and drain region 12 to the effective channel 14 and the substrate-body region (because the doping concentration is not uniform in the vertical direction, for example, from the top surface with higher doping concentration to the junction with lower doping concentration in the vertical direction).

(4) Furthermore, when the horizontal dimension is reduced to 7nm, 5nm or 3nm, the height of the fin structure of the N-type metal-oxide-semiconductor (e.g. 40~100nm) is much greater than the width of the fin structure of the N-type metal-oxide-semiconductor (e.g. 3~10nm), which makes the fin structure of the N-type metal-oxide-semiconductor very fragile or even collapse in the subsequent manufacturing process (e.g., forming source region 11/drain region 12, or gate structure 5, etc.).

Therefore, this invention discloses a new 3D transistor structure to solve the above-mentioned shortcomings of the fin field-effect transistor. For example, the new 3D transistor structure can reduce the standby current Ioff by 10 to 100 times.

One embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor body, a source region, a drain region, and a gate region. The semiconductor body has a convex structure, wherein the convex structure has at least four upwardly extending conductive channels. The source region is in contact with a first end of the convex structure. The drain region is in contact with a second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer spans across the top of the convex structure. Two or all four conductive channels are not parallel to each other, and there are no shallow trench isolation (STI) regions between the at least four conductive channels.

In one embodiment of the invention, a groove is formed in the convex structure, the groove being located between the first end and the second end, and a first portion of the gate conductive layer is filled in the groove.

In one embodiment of the invention, the convex structure includes a set of upwardly extending thin bodies, and each thin body includes two conductive channels along the sidewall of the at least four conductive channels.

In one embodiment of the invention, the trench is located between two of the thin bodies in the group of thin bodies, a gate dielectric layer spans across the top of the convex structure, and a first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench.

In one embodiment of the invention, the ditch is tapered.

In one embodiment of the invention, the convex structure includes at least four upwardly extending conductor-oxide-semiconductor surfaces, and the at least four conductor-oxide-semiconductor surfaces are horizontally offset from each other.

Another embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor body, a source region, a drain region, and a gate region. The semiconductor body has a convex structure, wherein the convex structure has a raw surface, and the convex structure includes two upwardly extending thin bodies, which are separated from each other. The source region is in contact with a first end of the convex structure. The drain region is in contact with a second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer extends across the top of the convex structure. Each thin body is tapered, and there is no shallow trench isolation region between the two thin bodies.

In one embodiment of the invention, a groove is formed in the convex structure, the groove being located between the first end and the second end, and a first portion of the gate conductive layer is filled in the groove.

In one embodiment of the invention, each thin body includes two upwardly extending conductive channels.

In one embodiment of the invention, the trench separates the two thin bodies, a gate dielectric layer extends across the top of the convex structure, and a first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench.

Another embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor body, a source region, a drain region, a gate region, a trench, and an air electrode. The semiconductor body has a convex structure, wherein the convex structure has a raw surface, and the convex structure includes two upwardly extending thin bodies. The source region is in contact with a first end of the convex structure. The drain region is in contact with a second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer extends across the top of the convex structure. The trench is formed in the convex structure and located between the first end and the second end, wherein the trench separates the two thin bodies. The air electrode is located in the trench and is covered by the gate conductive layer.

In one embodiment of the invention, the convex structure includes a first outer wall and a second outer wall covered by the gate conductive layer, and the convex structure further includes a first inner wall and a second inner wall within the groove.

In one embodiment of the invention, the transistor structure further includes a first recess and a second recess. The first recess is used to accommodate the source region. The second recess is used to accommodate the drain region. The sidewalls of the first recess and the sidewalls of the second recess are surrounded by a shallow groove isolation region.

In one embodiment of the present invention, the edge of the source region is in contact with the two thin bodies, and the edge of the drain region is also in contact with the two thin bodies.

In one embodiment of the invention, the source region includes a lightly doped drain (LDD) region, a heavily doped region, and a metal region. The lightly doped drain region is in contact with the two thin bodies. The heavily doped region extends laterally from the lightly doped drain region. The metal region is located within the first recess and is in contact with one sidewall of the heavily doped region.

In one embodiment of the invention, the width of each thin body is no more than 3 nanometers (nm).

Please refer to Figures 4A, 4B, 4C, 4D, 4E, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, and 22. Figure 4A is a flowchart of a manufacturing method for a vertical thin body field-effect transistor (VTBFET) disclosed in an embodiment of the present invention. The manufacturing method of the VTBFET in Figure 4A enables the VTBFET to have lower standby current and lower gate-induced drain. It exhibits lower leakage (GIDL) current and shorter short-channel effect (SCE), and can form a solid fence wall to clamp the active region or narrow convex structure of the vertical thin-body field-effect transistor. Furthermore, the detailed steps of the manufacturing method for this vertical thin-body field-effect transistor (taking an N-type metal-oxide-semiconductor (MOS) transistor as an example) are as follows:

Step 10: Begin;

Step 20: On the basis of semiconductor substrate 200, define active region and form convex structure with multiple current conduction channels or multiple vertical thin bodies;

Step 30: Form the gate region of the vertical thin-body field-effect transistor;

Step 40: Form the source and drain regions of the vertical thin-film field-effect transistor;

Step 50: End.

Please refer to Figures 4B, 4C, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15. Step 20 includes:

Step 102: Generate a lining oxide layer 204 and deposit a lining nitride layer 206;

Step 104: Define the active region using photolithographic mask technology and remove portions of the semiconductor material (e.g., silicon) outside the active region to form the convex structure;

Step 106: Deposit a nitrided spacer layer 306 (or an oxide spacer layer 304 and a nitrided spacer layer 306) around the active region and etch back the nitrided spacer layer 306 (or an oxide spacer layer 304 and a nitrided spacer layer 306);

Step 108: Deposit an oxide layer and use chemical mechanical polishing (CMP) to remove excess oxide layer to form shallow trench isolation (STI) zone 402;

Step 110: Deposit a thin 802 nitride layer;

Step 112: Define the gate region spanning the active region and the shallow groove isolation region 402 using the photomask 902, and etch away the nitride layer 802 and the padding nitride layer 206 corresponding to the gate region;

Step 114: Remove the photomask 902, where the central pole related area is defined within the active area;

Step 116: Deposit a silicon carbide oxide (SiCOH) layer (or a combination of oxide/nitride layers) to form a silicon carbide oxide spacer-2 layer 1102;

Step 118: Based on the silicon carbide oxide spacer-2 layer 1102 and the nitride layer 802, a depression (or groove) 1202 is formed in the convex structure using anisotropic etching technique;

Step 120: Form a dielectric layer (e.g., thermal oxide) as the central electrode 1302 to fill the recess 1202;

Step 122: Deposit nitride-3 layers and etch back the nitride-3 layers to form nitride cap 1402;

Step 124: The shallow groove isolation area 402 exposed by back erosion is used to establish the convex structure in the gate polarity;

Step 126: Remove the nitride layer 802, the nitride spacer layer 306, and the nitride cap layer 1402 and the carbon silicon oxide spacer-2 layer 1102 near the central electrode-related region;

Step 128: Remove the oxide spacer layer 304, the central electrode 1302, and the padding oxide layer 204 near the central electrode.

Please refer to Figures 4D, 16, 17, and 18. Step 30 includes:

Step 130: Form a gate dielectric layer 1502 in the gate region;

Step 132: Deposit gate conductive material 1504 in the gate region, and then etch back the gate conductive material 1504;

Step 134: Form the cap layer 1506 and polish the cap layer 1506 by the chemical mechanical polishing technology;

Step 136: Shallow erosion trench isolation zone 402;

Step 138: Etch away the lining nitride layer 206 and the lining oxide layer 204 to expose the original horizontal surface OHS;

Step 140: Form oxide spacer-2 layer 1802 and nitride spacer-2 layer 1804 on the edge of gate conductive material 1504 and cap layer 1506.

Please refer to Figures 4E, 19, 20, 21, and 22. Step 40 includes:

Step 142: Etch away the exposed silicon;

Step 144: Thermal growth of oxide-3 layers of 1002;

Step 146: Form nitride layer 1904;

Step 148: Formation of tungsten layer 1906;

Step 150: Forming a titanium nitride (TiN) layer 1908;

Step 152: Etch away the oxide layer - part of the 3-layer 1002;

Step 154: Form n-type lightly doped drains (LDDs) 2004 and 2006, and then form n+ doped source 2008 and n+ doped drain 2010.

The manufacturing method described above is explained in detail below. Taking an N-type metal-oxide-semiconductor (MODS) as an example, the process begins with a well-designed doped p-type well 202 mounted in a semiconductor substrate 200 (e.g., a p-type semiconductor substrate). (In another embodiment of the invention, the process may begin with the semiconductor substrate 200 instead of the p-type well 202). In one embodiment of the invention, the top surface of the p-type well 202 is approximately 500 nm thick from the original horizontal surface (OHS). Additionally, the semiconductor substrate 200, for example, has a doping concentration close to 1 x ^10¹⁶ dopant/ ^cm³ , however, the actual doping concentration will be determined by final mass production optimization.

In step 102, as shown in Figure 5(a), a lining oxide layer 204 with a well-designed thickness is grown above the original horizontal surface OHS, and a lining nitride layer 206 with a well-designed thickness is deposited above the top surface of the lining oxide layer 204.

In step 104, as shown in Figure 5(a), the active region of the vertical thin-film field-effect transistor is defined using the anisotropic etching technique via the photolithography technique. The anisotropic etching technique removes a portion of the semiconductor material (e.g., silicon) outside the active region to form trenches (e.g., approximately 300 nanometers (nm) deep) to meet the future requirement of generating shallow trench isolation regions 402, thereby also creating the convex structure of the active region. Additionally, Figure 5(b) is a top view corresponding to Figure 5(a), where Figure 5(a) is a cross-sectional view along the X-direction cut line shown in Figure 5(b).

In step 106, as shown in FIG6(a), an oxide spacer layer 304 is deposited at the edge of the active region, and then a nitride spacer layer 306 is deposited on the oxide spacer layer 304 (or only at the edge of the active region). The anisotropic etching technique is used to etch back the oxide spacer layer 304 and the nitride spacer layer 306 so that the top surfaces of the oxide spacer layer 304 and the nitride spacer layer 306 are flush with the original horizontal surface OHS, wherein the oxide spacer layer 304 and the nitride spacer layer 306 are located outside the active region. Therefore, the key to step 106 is that the oxide spacer layer 304 and the nitride spacer layer 306 (or only the nitride spacer layer 306) form a robust fence (i.e., an isolation wall) to clamp the active region or the narrow convex structure, especially the sidewalls of the convex structure. Additionally, the robust fence can be a single layer (e.g., the nitride spacer layer 306) or other composite layers (e.g., oxide spacer layer 304 and nitride spacer layer 306) to protect the narrow convex structure or the finned structure from collapse during the formation of the source/drain or gate region of the vertical thin-body field-effect transistor.

In step 108, as shown in Figure 7(a), a thick oxide layer is deposited to completely fill the trench surrounding the active region, and the excess oxide layer is removed using the chemical mechanical polishing technique to form a shallow trench isolation region 402, wherein the top surface of the shallow trench isolation region 402 is flush with the top surface of the backing nitride layer 206. Similarly, the shallow trench isolation region 402 further surrounds or clamps the active region or the narrow convex structure, especially the sidewalls of the convex structure, to protect the narrow convex structure from collapse during the formation of the source/drain or gate region of the vertical thin-body field-effect transistor.

In step 110, as shown in FIG7(a), a nitrided layer 802 is deposited above the nitrided pad layer 206 and the shallow groove isolation area 402. FIG7(b) is a top view corresponding to FIG7(a), wherein FIG7(a) is a cross-sectional view along the X-direction cut line shown in FIG7(b).

In step 112, as shown in FIG8(a), a gate region spanning the active region and the shallow groove isolation region 402 is defined using a photomask 902, thereby removing the nitride layer 802 and the padding nitride layer 206 corresponding to the gate region to form a recess 904. FIG8(b) is a top view corresponding to FIG8(a), wherein FIG8(a) is a cross-sectional view along the X-direction cut line shown in FIG8(b), and FIG8(c) is a cross-sectional view along the Y-direction cut line shown in FIG8(b).

In step 114, as shown in FIG. 9(a), the photomask 902 is removed. This achieves a smooth edge for the gate region of the vertical thin-film field-effect transistor, and simultaneously defines the central electrode-related region within the active region, wherein the smooth edge is the edge of the nitride layer 802 and the padding nitride layer 206. FIG. 9(b) is a top view corresponding to FIG. 9(a), where FIG. 9(a) is a cross-sectional view along the X-direction cut line shown in FIG. 9(b).

In step 116, as shown in Figure 10(a), the silicon carbide layer (or a combination of the oxide layer and the nitride layer) is deposited in the central electrode-related region and etched back to form a silicon carbide spacer-2 layer 1102 (wherein, for example, the width of the silicon carbide spacer-2 layer 1102 may be 1~3 nm). As shown in Figure 10(b), the silicon carbide oxide spacer-2 layer 1102 is located on the four surrounding edges within the central pole region, and the silicon carbide oxide spacer-2 layer 1102 is used to protect the underlying virgin silicon region, which serves as the surrounding ring of silicon (or surrounding Si ring) on the central pole (SRS-CP) to be formed later.

In step 118, as shown in Figure 10(a), the anisotropic etching technique is then used to etch the pad oxide layer 204 and the semiconductor material of the semiconductor substrate 200 in the central electrode relevant region based on the silicon carbide oxide spacer-2 layer 1102 and the nitride layer 802 to form a recess (or trench) 1202 with a depth of about 50 to 80 nm (e.g., 75 nm) in the exposed silicon region. That is, the silicon carbide oxide spacer-2 layer 1102 and the nitride layer 802 act as a photomask so that the exposed pad oxide layer 204 in the central electrode relevant region is removed and the exposed silicon is also removed to a depth of about 75 nm to form the recess 1202 in the central electrode relevant region. Therefore, the silicon carbide oxide spacer-2 layer 1102 acts like a rain shelter to protect the silicon surrounding ring (SRS-CP) to be created. In addition, Figure 10(b) is a top view corresponding to Figure 10(a), where Figure 10(a) is a cross-sectional view along the X-direction cut line shown in Figure 10(b) and Figure 10(c) is a cross-sectional view along the Y-direction cut line shown in Figure 10(b).

In step 120, as shown in Figure 11(a), the dielectric layer is formed (e.g., by short-time growth of thermal oxides or chemical vapor deposition (CVD) deposition) as a central electrode 1302 to fill the recess 1202, wherein the central electrode 1302 is also referred to as a central oxide pole or column pole (CP).

In step 122, as shown in Figure 11(a), the nitride-3 layer is then deposited and etched back to form a nitride cap layer 1402 above the central electrode 1302 to protect the central electrode 1302. Additionally, Figure 11(b) is a top view corresponding to Figure 11(a), where Figure 11(a) is a cross-sectional view along the X-direction cut line shown in Figure 11(b), and Figure 11(c) is a cross-sectional view along the Y-direction cut line shown in Figure 11(b).

In step 124, as shown in FIG12(a), the exposed shallow groove isolation region 402 is etched back to a depth of approximately 50-80 nm to form a vertical convex structure in the defined gate region. For example, the shallow groove isolation region 402 in the defined gate region is etched downwards by approximately 75 nm (i.e., the height of the convex structure). In one embodiment of the present invention, the height of the convex structure is the same as or substantially the same as the height of the center electrode 1302 calculated from the original horizontal surface OHS of the p-type well 202 to the bottom of the center electrode 1302. Additionally, FIG12(b) is a top view corresponding to FIG12(a), wherein FIG12(a) is a cross-sectional view along the Y-direction cut line shown in FIG12(b).

In step 126, as shown in FIG13(a), etching is used to remove the nitride cap 1402, the silicon carbide oxide spacer-2 layer 1102, the nitride layer 802, and the nitride spacer layer 306 covering the convex structure in the defined gate region near the central electrode-related region. Thus, the previously defined central electrode-related region reappears. In addition, FIG13(b) is a top view corresponding to FIG13(a), wherein FIG13(a) is a cross-sectional view along the X-direction cut line shown in FIG13(b), and FIG13(c) is a cross-sectional view along the Y-direction cut line shown in FIG13(b).

In step 128, as shown in FIG14(a), the lining oxide layer 204 near the central electrode region and the oxide spacer layer 304 covering the convex structure are removed by etching. The shallow trench isolation region 402 outside the defined gate region is also etched to a certain extent (e.g., about 40-80 nm deep), so that the top surface of the shallow trench isolation region 402 outside the defined gate region is lower than the top surface of the lining nitride layer 206. Therefore, as shown in FIG14(c), the two outer sides of the single crystal silicon of the convex structure are exposed. More importantly, as shown in Figure 14(b), the silicon surrounding ring (SRS-CP) is present on the central electrode 1302. Additionally, Figure 14(b) is a top view corresponding to Figure 14(a), where Figure 14(a) is a cross-sectional view along the X-direction cut line shown in Figure 14(b), and Figure 14(c) is a cross-sectional view along the Y-direction cut line shown in Figure 14(b).

Subsequently, as shown in Figure 15(a), the center electrode 1302 is removed to expose the groove-2 1501. As shown in Figure 15(c), in this convex structure, there are two vertical thin bodies, Sright and Sleft, used to conduct current during the conduction state of the vertical thin-body field-effect transistor, wherein the vertical thin body Sright has an outer wall and an inner wall adjacent to the groove-2 1501, and the vertical thin body Sleft also has an outer wall. As shown in Figure 15(c), in the groove-2 1501, the inner wall of the vertical thin body Sright faces the inner wall of the vertical thin body Sleft. Additionally, Figure 15(b) is a top view corresponding to Figure 15(a), wherein Figure 15(a) is a cross-sectional view along the X-direction cutting line shown in Figure 15(b) and Figure 15(c) is a cross-sectional view along the Y-direction cutting line shown in Figure 15(b).

In step 130, as shown in Figure 16(a), a gate dielectric layer (e.g., a high-k material or oxide) 1502 is then formed in the defined gate region.

In step 132, as shown in Figure 16(a), a gate conductive material (e.g., polycrystalline silicon, or a metal such as tungsten on a titanium nitride layer, or other metals with a suitable work function) 1504 is then deposited in the gate region. Excess gate conductive material 1504 is removed using the chemical mechanical polishing technique, followed by etching/polishing of the gate conductive material 1504. Of course, in the presence of a gate last process, the previously formed gate conductive material 1504 can be removed and replaced with another suitable gate conductive material. The portion of the gate conductive material 1504 in the trench-2 1501 can be referred to as the "conductive central pole," and this conductive central pole is surrounded by the gate dielectric layer 1502 in the trench-2 1501. Additionally, Figure 16(b) is a top view corresponding to Figure 16(a), where Figure 16(a) is a cross-sectional view along the X-direction cut line shown in Figure 16(b), and Figure 16(c) is a cross-sectional view along the Y-direction cut line shown in Figure 16(b).

In step 134, as shown in Figure 17(a), a cap layer 1506, consisting of a nitride layer 15062 and a hard mask-oxide layer 15064, is deposited in the gate region on the top surface of the gate conductive material 1504. The cap layer 1506 serves to protect the gate conductive material 1504. Then, the cap layer 1506 is polished using a chemical mechanical polishing technique so that the top surface of the cap layer 1506 is flush with the top surface of the backing nitride layer 206.

In step 136, as shown in FIG17(a), the shallow trench isolation region 402 is then etched (and the gate dielectric layer 1502 above the shallow trench isolation region 402 is etched as well) so that the top surface of the shallow trench isolation region 402 is flush with the top surface of the padding oxide layer 204. In addition, FIG17(b) is a top view corresponding to FIG17(a), wherein FIG17(a) is a cross-sectional view along the X-direction cut line shown in FIG17(a).

In step 138, as shown in Figure 18(a), the padding nitride layer 206 and the padding oxide layer 204 are etched away to expose the original horizontal surface OHS. Furthermore, a portion of the shallow groove isolation region 402 is etched back to make the top surface of the shallow groove isolation region 402 flush with the original horizontal surface OHS.

In step 140, as shown in FIG18(a), an oxide-2 layer is deposited on the edge of the gate material 1504 and the cap layer 506 to form an oxide spacer-2 layer 1802, and a nitride-2 layer is deposited to form a nitride spacer-2 layer 1804 on the edge of the gate material 1504 and the cap layer 506. FIG18(b) is a top view corresponding to FIG18(a), wherein FIG18(a) is a cross-sectional view along the X-direction cut line shown in FIG18(b).

In step 142, as shown in Figure 19(a), some of the exposed silicon in the active region is then etched away to form shallow trenches 1902 for the source and drain regions (e.g., about 50 nm to 60 nm deep) of the vertical thin-body field-effect transistor.

In step 144, as shown in Figure 19(a), a thermal oxidation process known as the oxide-3 process is used to grow an oxide-3 layer 1002 (comprising an oxide-3V layer 10022 (assuming a sharp crystal orientation (110)) penetrating the vertical sidewalls of the vertical thin-body field-effect transistor) and an oxide-3B layer 10024 above the bottom of the shallow trench 1902. This is because some sidewalls of the shallow trench 1902 have a vertical composite material of oxide spacer-2 layers 1802 and nitride spacer-2 layers 1804, and Furthermore, the sidewalls of the shallow trench 1902 are further surrounded by the shallow trench isolation region 402, so the oxide-3 process should only grow a small amount of oxide (i.e., oxide-3 layer 1002) on these walls, thereby making the width of the source/drain region of the vertical thin-body field-effect transistor actually unaffected by the thermal oxidation process. Additionally, the thicknesses of oxide-3V layer 10022 and oxide-3B layer 10024 appearing in Figure 19(a) and subsequent figures are only for illustrative purposes, and oxide-3V layer 10022... The geometry of the 022 and oxide-3B layers 10024 is not proportional to the dimensions of the shallow trench isolation regions 402 shown in the figures. For example, the thickness of the oxide-3V layer 10022 and oxide-3B layer 10024 is approximately 20-30 nm, but the vertical height of the shallow trench isolation regions 402 can be approximately 200-250 nm. Based on this oxide-3 process, the thickness of the oxide-3V layer 10022 can be controlled very precisely under precise control of the thermal oxidation temperature, time, and growth rate. Since the thermal oxidation process on the defined silicon surface results in the removal of 40% of the thickness of the oxide-3V layer 10022, the thickness of the silicon surface (110) exposed in the vertical wall of the body of the vertical thin-body field-effect transistor and the remaining 60% of the thickness of the oxide-3V layer 10022 are considered as additions outside the vertical wall of the body of the vertical thin-body field-effect transistor. Furthermore, in one embodiment of the invention, the edge of the oxide-3V layer 10022 may be aligned with or substantially aligned with the edge of the gate region.

In step 146, as shown in Figure 19(a), nitride is deposited on the top surface of oxide-3B layer 10024 using the chemical vapor deposition technique, and the nitride is etched back to form nitride layer 1904. Additionally, Figure 19(b) is a top view corresponding to Figure 19(a), where Figure 19(a) is a cross-sectional view along the X-direction cut line shown in Figure 19(b).

In step 148, as shown in Figure 20(a), tungsten is deposited and etched back to form a tungsten layer 1906 on the top surface of the nitride layer 1904.

In step 150, as shown in Figure 20(a), titanium nitride is then deposited (e.g., atomic layer deposition (ALD)) and etched back to form a titanium nitride layer 1908 over the top surface of tungsten layer 1906. Additionally, Figure 20(b) is a top view corresponding to Figure 20(a), where Figure 20(a) is a cross-sectional view along the X-direction cut line shown in Figure 20(b).

In step 152, as shown in Figure 21(a), the top surface of the titanium nitride layer 1908 is then used as a reference to etch away a portion of the oxide-3V layer 10022 to expose the silicon sidewall 2002 (which has a crystal orientation (110)).

In another embodiment of the present invention, the steps of forming tungsten layer 1906 and titanium nitride layer 1908 in FIG20 can be omitted, and the portion of etched oxide-3V layer 10022 in FIG21 can be referenced by the top surface of nitride layer 1904.

In step 154, as shown in Figure 21(a), a selective growth technique (e.g., selective epitaxy growth (SEG) technique) is then used to form n-type lightly doped absorbers 2004 and 2006, followed by the formation of n+ doped source 2008 and n+ doped absorber 2010. It is worth mentioning that no ion distribution is required when forming all the n-type lightly doped drains 2004, 2006, n+ doped sources 2008, and n+ doped drains 2010 of this vertical thin-body field-effect transistor, and high-temperature thermal annealing is not required to eliminate the damage caused by the heavy bombardment during the formation of n+ doped sources 2008 and n+ doped drains 2010.

As shown in Figure 21(a), finally, titanium nitride layer 2012 and tungsten layer 2014 are deposited (e.g., this can be done by atomic layer deposition) and etched back. In one embodiment of the invention, as shown in Figure 21(a), the bottom of the conductive center electrode is lower than the bottom of the oxide-3B layer 10024, and the heights of the n+ doped source electrode 2008 and the n+ doped drain electrode 2010 are approximately 40–60 nm.

In one embodiment of the invention, the height of the convex structure (approximately 75 nm) is approximately 10–30 nm (e.g., 20 nm) higher than the heights of the n+ doped source 2008 and n+ doped drain 2010 (or the heights of the titanium nitride layer 2012 and tungsten layer 2014). Therefore, the gap between the bottom of the gate region and the n+ doped source 2008 and n+ doped drain 2010 (or the bottom of the titanium nitride layer 2012 and tungsten layer 2014) is approximately 10–30 nm (e.g., 20 nm). In other words, the bottom of the gate region (gate dielectric layer 1502 or gate conductive material 1504) is lower than the bottom of the n+ doped source 2008 and the n+ doped drain 2010 (or the bottom of the titanium nitride layer 2012 and the tungsten layer 2014).

As shown in Figure 21(c), which is a schematic diagram illustrating that the vertical thin-body field-effect transistor has three vertical gate conductive portions G1 to G3, wherein the vertical gate conductive portions G1 to G3 are connected by the top gate conductive portion 15042 of the gate conductive material 1504. As mentioned above, the four vertical sidewalls of the convex structure are covered by the gate dielectric layer 1502 and the gate conductive material 1504. In the vertical gate conductive section G1, the gate conductive material 1504, oxide (i.e., gate dielectric layer 1502), and semiconductor material (i.e., p-type well 202) form a conductor-oxide-semiconductor structure 2102 along one outer wall of the convex structure, wherein the conductor-oxide-semiconductor structure 2102 is similar to a metal-oxide-semiconductor (MOS) structure. Similarly, in the vertical gate conductive section G3, the gate conductive material 1504, oxide (i.e., gate dielectric layer 1502), and semiconductor material (i.e., p-type well 202) form a conductor-oxide-semiconductor structure 2104 along the other outer wall of the convex structure. Similarly, in the vertical gate conductive portion G2 (or the conductive center pole), two more conductor-oxide-semiconductor structures 2106 and 2108 are formed along the inner wall of the convex structure by the gate conductive material 1504, oxide (i.e., gate dielectric layer 1502), and semiconductor material (i.e., p-type well 202). Therefore, there are four conductor-oxide-semiconductor structures (or metal-oxide-semiconductor (MOS) structures) 2102, 2104, 2106, and 2108. According to the present invention, the unique feature of the above embodiments is that the four conductor-oxide-semiconductor structures 2102, 2104, 2106, and 2108 share a source region and a drain region in the vertical thin-body field-effect transistor. However, the present invention can be applied to the convex structure having multiple (e.g., 6 or 8) conductor-oxide-semiconductor structures (or metal-oxide-semiconductor MOS structures).

In another embodiment of the present invention, the material of the vertical gate conductive part G2 may be different from or the same as the material of the vertical gate conductive parts G1, G3 (or the top gate conductive part 15042).

Furthermore, as shown in Figure 21(a), due to the presence of the silicon surrounding ring in the convex structure, the length B of the gate conductive layer above the original horizontal surface OHS is longer than the length A of the conductive center electrode. Additionally, the transverse length of the outer wall of the convex structure is greater than the transverse length of the inner wall of the convex structure. Figure 21(b) is a top view corresponding to Figure 21(a), where Figure 21(a) is a cross-sectional view along the X-direction cut line shown in Figure 21(b), and Figure 21(c) is a cross-sectional view along the Y-direction cut line shown in Figure 21(b).

Additionally, as shown in Figure 22, when the bonding pad 2202 is formed on the n+ doped source 2008 and the n+ doped drain 2010, at least two sides (one sidewall and one top) of the n+ doped drain 2010 (or the n+ doped source 2008) are in contact with the titanium nitride layer 2012/tungsten layer 2014 and the bonding pad 2202. Therefore, the contact resistance of the n+ doped source 2008 and the n+ doped drain 2010 is correspondingly reduced.

Figure 23 illustrates the technology computer-aided design (CAD) for the turn-on current Ion of a conventional fin-type field-effect transistor (FinFET) and this vertical thin-body field-effect transistor. A schematic diagram of the simulation results of the Design (TCAD), in which the conventional fin field-effect transistor (the middle diagram of Figure 23) has a gate dielectric layer with an 8nm fin width, a 70nm fin height, and a 1nm thickness, and the vertical thin-body field-effect transistor (the left diagram of Figure 23) has a 1.5nm vertical thin body Sright, a 1.5nm vertical thin body Sleft, and a 1nm thick gate dielectric layer covering the vertical thin bodies Sleft and Sright, wherein the center electrode (not shown in Figure 23) is located between the vertical thin bodies Sleft and Sright. When a suitable gate metal material is used to adjust the work function of the center electrode and/or the gate conductive material 1504, the current density of the vertical thin-body MOSFET in the conducting state (shown by the blue curve) is 7 times that of the conventional fin MOSFET in the conducting state (shown by the brown dashed line), and the turn-on current Ion of the vertical thin-body MOSFET is approximately twice that of the conventional fin MOSFET. It is worth noting that due to the vertical thin bodies Sleft and Sright, multiple current conduction channels exist in this vertical thin-body MOSFET.

On the other hand, Figure 24 is a schematic diagram illustrating the simulation results of the Technology Computer-Aided Design (TCAD) for the turn-off current Ioff of the conventional fin field-effect transistor and the vertical thin-body field-effect transistor. Based on the same structure, as shown in the right figure of Figure 24, the current density of the conventional fin field-effect transistor in the off state (marked by the brown dashed line) is 14 times that of the vertical thin-body field-effect transistor in the off state (marked by the blue curve), and the turn-off current Ioff of the conventional fin field-effect transistor is approximately 34 times that of the vertical thin-body field-effect transistor. Thus, compared to the traditional finned field-effect transistor, this vertical thin-body field-effect transistor effectively increases the Ion/Ioff ratio by approximately 68 times.

Furthermore, since the width of the vertical thin body Sleft/vertical thin body Sright is approximately 1.5–3 nm (i.e., the width of the silicon wrapping ring is approximately 1.5–3 nm), in another embodiment of the present invention, when selectively growing n-type lightly doped drains 2004, 2006 and highly doped semiconductor regions (n+ doped source 2008 and n+ doped drain 2010) at a predetermined temperature, the edge of the n-type lightly doped drain 2006 can move laterally to contact the gate dielectric layer 1502, and the same applies to the edge of the n-type lightly doped drain 2004. Therefore, in this embodiment, the effective channel length of the vertical thin-body field-effect transistor can be shorter than the effective channel length (Leff) of the vertical thin-body field-effect transistor shown in FIG21(a).

Figure 25 is a schematic diagram illustrating the structural differences between the conventional fin field-effect transistor and the vertical thin-body field-effect transistor. As shown in Figure 25(a), in the conventional fin field-effect transistor, to increase the turn-on current Ion, there are typically two (or more) independent fin structures separated by a shallow trench isolation region located between the two independent fin structures. A gate region (gate dielectric layer and gate conductive layer) spans the two independent fin structures and the shallow trench isolation region between them. Then, each end of the fin structure provides a seed region for selective epitaxial growth of lightly doped drain regions and heavily doped semiconductor regions. Thus, the two N+ regions 2502 and 2504 of the two fin structures are grown separately by selective epitaxial growth (SEG) technology, and because the two N+ regions 2502 and 2504 grown in this conventional fin field-effect transistor are not restricted by shallow trench isolation regions, the N+ regions 2502 and 2504 will gradually expand like two independent mushrooms, eventually leading to the N+ regions 2502 and 2504 being connected together. Therefore, the traditional fin field-effect transistor in Figure 25(a) comprises two (or more) independent fin structures, each with a width of 6 nm. The width of the shallow groove isolation region between the two independent fin structures can be 25 nm, and the width of the shallow groove isolation region between the traditional fin field-effect transistor and another traditional fin field-effect transistor is also 25 nm. Therefore, the pitch distance between the traditional fin field-effect transistor and another traditional fin field-effect transistor in Figure 25(a) is 62 nm.

However, as shown in Figure 25(b), in one embodiment of the present invention, as previously described, only a convex structure is formed on the semiconductor substrate, and a groove is formed in the convex structure, thereby creating two vertical thin bodies. However, there is no shallow groove isolation area between the two vertical thin bodies. The gate region (gate dielectric layer and gate conductive layer) then spans the two vertical thin bodies and the trench between them. The portion of the gate conductive layer within the trench (i.e., the aforementioned central electrode) is surrounded by the gate dielectric layer, specifically along the four sidewalls and bottom of the trench surrounding the central electrode. The bottom of the trench remains below the semiconductor material of the semiconductor substrate. Therefore, there is no shallow trench isolation region between the two vertical thin bodies.

As shown in Figure 25(b), even with two vertical thin bodies, due to the presence of the aforementioned silicon-encircling ring, one exposed end of the silicon-encircling ring provides only one seed region for selective epitaxial growth of the lightly doped drain region and the heavily doped semiconductor region, rather than two separate seed regions. Furthermore, in the embodiment of Figure 25(b), the N+ region 2506 of the vertical thin-body MOSFET will be grown in a recess confined by a shallow trench isolation region using selective epitaxial growth (SEG) technology as described in Figure 21. Thus, the body of the vertical thin-film field-effect transistor in Figure 25(b) comprises only a convex structure (or fin structure) with two upwardly extending vertical thin films, each with a width of approximately 1.5 nm and a height of approximately 50–70 nm. Within each vertical thin film, two conductor-oxide-semiconductor structures or two conduction channels (located within the vertical thin film's VTB, as shown in Figure 25(b)) exist along the two sidewalls of the vertical thin film. In the embodiment of Figure 25(b), as previously described, due to lateral displacement caused by the thermal process, the lightly doped drain region of the source/drain region contacts the two vertical thin films. The width of the shallow groove isolation region between the vertical thin-body field-effect transistor and the other vertical thin-body field-effect transistor can be 12 nm. Therefore, the spacing between the vertical thin-body field-effect transistor and the other vertical thin-body field-effect transistor in Figure 25(b) is 22 nm.

Furthermore, Figure 25(c) corresponds to another embodiment of the invention, wherein the main difference between Figure 25(c) and Figure 25(b) is that the N+ region 2508 is not grown in a depression confined by a shallow trench isolation region. Therefore, the N+ region 2508 can gradually expand like a mushroom. It is worth noting again that even though there are two vertical thin bodies in this convex structure, due to the presence of the aforementioned silicon-encircling ring, one exposed end of the silicon-encircling ring provides only one seed region for the selective epitaxial growth of the lightly doped drain region and the heavily doped semiconductor region, rather than two separate seed regions.

Additionally, please refer to Figure 26, which is a schematic diagram illustrating the formation of the center electrode 2601 according to the second embodiment of the present invention, wherein Figure 26 is a continuation of Figure 10. As shown in Figure 26(a), a conformal dielectric liner 2602 is first deposited in the recess (or groove) 1202, wherein the electrode length Lpole used to form the air electrode should be 8~30 nanometers (nm). Then, a non-conformal dielectric 2604 is deposited in the recess 1202 to form an air electrode 2606, wherein the air electrode 2606 has a 2-4 nm non-conformal dielectric 2604 on top, and the central electrode 2601 is composed of a conformal dielectric pad 2602, a non-conformal dielectric 2604, and an air electrode 2606. In addition, as shown in FIG26(a), the nitride-3 layer is then deposited and etched back to form a nitride cap layer 1402 protecting the central electrode 2601 above it. Additionally, as shown in Figures 26(b) and 26(c), a shallow groove isolation region 402 of approximately 75 nm is then etched downwards within the gate region to form the height of the convex structure. Furthermore, Figure 26(b) is a top view corresponding to Figure 26(a), where Figure 26(a) is a cross-sectional view along the X-direction cut line shown in Figure 26(b), and Figure 26(c) is a cross-sectional view along the Y-direction cut line shown in Figure 26(b).

Continuing with Figure 26, the silicon carbide oxide spacer-2 layer 1102, the nitride cap layer 1402 and the padding oxide layer 204 in the gate region are removed, and the non-compliant dielectric 2604 is etched down to the original horizontal surface OHS. Then, as shown in Figures 26-1(a) and 26-1(b), a gate dielectric layer (e.g., a high-k material or oxide) 1502 is formed in the gate region. Subsequently, a gate conductive material (e.g., polycrystalline silicon, or a metal such as tungsten on a titanium nitride layer, or other metals with a suitable work function) 1504 is deposited in the gate region to cover the center electrode 2601. The excess gate conductive material 1504 is removed using the chemical mechanical polishing (CMP) technique, and then the gate conductive material 1504 is etched back/polished. Additionally, following Figure 26-1, Figures 16, 17, 18, 19, 20, 21, and 22 can be performed without removing the air electrode 2606 to complete the vertical thin body field-effect transistor (VTBFET). Figure 26-1(b) is a top view corresponding to Figure 26-1(a), where Figure 26-1(a) is a cross-sectional view along the Y-direction cut line shown in Figure 26-1(b). Then, the source/drain regions are formed as previously described with respect to Figures 19-22.

Additionally, please refer to Figures 27, 28, 29, 30, 31, 32, 33, and 34. Figures 27, 28, 29, 30, 31, 32, 33, and 34 are schematic diagrams illustrating the formation of a vertical thin-body field-effect transistor with a tapered central pole according to a third embodiment of the present invention, wherein the tapered central pole is a tapered groove filled with gate conductive material. The third embodiment begins with FIG27, as shown in FIG27(a). The difference between FIG27(a) and FIG5(a) is that a semiconducting layer 2702 (e.g., a germanium siliconization layer) is formed below the pad oxide layer 204. FIG27(b) is a top view corresponding to FIG27(a), and FIG27(a) is a cross-sectional view along the X-direction cut line shown in FIG27(b). FIG6 and FIG7 are then executed after FIG27 to obtain FIG28, where FIG28(b) is a top view corresponding to FIG28(a), and FIG28(a) is a cross-sectional view along the X-direction cut line shown in FIG28(b).

Continuing with Figure 28, as shown in Figure 29(a), a photomask 2902 is deposited on the nitride layer 802. Then, using the anisotropic etching technique and the pattern of the photomask 2902, a portion of the nitride layer 802, the nitride layer 206, the oxide layer 204, the semiconductor layer 2702, and the shallow trench isolation region 402 are removed to form a recess 2904. Additionally, Figure 29(b) is a top view corresponding to Figure 29(a), where Figure 29(a) is a cross-sectional view along the X-direction cut line shown in Figure 29(b), and Figure 29(c) is a cross-sectional view along the Y-direction cut line shown in Figure 29(b).

Continuing with Figure 29, as shown in Figure 30(b), a photomask 3002 is deposited outside the gate region. Then, using the anisotropic etching technique, shallow trench isolation region 402, oxide spacer layer 304, and nitride spacer layer 306 are etched downwards within the gate region. Additionally, Figure 30(b) is a top view corresponding to Figure 30(a), where Figure 30(a) is a cross-sectional view along the Y-direction cutting line shown in Figure 30(b).

Then, as shown in Figure 31(a), the photomask 3002 is removed, and a thin body 3102 (epitaxy layer) is formed using a selective growth technique (e.g., selective epitaxy growth, SEG). The thin body 3102 is then etched back to align its top surface with the original horizontal surface OHS. This forms a semiconductor body comprising a bottom portion (p-well 202) and a recessed portion (thin body 3102). It is noteworthy that different in-situ doping concentrations of the thin body 3102 (epitaxy layer) can result in different selective etching capabilities between the thin body 3102 (epitaxy layer) and the semiconductor layer 2702. Additionally, Figure 31(b) is a top view corresponding to Figure 31(a), where Figure 31(a) is a cross-sectional view along the X-direction cut line shown in Figure 31(b), and Figure 31(c) is a cross-sectional view along the Y-direction cut line shown in Figure 31(b). After Figure 31, oxide spacer-2 layers 1802 and nitride spacer-2 layers 1804 are formed along the sidewalls of the padding nitride layer 206 and the padding oxide layer 204, and then Figures 19 to 22 are performed to complete the source/drain region of the vertical thin-body field-effect transistor (as shown in Figure 32).

Continuing with Figure 32, as shown in Figure 33(a), the nitride layer 802, the backing nitride layer 206, the backing oxide layer 204, and the semiconductor layer 2702 are first removed to form a trench 3302 within the gate region. Then, a gate dielectric layer 1502 (e.g., a high-k material or oxide) is formed within the gate region to cover the sidewalls of the thin body 3102. Because the thin body 3102 (epithelial layer) and the semiconductor layer 2702 have different selective etching capabilities, the thin body 3102 (epithelial layer) can be left intact. Additionally, Figure 33(b) is a top view corresponding to Figure 33(a), where Figure 33(a) is a cross-sectional view along the X-direction cut line shown in Figure 33(b), and Figure 33(c) is a cross-sectional view along the Y-direction cut line shown in Figure 33(b). Subsequently, gate conductive material 1504 is deposited in the gate region, and Figure 17 is executed to complete the gate structure of the vertical thin-body field-effect transistor (as shown in Figure 34(a)). Furthermore, after completing the gate structure of the vertical thin-body field-effect transistor, a tapered central pole 3402 can be seen in Figure 34(c). Additionally, Figure 34(b) is a top view corresponding to Figure 34(a), wherein Figure 34(a) is a cross-sectional view along the X-direction cutting line shown in Figure 34(b) and Figure 34(c) is a cross-sectional view along the Y-direction cutting line shown in Figure 34(b).

Furthermore, it is evident that there is no shallow groove separating region 402 between the two thin bodies 3102 in the convex structure, and as shown in FIG. 34, the groove 3302 in the gate region separates the two thin bodies 3102, and the groove 3302 can be a tapered groove that is narrower at the top and wider at the bottom. In addition, in one embodiment of the invention, each thin body is tapered and extends upwards, and each thin body also includes two upwardly extending conductive channels, with two conductor-oxide-semiconductor surfaces along these two conductive channels. The two conductive channels of one thin body or the four conductive channels of two thin bodies are not parallel to each other. In one embodiment of the invention, the tapered thin body has a narrower upper portion and a wider lower portion, or the tapered thin body has a wider upper portion and a narrower lower portion. Of course, the invention is applicable not only to the above-described embodiments with one semiconductor body and two thin bodies, but also to embodiments with two or more thin bodies.

In summary, the convex structure of this vertical thin-body MOSFET contains a central electrode, and this conductive central electrode is surrounded by the gate dielectric layer 1502. Therefore, the conductive central electrode within the convex structure can effectively suppress the leakage current path of the vertical thin-body MOSFET in the off state. However, the vertical thin-body MOSFET still has multiple vertical thin bodies (i.e., vertical thin bodies Sright and Sleft) for conducting current during the on state. Furthermore, the width of, for example, the vertical thin body Sright (or vertical thin body Sleft) can be approximately 1.5–2 nm. Because the conductive center electrode is surrounded by silicon, the conductive current of the vertical thin-body field-effect transistor in the conducting state will diverge and then converge in the conducting channel region extending from the drain region to the source region.

Additionally, a robust fence (e.g., oxide spacer layer 304 and nitride spacer layer 306 as shown in FIG. 6) is formed to clamp the active region or the narrow convex structure, especially the sidewalls of the convex structure. This robust fence can be a single layer or other composite layer to protect the narrow convex structure from collapse during the formation of the source/drain region or the gate region of the vertical thin-body field-effect transistor. Furthermore, the shallow groove isolation region 402 (as shown in FIG. 7) also surrounds or clamps the active region or the narrow convex structure (especially the sidewalls of the narrow convex structure) to protect the narrow convex structure from collapse during the formation of the source/drain region or the gate region of the vertical thin-body field-effect transistor. Therefore, even if the height (e.g., 60–300 nm) of the convex structure of the vertical thin-body field-effect transistor is much greater than the width (e.g., 3–7 nm), the convex structure protected by the robust fence is still unlikely to collapse in subsequent processes (e.g., the formation of the source/drain region or the gate region).

Another advantage of this invention is that, because the thickness of the oxide-spacer-2 layer 1802 and the nitride-spacer-2 layer 1804 formed on the edge of the gate region (as shown in Figure 18) is controllable, and the oxide-3V layer 10022 and oxide-3B layer 10024 (as shown in Figure 19) formed by the thermal oxidation process are also controllable, the edge of the source region/drain region can be aligned or substantially aligned with the edge of the gate region (as shown in Figure 21), especially since the source region/drain region is formed by the selective epitaxial growth technique. Therefore, the relative position or distance between the edges of the source/drain regions and the gate region is controllable and depends on the thickness of the spacer layers (oxide spacer-2 layers 1802 and nitride spacer-2 layers 1804) and/or the thickness of the oxide layer (e.g., oxide-3V layer 10022) formed on the edge of the gate region. Thus, the effective channel length Leff can be controlled, thereby improving the problem of gate-induced drain leakage (GIDL) current.

In summary, this vertical thin-body field-effect transistor has the following advantages:

(1) Because of the presence of the conductive center electrode surrounded by the gate dielectric layer in the convex structure, the leakage current path of the vertical thin-body field-effect transistor in the OFF state can be reduced, and the conductive center electrode can effectively suppress the leakage current of the vertical thin-body field-effect transistor during the OFF state. In addition, there are multiple vertical thin bodies in the convex structure, and the multiple vertical thin bodies further increase the conduction current of the vertical thin-body field-effect transistor during the ON state.

(2) Taking a process with a minimum feature size (F) of 5nm as an example, the vertical thin-body field-effect transistor has multiple conductor-oxide-semiconductor structures and multiple conduction channels. Its structure dimensions are as follows: First, two vertical thin bodies with a width of about 1.5nm are fabricated. The thickness of the gate dielectric layer is about 1nm, the thickness of the inner gate (the conductive center electrode) is about 3nm, and the thickness of the convex structure is required to be about 8nm. Assuming the width of the shallow groove separating the two convex structures is 8 nm, the spacing (space plus width) between the two vertical thin bodies is approximately 16 nm (= 3.2 F), which is much smaller than the spacing of a traditional fin field-effect transistor, where the fin width is approximately 6 nm and the spacing between the two fins is approximately 24 nm. Therefore, the spacing between this traditional fin field-effect transistor and another traditional fin field-effect transistor is approximately 30 nm (= 6 F).

(3) Figures 23 and 24 illustrate the computer-aided design simulation results of the vertical thin-body MOSFET and the conventional fin MOSFET (or three-gate MOSFET). The ratio of the turn-on current Ion of the vertical thin-body MOSFET to that of the conventional fin MOSFET is approximately 2, and the ratio of the turn-off current Ioff of the conventional fin MOSFET to that of the vertical thin-body MOSFET is approximately 34, whereby the vertical thin-body MOSFET significantly improves these ratios. This improvement can be achieved by having a device width spacing of less than 4F for the vertical thin-body MOSFET and a device width spacing of 6F for the conventional fin MOSFET. Therefore, the yield of this vertical thin-body field-effect transistor is indeed much better, and it is worthwhile for a new structure with a fairly tolerable process complexity.

(4) The robust fence is used to clamp the active area or the narrow convex structure, especially the sidewalls of the convex structure. Thus, even if the height of the convex structure (e.g., 60-300 nm) is much greater than the width of the convex structure (e.g., 3-7 nm), the convex structure protected by the robust fence is still unlikely to be damaged.

(5) The relative position or distance between the edge of the source region/drain region and the edge of the gate region is controllable and depends on the thickness of the spacer layer formed on the edge of the gate region and/or the oxide layer (e.g., oxide-3V layer).

(6) The resistance of the source/drain region can be reduced by forming a metal semiconductor junction in the source/drain region.

(7) Most of the source/drain region is isolated by an insulating material, wherein the insulating material comprises a bottom structure consisting of an oxide-3B layer and/or a nitride-3 layer, so that the junction leakage current can be significantly reduced. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention shall be within the scope of the present invention.

5: Gate structure; 11: Source region; 12: Drain region; 13: n-lightly doped drain; 14: Effective channel; 16: Dashed rectangular region; 18: Red dashed rectangle; 200: Semiconductor substrate; 202: P-type well; 204: Backing oxide layer; 206: Backing nitride layer; 304: Oxide spacer layer; 306: Nitride spacer layer; 402: Shallow trench isolation region; 802, 1506, 1904: Nitride layer; 902: Photomask; 904, 1202, 2904: Recess; 1102: Silicon carbide oxide spacer-2 layer; 1302, 2601: Central electrode. 1402: Nitride cap layer; 1501: Groove-2; 1502: Gate dielectric layer; 1504: Gate conductive material; 15042: Top gate conductive section; 1506: Cap layer; 15064: Hard photomask oxide layer; 1802: Oxide spacer-2 layers; 1804: Nitride spacer-2 layers; 1902: Shallow groove; 1002: Oxide-3 layer; 10022: Oxide-3V layer; 10024: Oxide-3B layer; 1906, 2014: Tungsten layers; 1908, 2012: Titanium nitride layers; 2002: Silicon sidewall. 2004, 2006: n-type lightly doped drain; 2008: n+ doped source; 2010: n+ doped drain; 2102, 2104, 2106, 2108: Conductor-oxide-semiconductor structure; 2202: Bonding pad; 2502, 2504, 2506, 2508: N+ region; 2602: Compliant dielectric pad; 2604: Non-compliant dielectric; 2606: Air electrode; 2702: Semiconductor layer; 2902, 3002: Photomask; 3102: Thin body; 3302: Groove; 3402: Tapered center electrode; A, B: Length. G1~G3: Vertical gate conductive section; Leff: Effective channel length; Lpole: Pole length; OHS: Original horizontal surface; STI: Shallow groove isolation; Sright, Sleft, VTB: Vertical thin body; 10-50, 102-154: Steps

Figure 1 is a schematic diagram illustrating a fin field-effect transistor (FinFET) with an active region formed as a fin structure in the prior art. Figure 2 is a schematic diagram illustrating a higher leakage current path formed within the fin structure. Figure 3 illustrates the structure of a 3D fin FET under Technology Computer-Aided Design (TCAD) simulation, a cross-sectional view of the 3D fin FET structure, and a schematic diagram of the current distribution of the 3D fin FET in the off state. Figure 4A is a flowchart of a manufacturing method for a vertical thin body field-effect transistor (VTBFET) disclosed in an embodiment of the present invention. Figures 4B, 4C, 4D, and 4E are schematic diagrams illustrating Figure 4A. Figure 5 is a schematic diagram illustrating the growth of the lining oxide layer, the deposition of the lining nitride layer, and the formation of trenches. Figure 6 is a schematic diagram illustrating the deposition of an oxide spacer layer on top of the p-type well, followed by the deposition of a nitride spacer layer on top of the oxide spacer layer. Figure 7 is a schematic diagram illustrating the formation of a shallow trench isolation zone and the deposition of a nitride layer. Figure 8 is a schematic diagram illustrating the gate region spanning the active region and the shallow trench isolation zone. Figure 9 is a schematic diagram illustrating the removal of the lithography mask. Figure 10 is a schematic diagram illustrating the formation of a silicon carbide spacer-2 layer and the formation of a depression (or trench) based on the silicon carbide spacer-2 layer. Figure 11 is a schematic diagram illustrating the formation of a dielectric layer to fill the depression to form a central electrode, and then forming a nitride cap layer on top of the central electrode. Figure 12 is a schematic diagram illustrating the etching back of the exposed shallow trench isolation region to form the vertical convex structure in the defined gate region. Figure 13 is a schematic diagram illustrating the removal of the nitride cap and silicon carbide spacer-2 layer near the central electrode using etching. Figure 14 is a schematic diagram illustrating the removal of the backing oxide layer and the oxide spacer layer covering the convex structure near the central electrode region, as well as the etching of the shallow trench isolation region corresponding to the central electrode region. Figure 15 is a schematic diagram illustrating the removal of the central electrode to expose trench-2. Figure 16 is a schematic diagram illustrating the formation of the gate dielectric layer and the deposition of the gate conductive material in the gate region. Figure 17 is a schematic diagram illustrating the deposition of the cap layer and the etching of the shallow trench isolation region. Figure 18 is a schematic diagram illustrating the etching away of the padding nitride and padding oxide layers, the etchback of the shallow trench isolation region, and the formation of oxide-spacer-2 and nitride-spacer-2 layers at the edge of the gate region. Figure 19 is a schematic diagram illustrating the etching away of some exposed silicon to form shallow trenches for the source and drain regions of the vertical thin-body field-effect transistor, the growth of oxide-3 layers using a thermal oxidation process, and the deposition and etchback of nitrides using chemical vapor deposition. Figure 20 is a schematic diagram illustrating the deposition of a tungsten layer, followed by the deposition of a titanium nitride layer on top of the tungsten layer. Figure 21 is a schematic diagram illustrating the etching away of the oxide-3V layer to expose the silicon sidewalls, followed by the formation of an n-type lightly doped drain, an n+ doped source, and an n+ doped drain, and then the deposition of titanium nitride and tungsten layers. Figure 22 is a schematic diagram illustrating the formation of bonding pads on the n+ doped source and n+ doped drain. Figure 23 is a schematic diagram illustrating the computer-aided design simulation results of the turn-on current for conventional fin field-effect transistors and vertical thin-body field-effect transistors. Figure 24 is a schematic diagram illustrating the simulation results of computer-aided design of the turn-off current for a conventional fin-type field-effect transistor and a vertical thin-body field-effect transistor. Figure 25 is a schematic diagram illustrating the structural differences between the conventional fin-type field-effect transistor and the vertical thin-body field-effect transistor. Figures 26 and 26-1 are schematic diagrams illustrating the formation of the center pole and gate pole structure according to the second embodiment of the present invention. Figures 27, 28, 29, 30, 31, 32, 33, and 34 are schematic diagrams illustrating the formation of a vertical thin-body field-effect transistor with a tapered central pole according to the third embodiment of the present invention.

200: Semiconductor substrate

202: P-type well

304: Oxide spacer layer

306: Nitrided spacer layer

402: Shallow Ditch Isolation Area

15062, 1904: Nitrided layers

1502: Gate dielectric layer

1504: Gate conductive material

15042: Top gate conductive section

1506: Hat Layer

15064: Hard photomask oxide layer

1802: Oxide spacer -2 layers

1804: Nitride spacer -2 layers

1002: Oxide-3 layers

10022: Oxide-3V layer

10024: Oxide-3B layer

1906, 2014: Tungsten layer

1908, 2012: Titanium nitride layers

2002: Silicon Sidewall

2004, 2006: n-type lightly doped dipole

2008:n+Mixed Source

2010:n+mixed with extreme

2202: Joining Pads

3102: Thin Body

3402: Conical center pole

G1~G3: Vertical gate conductor section

OHS: Original horizontal surface

Claims (16)

A transistor structure comprising: a semiconductor body having a convex structure, wherein the convex structure includes a set of upwardly extending thin bodies and has at least four upwardly extending conductive channels, and each thin body includes two conductive channels along a sidewall of the at least four conductive channels; a source region in contact with a first end of the convex structure; a drain region in contact with a second end of the convex structure; and a gate region having a gate conductive layer, wherein the gate conductive layer spans over the convex structure; wherein two or all four conductive channels of the at least four conductive channels are not parallel to each other, and there is no shallow trench isolation (STI) region between the at least four conductive channels. The transistor structure as described in claim 1, wherein a groove is formed in the convex structure, the groove being located between the first end and the second end, and a first portion of the gate conductive layer is filled in the groove. The transistor structure as described in claim 2, wherein the bottom of the groove is higher than the bottom of the convex structure. The transistor structure as described in claim 3, wherein the trench is located between two of the thin bodies in the set of thin bodies, a gate dielectric layer spans over the convex structure, and a first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench. The transistor structure as described in claim 2, wherein the trench is tapered. The transistor structure as described in claim 2, wherein the convex structure includes at least four upwardly extending conductor-oxide-semiconductor surfaces, and the at least four conductor-oxide-semiconductor surfaces are horizontally offset from each other. A transistor structure comprising: a semiconductor body having a convex structure, wherein the convex structure has an original surface, the convex structure including two upwardly extending thin bodies, and the two thin bodies being separated from each other; a source region in contact with a first end of the convex structure; a drain region in contact with a second end of the convex structure; and a gate region having a gate conductive layer, wherein the gate conductive layer extends across the top of the convex structure; wherein each thin body is tapered, and there is no shallow groove isolation region between the two thin bodies. The transistor structure as described in claim 7, wherein a groove is formed in the convex structure, the groove being located between the first end and the second end, and a first portion of the gate conductive layer is filled in the groove. The transistor structure as described in claim 8, wherein each thin body comprises two upwardly extending conductive channels. The transistor structure as described in claim 9, wherein the trench separates the two thin bodies, a gate dielectric layer extends across the top of the convex structure, and a first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench. A transistor structure comprising: a semiconductor body having a convex structure, wherein the convex structure has an original surface and the convex structure includes two upwardly extending thin bodies; a source region in contact with a first end of the convex structure; a drain region in contact with a second end of the convex structure; a gate region having a gate conductive layer, wherein the gate conductive layer extends across the top of the convex structure; a trench formed in the convex structure and located between the first end and the second end, wherein the trench separates the two thin bodies; and an air electrode located in the trench and covered by the gate conductive layer. The transistor structure as described in claim 11, wherein the convex structure includes a first outer wall and a second outer wall covered by the gate conductive layer, and the convex structure further includes a first inner wall and a second inner wall within the groove. The transistor structure as described in claim 11 further includes: a first recess for accommodating the source region; and a second recess for accommodating the drain region; wherein the sidewalls of the first recess and the sidewalls of the second recess are surrounded by a shallow groove isolation region. The transistor structure as described in claim 13, wherein the edge of the source region is in contact with the two thin bodies, and the edge of the drain region is also in contact with the two thin bodies. The transistor structure as described in claim 14, wherein the source region comprises: a lightly doped drain (LDD) region in contact with the two thin bodies; a heavily doped region extending laterally from the lightly doped drain region; and a metal region located within the first recess and in contact with a sidewall of the heavily doped region. The transistor structure as described in claim 11, wherein the width of each thin body is not greater than 3 nanometers (nm).