TWI908505B - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device, including: a semiconductor substrate, including a first doping region having a first doping type, and a second doping region having a second doping type different from the first doping type; a dielectric layer being disposed above the first doped region; a first metal layer being disposed above the dielectric layer; and a second metal layer being disposed above the second doped region.

Description

semiconductor devices

This invention relates to a semiconductor device, and more particularly to a temperature sensing element.

LCD panels can be used in many applications, such as automotive displays. However, in low-temperature environments, the response time of LCDs increases, especially between -20°C and 10°C, where there are drastic changes, causing the display to be unable to show information in real time. Therefore, a temperature sensor must be added to the LCD panel to determine its temperature and whether it needs to be heated.

Traditional LCD panels typically use thin-film transistors (TFTs) for temperature sensing. Under sub-saturation conditions, these transistors suffer from unstable signals and low accuracy. Furthermore, when operating in off-state conditions, the signal from the temperature sensing element is weak in low-temperature environments and is easily affected by external interference, impacting the readability and accuracy of the temperature sensing element.

This invention provides a semiconductor device to improve the accuracy of temperature measurement.

The present invention provides a semiconductor device comprising: a substrate including a first doped region having a first doping type and a second doped region having a second doping type different from the first doping type; a dielectric layer disposed above the first doped region; a first metal layer disposed above the dielectric layer; and a second metal layer disposed above the second doped region.

In some embodiments of the present invention, the doping type of the first doped region is undoped, and the doping type of the second doped region is N-type or P-type.

In some embodiments of the present invention, the doping type of the first doped region is N-type or P-type, and the doping type of the second doped region is undoped.

In some embodiments of the present invention, the second doped region may be divided into a first part and a second part, wherein the first part and the second part have the same doping type, wherein the doping concentration of the first part is less than the doping concentration of the second part, and wherein the second part is in contact with the second metal layer.

In some embodiments of the present invention, the doping type of the second doped region is P-type or N-type.

In some embodiments of the present invention, the distance between the interface between the first doped region and the second doped region and the side surface of the dielectric layer is less than or equal to the effective carrier diffusion length of the dopant in the second doped region.

In some embodiments of the present invention, the distance between the interface between the first doped region and the second doped region and the side surface of the second metal layer is less than or equal to the effective carrier diffusion length of the dopant in the second doped region.

In some embodiments of the present invention, the dielectric layer is overlaid on the second doped region.

In some embodiments of the present invention, the second metal layer passes through the dielectric layer and is connected to the second doped region.

In some embodiments of the present invention, the semiconductor device further includes an insulating layer located between the first metal layer and the second metal layer for electrically isolating the first metal layer and the second metal layer.

Based on the above, the semiconductor device provided by this invention can significantly improve signal strength and avoid coupling interference compared to thin-film transistor temperature sensors, thereby improving accuracy. Furthermore, it can perform temperature measurement in either temperature-sensing current or temperature-sensing voltage modes as needed.

Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Please refer to Figure 1. The semiconductor device 100 includes: a substrate 110, a dielectric layer 120, a first metal layer 130, and a second metal layer 140.

The substrate 110 may be, for example, crystalline silicon, silicon-on-insulator, or other suitable elemental semiconductors.

The substrate 110 may be doped with a P-type dopant to become a P-type substrate, or doped with an N-type dopant to become an N-type substrate. As shown in FIG1, the substrate 110 includes a first doped region 112 having a first doping type, and a second doped region 114 having a second doping type different from the first doping type.

In some embodiments, the first doping region 112 is not doped with any dopant and has no doping type. In some embodiments, the second doping region 114 is doped with a type P dopant. In some embodiments, the second doping region 114 is doped with an type N dopant.

Since the first doped region 112 and the second doped region 114 have different doping types, a junction is formed at the interface between the first doped region 112 and the second doped region 114. Depending on the doping type of the first doped region 112 and the second doped region 114, this junction can be an I/N junction or an I/P junction.

In some embodiments, the first doping region 112 is doped with a type P dopant. In some embodiments, the first doping region 112 is doped with a type N dopant. In some embodiments, the second doping region 114 is not doped with any dopant and has no dopant type.

The dielectric layer 120 is located above the first doped region 112. In some embodiments, the material of the dielectric layer 120 may be silicon oxide, silicon nitride and/or silicon oxynitride, or other suitable materials, and this disclosure is not limited thereto.

The first metal layer 130 is located above the dielectric layer 120. In some embodiments, the material of the first metal layer 130 may be copper, titanium, tungsten, aluminum, or other suitable materials, and this disclosure is not limited thereto.

The second metal layer 140 is located above the second doped region 114. In some embodiments, the material of the second metal layer 140 may be copper, titanium, tungsten, aluminum, or other suitable materials, and this disclosure is not limited thereto. In some embodiments, the first metal layer 130 and the second metal layer 140 may be the same material or different materials.

Please refer to Figure 1. The semiconductor device 100 further includes an insulating layer 150 located between the first metal layer 130 and the second metal layer 140 for electrically isolating the first metal layer 130 and the second metal layer 140. In some embodiments, the material of the insulating layer 150 may be silicon oxide, silicon nitride and/or silicon oxynitride, or other suitable materials, and this disclosure is not limited thereto.

Figure 2 is a schematic diagram of a temperature sensing mode according to an embodiment of the present invention. In this embodiment, by applying a first voltage V1 to the first metal layer 130 and a second voltage V2 to the second metal layer 140, and by the induced charge causing a reverse bias voltage to be generated at the interface formed by the first doped region 112 and the second doped region 114 located in the substrate 110, the temperature can be sensed by measuring the second current I2 that changes with temperature through the second metal layer 140. The working principle is explained below.

Please refer to Figure 2. In Figure 2, the first doping region 112 has no dopant and no doping type. The second doping region 114 is doped with an N-type dopant, and the doping type is N.

In order to maintain the reverse bias operation at the interface formed by the first doped region 112 and the second doped region 114, a first voltage V1 is applied to the first metal layer 130 and a second voltage V2 is applied to the second metal layer 140, wherein V1 < V2.

When V1 < V2, the first metal layer 130 repels electrons, causing positive charges to accumulate on the surface of the dielectric layer 120 near the first metal layer 130 and negative charges to accumulate on the surface of the first doped region 112 near the substrate 110. Therefore, an effective first voltage V1' is generated at the interface 122 between the dielectric layer and the first doped region 112.

Therefore, the interaction between the second voltage V2 and the effective first voltage V1' at the interface formed by the first doped region 112 and the second doped region 114 allows for the measurement of an induced current I2 flowing out of the second metal layer 140 from the first metal layer 130 through the dielectric layer 120, the first doped region 112, and the second doped region 114. This induced current I2 varies with temperature.

In this embodiment, in order for electrons to flow from the first metal layer 130 through the dielectric layer 120, the first doped region 112, and the second doped region 114 into the second metal layer 140, the semiconductor device 100 must meet the following conditions.

As shown in Figure 1, the distance D1 between the interface between the first doped region 112 and the second doped region 114, i.e., the side surface 114S of the second doped region 114, and the side surface 120S of the dielectric layer 120 is less than or equal to the effective carrier diffusion length of the first doped region 112, i.e., electrons can successfully pass through the first doped region 112 into the second doped region 114.

Furthermore, as shown in Figure 1, the distance D2 between the interface between the first doped region 112 and the second doped region 114, i.e., the side surface 114S of the second doped region 114, and the side surface 140S of the second metal layer 140, is less than or equal to the effective carrier diffusion length of the dopant in the second doped region 114, meaning that electrons can successfully pass through the second doped region 114 into the second metal layer 140.

In some embodiments, if the second doped region 114 is doped with a P-type dopant, and the doping type is P-type, then in order to apply a reverse bias to the interface 114S formed by the first doped region 112 and the second doped region 114, a first voltage V1 is applied to the first metal layer 130 and a second voltage V2 is applied to the second metal layer 140, where V1 > V2.

Therefore, by applying a reverse bias voltage to the junction 114S formed by the first doped region 112 and the second doped region 114 through the first metal layer 130 and the second metal layer 140, the temperature-dependent induced current I2 can be measured in the second metal layer 140 for temperature measurement.

Since the measurement method here is to fix the first voltage V1 and the second voltage V2 and measure the current I2 that changes with temperature, it is also called constant voltage mode.

Figure 3 is a schematic diagram of another temperature sensing mode according to an embodiment of the present invention. In this embodiment, by applying a second voltage V2 and a fixed second current I2 to the second metal layer 140, temperature can be sensed by measuring the first voltage V1 of the first metal layer 130 as it changes with temperature. The temperature sensing voltage mode of the semiconductor device 100 will be described below. The working principle will be explained below.

Please refer to Figure 3. In Figure 3, the first doping region 112 has no dopant and no doping type. The second doping region 114 is doped with an N-type dopant, and the doping type is N.

A current I2 is injected into the second metal layer 140, and a second voltage V2 is provided to the second metal layer 140 to drive the interface formed by the first doped region 112 and the second doped region 114.

When a second voltage V2 is provided to the second metal layer 140 to drive the interface formed by the first doped region 112 and the second doped region 114, an effective first voltage V1'' can be sensed at the interface between the dielectric layer 120 and the first doped region 112.

Because the dielectric layer 120 remains electrically neutral, positive charges accumulate on the surface of the dielectric layer 120 near the first metal layer 130, and negative charges accumulate on the surface of the dielectric layer 120 near the first doped region 112 of the substrate 110. Therefore, the first metal layer 130 generates a first voltage V1 that changes with temperature.

In some embodiments, if the second doped region 114 is doped with a P-type dopant, and the doping type is P-type, then a first voltage V1 and a current I2 are applied to the first metal layer 130, and a second voltage V2 that changes with temperature is measured on the second metal layer 140.

Since the measurement method here is to fix the second voltage V2 and the current I2, and measure the first voltage V1 that changes with temperature, it is also called constant current mode.

Figure 4 is a schematic diagram of a semiconductor device according to another embodiment of the present invention. Referring to Figure 4, semiconductor device 100A is similar to semiconductor device 100 shown in Figure 1, wherein the same reference numerals correspond to the same components, and therefore will not be described in detail here.

The difference between semiconductor device 100A and semiconductor device 100 is that, in addition to covering the first doped region 112, dielectric layer 120A extends to cover the second doped region 114. Therefore, the manufacturing process of semiconductor device 100A can be simplified.

Furthermore, as shown in Figure 4, the second metal layer 140A passes through the dielectric layer 120A and is connected to the second doped region 114. Therefore, compared to Figure 1, the side surface of the second metal layer 140A is simultaneously connected to both the dielectric layer 120A and the insulating layer 150.

Furthermore, as shown in Figure 4, the second doped region 114 can be divided into a first portion 114A and a second portion 114B. As shown in Figure 4, the second portion 114B is connected to the second metal layer 140. The first portion 114A and the second portion 114B have the same doping type, wherein the doping concentration of the first portion 114A is less than the doping concentration of the second portion 114B. By controlling the doping concentration of the first portion 114A and the second portion 114B, the performance of the semiconductor device 100 as a function of temperature can be controlled, for example, by changing the temperature-dependent second current I2 in the embodiment shown in Figure 2, or by changing the temperature-dependent first voltage V1 in the embodiment shown in Figure 3.

Figure 5 shows the relationship between current signal and temperature in a semiconductor device and a conventional temperature sensing device according to an embodiment of the present invention.

Figure 5 shows the relationship between current I2 and temperature measured by the semiconductor device operating in constant voltage mode as shown in Figure 2. On the other hand, the relationship between current I1 and temperature measured by the thin-film transistor temperature sensor is compared.

As shown in Figure 5, under the condition of a fixed terminal voltage difference V12 = V1 - V2, the current I2 measured by the semiconductor device operating in constant voltage mode as shown in Figure 2 is greater than the current I1 measured by the thin-film transistor temperature sensor. In the temperature range of -40°C to 60°C, the ratio of I2/I1 is approximately between 41 and 67. It is evident that the current I2 measured by the semiconductor device is much greater than the current I1 measured by the thin-film transistor temperature sensor, which can significantly improve the measurement accuracy.

In addition, under temperature-sensing voltage operation, the sensing voltage terminal can be connected to the feedback circuit switch TFT. The rise and fall of the potential at the sensing voltage terminal can directly control the heating element without transmitting the sensing signal and then having the microcontroller feed back the signal to control the heating element through the core wiring, which simplifies the internal wiring design of the core.

In summary, the semiconductor device provided by this invention significantly improves signal strength and avoids coupling interference compared to traditional thin-film transistor temperature sensors, thereby enhancing accuracy. Furthermore, it can measure temperature using either temperature-sensing current or temperature-sensing voltage modes as needed.

100, 100A: Semiconductor Device 110: Substrate 112: First Doped Region 114: Second Doped Region 114A: First Part 114B: Second Part 114S, 120S, 140S: Side Surfaces 120, 120A: Dielectric Layer 122: Interface 130: First Metal Layer 140, 140A: Second Metal Layer 150: Insulating Layer D1, D2: Distance I2: Current V1: First Voltage V1’, V1’’: Effective First Voltage V2: Second Voltage

Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 is a schematic diagram of a temperature sensing mode according to an embodiment of the present invention. Figure 3 is a schematic diagram of another temperature sensing mode according to an embodiment of the present invention. Figure 4 is a schematic diagram of a semiconductor device according to another embodiment of the present invention. Figure 5 shows the relationship between current signal and temperature in a semiconductor device and a thin-film transistor temperature sensing device according to an embodiment of the present invention.

100: Semiconductor Devices

110: Base

112: First Mixed Area

114: Second Mixed Area

114S, 120S, 140S: Side surface

120: Dielectric layer

130: First metal layer

140: Second metal layer

150: Insulation Layer

D1, D2: Distance

Claims (9)

A semiconductor device includes: a substrate including a first doped region having a first doping type and a second doped region having a second doping type different from the first doping type; a dielectric layer disposed on the first doped region; a first metal layer disposed on the dielectric layer; and a second metal layer disposed on the second doped region, wherein the second doped region can be divided into a first portion and a second portion, wherein the first portion and the second portion have the same doping type, wherein the doping concentration of the first portion is less than the doping concentration of the second portion, and wherein the second portion is in contact with the second metal layer. The semiconductor device as claimed in claim 1, wherein the doping type of the first doped region is undoped, and the doping type of the second doped region is N-type or P-type. The semiconductor device as claimed in claim 1, wherein the doping type of the first doped region is N-type or P-type, and the doping type of the second doped region is undoped. The semiconductor device as claimed in claim 1, wherein the doping type of the second doped region is P-type or N-type. The semiconductor device of claim 1, wherein the distance between the interface between the first doped region and the second doped region and the side surface of the dielectric layer is less than or equal to the effective carrier diffusion length of the dopant of the second doped region. The semiconductor device of claim 1, wherein the distance between the interface between the first doped region and the second doped region and the side surface of the second metal layer is less than or equal to the effective carrier diffusion length of the dopant of the second doped region. The semiconductor device as claimed in claim 1, wherein the dielectric layer covers the second doped region. The semiconductor device as claimed in claim 1, wherein the second metal layer extends through the dielectric layer and is connected to the second doped region. The semiconductor device as claimed in claim 1 further includes: an insulating layer located between the first metal layer and the second metal layer for electrically isolating the first metal layer and the second metal layer.