TWI908334B - High-speed data input device and processing method for input data enabling high-speed transmission - Google Patents

Abstract

A data input device includes an input circuit, a training circuit, a detection circuit, a data delay line, and a clock delay line. The input circuit is configured to receive a first data signal and a first clock signal. The training circuit is configured to set a first delay setting based on the first data signal and the first clock signal. The first delay setting includes a first data delay amount and a first clock delay amount. The detection circuit is configured to set a second delay setting based on the first delay setting and a clock cycle of the first clock signal. The second delay setting includes a second data delay amount and a second clock delay amount. The data delay line is configured to output a second data signal based on the first data signal and the second data delay amount. The clock delay line is configured to output a second clock signal based on the first clock signal and the second clock delay amount.

Description

High-speed data input device and processing method for high-speed input data.

This case relates to data transmission technology, and in particular to a data input device and a method for processing input data that can achieve high-speed transmission.

In circuits, such as memory circuits, clock signals are typically used as the timing reference for their operation. However, variations in temperature and voltage can cause phase shifts in the clock signals, which in turn increases the error rate of memory circuits when sampling input data.

In some embodiments, a data input device includes an input circuit, a training circuit, a detection circuit, a data delay line, and a clock delay line. The input circuit receives a first data signal and a first clock signal. The training circuit is coupled to the input circuit and sets a first delay setting based on the first data signal and the first clock signal. The first delay setting includes a first data delay amount and a first clock delay amount. The detection circuit is coupled to the input circuit and the training circuit and sets a second delay setting based on the first delay setting and the clock cycle of the first clock signal. The second delay setting includes a second data delay amount and a second clock delay amount. A data delay line is coupled to the input circuit and the detection circuit to output a second data signal based on a first data signal and a second data delay. A clock delay line is coupled to the input circuit and the detection circuit to output a second clock signal based on a first clock signal and a second clock delay.

In some embodiments, the clock cycle includes multiple delay unit time intervals. The detection circuit is used to set a second delay setting based on the first delay setting and the number of delay unit time intervals included in the clock cycle.

In some embodiments, when the first delay setting is completed, the detection circuit detects and records the number of multiple delay unit time segments included in the clock cycle as a first number, and then detects the number of multiple delay unit time segments included in the clock cycle in real time thereafter. When the detection circuit detects that the number of multiple delay unit time segments included in the clock cycle is different from the first number, the detection circuit records the detected number of multiple delay unit time segments included in the clock cycle as a second number, and sets the second delay setting according to the first delay setting, the first number, and the second number.

In some embodiments, the first data delay, the first clock delay, the second data delay, and the second clock delay all comprise multiple delay unit time intervals. The detection circuit adjusts the number of delay unit time intervals in the first data delay based on a first number and a second number to obtain the second data delay. The detection circuit adjusts the number of delay unit time intervals in the first clock delay based on a first number and a second number to obtain the second clock delay.

In some embodiments, the detection circuit adjusts the number of multiple delay unit time intervals of the first data delay based on the ratio of the second number to the first number to obtain the second data delay. The detection circuit adjusts the number of multiple delay unit time intervals of the first clock delay based on the ratio of the second number to the first number to obtain the second clock delay.

In some embodiments, the detection circuit obtains a second data delay by multiplying the number of delay units (time grids) of the first data delay by the ratio of a second number to the first number. Similarly, the detection circuit obtains a second clock delay by multiplying the number of delay units (time grids) of the first clock delay by the ratio of a second number to the first number.

In some implementations, delay unit time intervals correspond to delay units. Delay units are buffers.

In some embodiments, an input data processing method includes: receiving a first data signal and a first clock signal; setting a first delay setting based on the first data signal and the first clock signal, the first delay setting including a first data delay amount and a first clock delay amount; setting a second delay setting based on the first delay setting and the clock cycle of the first clock signal, the second delay setting including a second data delay amount and a second clock delay amount; outputting a second data signal based on the first data signal and the second data delay amount; and outputting a second clock signal based on the first clock signal and the second clock delay amount.

In some embodiments, the clock cycle includes multiple delay unit time intervals. The steps of setting a second delay based on the clock cycle setting of the first delay setting and the first clock signal include: setting the second delay setting based on the first delay setting and the number of delay unit time intervals included in the clock cycle.

In some embodiments, the steps of setting a second delay setting based on a first delay setting and a clock cycle setting of a first clock signal include: when the first delay setting is completed, detecting and recording the number of multiple delay unit time segments included in the clock cycle at that time as a first number, and subsequently detecting the number of multiple delay unit time segments included in the clock cycle in real time; when the number of multiple delay unit time segments included in the clock cycle is detected to be different from the first number, recording the detected number of multiple delay unit time segments included in the clock cycle as a second number; and setting the second delay setting based on the first delay setting, the first number, and the second number.

In some embodiments, the first data delay, the first clock delay, the second data delay, and the second clock delay all include multiple delay unit time intervals. The steps of setting the second delay according to the first delay setting, the first number, and the second number include: adjusting the number of multiple delay unit time intervals of the first data delay according to the first number and the second number to obtain the second data delay; and adjusting the number of multiple delay unit time intervals of the first clock delay according to the first number and the second number to obtain the second clock delay.

In some embodiments, the step of setting a second delay based on a first delay setting, a first number, and a second number includes: adjusting the number of multiple delay unit time intervals of the first data delay amount according to the ratio of the second number to the first number to obtain the second data delay amount; and adjusting the number of multiple delay unit time intervals of the first clock delay amount according to the ratio of the second number to the first number to obtain the second clock delay amount.

In some embodiments, the step of setting a second delay based on a first delay setting, a first number, and a second number includes: multiplying the number of delay unit time grids of the first data delay by the ratio of the second number to the first number to obtain a second data delay; and multiplying the number of delay unit time grids of the first clock delay by the ratio of the second number to the first number to obtain a second clock delay.

The following detailed description of the features and advantages of this application is sufficient to enable anyone skilled in the art to understand the technical content of this application and implement it accordingly. Furthermore, based on the content disclosed in this specification, the scope of the patent application, and the drawings, anyone skilled in the art can easily understand the relevant purpose and advantages of this application.

Please refer to Figure 1. The data input device 1 includes an input circuit 10, a training circuit 11, a detection circuit 12, a data delay line 13, and a clock delay line 14. The training circuit 11 is coupled to the input circuit 10, the detection circuit 12, the data delay line 13, and the clock delay line 14. The detection circuit 12 is coupled to the input circuit 10, the training circuit 11, the data delay line 13, and the clock delay line 14.

In some embodiments, the data input device 1 can be applied to a transmission interface. Examples include a transmission interface for memory, such as Dynamic Random Access Memory (DRAM), a die-to-die transmission interface, etc., but this invention is not limited to these; the data input device 1 can be applied to any transmission interface. Furthermore, the data input device 1 can be presented as a chip through integrated circuit manufacturing processes.

Please refer to Figures 1 and 2. Input circuit 10 is used to receive the first data signal D1 and the first clock signal CK from output circuit 2 (step S01). Please refer to Figure 3A. In some embodiments, the first data signal D1 contains multiple data points. For ease of explanation, in Figure 3A, the first data signal D1 contains only 3 data points, namely data D01, data D11, and data D21, but the number of data points contained in the first data signal D1 is not limited to this. In some embodiments, when the first data signal D1 and the first clock signal CK are emitted from output circuit 2, the positive edge and/or negative edge of the first clock signal CK hits (is located) at the center position of each data point contained in the first data signal D1. Figure 3A shows an embodiment where the positive edge of the first clock signal CK hits the center position of all data points contained in the first data signal D1. Please refer to Figure 3B. In some embodiments, when the input circuit 10 receives the first data signal D1 and the first clock signal CK, a skew T1 occurs between the first data signal D1 and the first clock signal CK. The skew T1 causes the positive edge of the first clock signal CK to not correctly hit the center position of all data points contained in the first data signal D1. In the embodiment of Figure 3B, the skew T1 causes the first data signal D1 to be faster than the first clock signal CK, resulting in the first positive edge of the first clock signal CK hitting data D11 instead of the expected data D01.

In some embodiments, output circuit 2 may be a memory circuit. In some embodiments, output circuit 2 may be a volatile storage medium, a non-volatile storage medium, or a combination thereof. Volatile storage media include, for example, random access memory (RAM), and random access memory includes, for example, static random access memory (SRAM) or dynamic random access memory (DRAM). Non-volatile storage media include read-only memory (ROM), such as programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electronically eraseable programmable read-only memory (EEPROM), programmable read-only memory (OTPROM), or flash memory. The type of output circuit 2 is not limited here.

In some embodiments, the first clock signal CK may be a global clock generated by a clock source (e.g., but not limited to, an oscillator). Furthermore, the first clock signal CK may be delayed by a clock tree, but this is not a limitation of the present invention.

In some embodiments, the transmission speed of the first data signal D1 and the first clock signal CK may be, but is not limited to, 16 Gbps or 32 Gbps.

In some embodiments, the offset T1 is caused by the physical metal wires between the output circuit 2 and the input circuit 10.

In some embodiments, training circuit 11 is used to execute a training procedure to set a first delay setting A (step S02) based on a first data signal D1 and a first clock signal CK, thereby correcting the offset T1. The first delay setting A includes a first data delay amount A1 and a first clock delay amount A2. Please refer to Figures 4A to 4C. In some embodiments, during the training process of the training circuit 11, in order to ensure that the positive or negative edge of the first clock signal CK hits the center position of the current data D01 of the first data signal D1, as shown in Figure 4C, taking the positive edge of the first clock signal CK as an example, the data input device 1 can detect the relationship between the first data signal D1 and the first clock signal CK through the training circuit 11 to set the first data delay A1 and the first clock delay A2 accordingly. The data state of the first data signal D1 input in the training process is already known to the training circuit 11. For example, suppose the data state of the first data signal D1 is known to be "010" and the current data D01 is "1", and the relationship between the first data signal D1 and the first clock signal CK can be shown in Figure 4A. First, the training circuit 11 can adjust the left index G1 and the right index G2 respectively until the boundary of the current data D01. Among them, the training circuit 11 can determine whether it has been adjusted to the left boundary of the current data D01 based on whether the data sampled at the left index G1 is "0", and determine whether it has been adjusted to the right boundary of the current data D01 based on whether the data sampled at the right index G2 is "0". After adjusting the left indicator G1 and the right indicator G2 to the boundaries of the current data D01, as shown in Figure 4B, the training circuit 11 can obtain the data width of the current data D01 based on the distance between the left indicator G1 and the right indicator G2, and find the center position of the current data D01 based on the data width. Then, the training circuit 11 can set the first data delay A1 and the first clock delay A2 based on the found center position, thereby completing the training procedure of the data input device 1. Here, the training circuit 11 increases the delay of the first data signal D1 (i.e., the first data delay A1), as shown in Figure 4C. In some embodiments, the initial values of the first data delay A1 and the first clock delay A2 are both 0 seconds (s).

Figures 3B and 4A to 4C illustrate the concept with an offset T1 in which the first data signal D1 is faster than the first clock signal CK, but this invention is not limited to this. In some embodiments, the offset T1 can also make the first clock signal CK faster than the first data signal D1. In some embodiments, when the offset T1 makes the first clock signal CK faster than the first data signal D1, the training circuit 11 increases the delay of the first clock signal CK (i.e., the first clock delay A2).

By executing the training program through the training circuit 11, the training circuit 11 can determine the duration of the offset T1 and increase the first data delay A1 or the first clock delay A2 according to the duration of the offset T1. For example, if the duration of the offset T1 shown in Figure 3B is 200 picoseconds (ps), since the first data signal D1 is faster than the first clock signal CK, after the training circuit 11 executes the training program, the training circuit 11 will set the first data delay A1 to 200 ps.

In some embodiments, after the training circuit 11 obtains the first delay setting A, the training circuit 11 transmits the first data delay A1 to the data delay line 13 and the first clock delay A2 to the clock delay line 14. The data delay line 13 outputs a first data signal D1 with an increased delay based on the first data delay A1, which is provided to the data processing unit (not shown). The clock delay line 14 outputs a first clock signal CK with an increased delay based on the first clock delay A2, which is provided to the data processing unit. At this time, the positive and/or negative edge of the first clock signal CK output by the clock delay line 14 will correctly hit the center position of each data point contained in the first data signal D1 output by the data delay line 13.

However, in some embodiments, during the operation of the data input device 1, the first clock signal CK generated after the training circuit 11 corrects the offset T1 may generate a new offset T2 due to variations in temperature, voltage, etc. Please refer to Figure 5. Offset T2 causes the positive edge of the first clock signal CK after offset T1 correction to not accurately hit the center position of each data point contained in the first data signal D1 after offset T1 correction. In the embodiment of Figure 5, offset T2 causes the first clock signal CK after offset T1 correction to be faster than the first data signal D1 after offset T1 correction, resulting in the positive edge of the first clock signal CK after offset T1 correction not accurately hitting the expected data. In other words, the first data delay A1 and the first clock delay A2 set by the training circuit 11 at this time to correct the offset T1 are unable to cope with the effects of the offset T2.

In some embodiments, the detection circuit 12 is used to set a second delay setting B (step S03) based on the first delay setting A and the clock cycle T of the first clock signal CK, thereby correcting the offset T2. The second delay setting B includes a second data delay amount B1 and a second clock delay amount B2. Please refer to Figure 6. In some embodiments, the clock cycle T includes multiple delay unit time intervals d. The detection circuit 12 is used to set the second delay setting B based on the first delay setting A and the number of multiple delay unit time intervals d included in the clock cycle T.

In some embodiments, a delay unit time grid d corresponds to a delay unit. The number of delay unit time grids d contained in a clock cycle T represents the duration of the clock cycle T as the time required for a signal to pass through multiple delay units corresponding to the number of delay unit time grids d contained in the clock cycle T. For example, suppose the number of delay unit time grids d contained in the clock cycle T is 100. The duration of the clock cycle T is the time required for the signal to pass through 100 delay units. In some embodiments, the delay unit is a buffer.

Please refer to Figure 7. In some embodiments, when the detection circuit 12 performs step S03, the detection circuit 12 first detects and records the number of multiple delay unit time grids d contained in the clock period T as the first number when the training circuit 11 completes the first delay setting A (step S031), and then detects the number of multiple delay unit time grids d contained in the clock period T in real time thereafter. When the detection circuit 12 detects that the number of delay unit time grids d contained in the clock cycle T is different from the first number, the detection circuit 12 records the detected number of delay unit time grids d contained in the clock cycle T as the second number (step S032). Then, the detection circuit 12 sets the second delay setting B according to the first delay setting A, the first number, and the second number (step S033). For example, assuming that when the training circuit 11 completes the first delay setting A, the number of delay unit time grids d contained in the clock cycle T is 100. The detection circuit 12 detects and records 100 as the first number, and after recording 100 as the first number, it detects the number of delay unit time grids d contained in the clock cycle T in real time. When the detection circuit 12 detects that the number of delay unit time grids d contained in the clock cycle T is 80, since 80 is different from the first number (i.e., 100), the detection circuit 12 records the detected 80 as the second number. Next, the detection circuit 12 sets the second delay setting B according to the first delay setting A, the first number (i.e., 100) and the second number (i.e., 80).

The reason why the number of time units d in the clock period T varies at different times (i.e., the values of the first and second numbers are different) is because the delay units are affected by variations in temperature, voltage, etc. For example, assuming the first number is 100 and the second number is 80, this means that the duration of the clock period T changes from the time required for the signal to travel through 100 delay units to the time required for the signal to travel through 80 delay units. In other words, the time required for the signal to travel through a single delay unit has increased, and this increased time is due to the influence of variations in temperature, voltage, etc., on the delay units. Assuming the clock cycle T is 200 ps, since the clock cycle T is fixed, the time required for a signal to pass through a single delay unit is 2 ps (200 ps / 100 = 2 ps) when the number of delay unit time grids d in the clock cycle T is the first number, and 2.5 ps (200 ps / 80 = 2.5 ps) when the number of delay unit time grids d in the clock cycle T is the second number.

In some embodiments, the first data delay A1, the first clock delay A2, the second data delay B1, and the second clock delay B2 also include multiple delay unit time grids d. Similarly, as above, the number of delay unit time grids d contained in the first data delay A1, the first clock delay A2, the second data delay B1, and the second clock delay B2 represents the time length required for the signal to pass through multiple delay units corresponding to the number of delay unit time grids d contained in the first data delay A1, the first clock delay A2, the second data delay B1, and the second clock delay B2.

In some embodiments, the training circuit 11 sets the first data delay A1 and the first clock delay A2 by setting the number of delay unit time grids d contained in the first data delay A1 and the first clock delay A2. Taking Figure 3B as an example, if the time length of offset T1 shown in Figure 3B is 200 ps, since the first data signal D1 is faster than the first clock signal CK, after the training circuit 11 executes the training program, if the time required for the signal to pass through a single delay unit is 2 ps, the training circuit 11 will set the number of time grids d of the multiple delay units contained in the first data delay A1 to 100, so that the time length of the first data delay A1 is 200 ps. It should be noted that when the delay unit is affected by variations in temperature, voltage, etc., causing the time required for the signal to pass through a single delay unit to change, the offset caused by the number of time grids d of the multiple delay units included in the first data delay A1 and the first clock delay A2 set by the training circuit 11 is the offset T2. As in the previous example, if the delay unit is affected by variations in temperature, voltage, etc., causing the time required for the signal to pass through a single delay unit to increase from 2ps to 2.5ps, since the number of time grids d in the multiple delay units included in the first data delay A1 is now 100, the duration of the first data delay A1 becomes 250ps (2.5ps * 100 = 250ps), instead of the originally expected 200ps. This results in the first data signal D1 after the offset T1 being delayed too much, making the first clock signal CK after the offset T1 50ps faster than the first data signal D1 after the offset T1. This 50ps difference caused by variations in temperature, voltage, etc., is the offset T2.

In some embodiments, when performing step S033, the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay A1 according to the first number and the second number to obtain the second data delay B1. Furthermore, the detection circuit 12 adjusts the number of delay unit time grids d of the first clock delay A2 according to the first number and the second number to obtain the second clock delay B2. For example, if the first number is 100, the second number is 80, the clock period T is 200 ps, and the number of time grids d in the multiple delay units of the first data delay A1 is 100, since the time required for the signal to pass through a single delay unit increases from 2 ps (200 ps/100 = 2 ps) to 2.5 ps (200 ps/80 = 2.5 ps), when the number of time grids d in the multiple delay units contained in the first data delay A1 is 100, the first data delay A1's The duration is 250ps (2.5ps * 100 = 250ps), instead of the originally expected 200ps. Therefore, in order to maintain the duration of the delay at 200ps, the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay A1 to 80, so as to maintain a delay of 200ps (2.5ps * 80 = 200). The first data delay A1, which contains 80 delay unit time grids d, is the second data delay B1.

In some embodiments, when executing step S033, the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay A1 according to the ratio of the second number to the first number to obtain the second data delay B1. Furthermore, the detection circuit 12 adjusts the number of delay unit time grids d of the first clock delay A2 according to the ratio of the second number to the first number to obtain the second clock delay B2. In some embodiments, the detection circuit 12 multiplies the number of delay unit time grids d of the first data delay A1 by the ratio of the second number to the first number to obtain the second data delay B1. Furthermore, the detection circuit 12 multiplies the number of delay unit time grids d of the first clock delay A2 by the ratio of the second number to the first number to obtain the second clock delay B2. For example, assuming the first number is 100, the second number is 80, and the number of delay unit time grids d contained in the first data delay A1 is 100, the detection circuit 12 multiplies the number of delay unit time grids d contained in the first data delay A1 (i.e., 100) by the ratio of the second number to the first number (i.e., 80/100=0.8) to obtain the second data delay B1 containing 80 delay unit time grids d (100*0.8=80).

Figure 5 illustrates how offset T2 causes the first data signal D1 after offset T1 to be delayed by too much, resulting in the first clock signal CK after offset T1 being faster than the first data signal D1 after offset T1. However, this invention is not limited to this. In some embodiments, offset T2 can also cause the first clock signal CK after offset T1 to be delayed by too much, resulting in the first data signal D1 after offset T1 being faster than the first clock signal CK after offset T1.

In some embodiments, data delay line 13 is used to output a second data signal D2 to the data processing unit (not shown) based on the first data signal D1 and the second data delay amount B1 (step S04). Clock delay line 14 is used to output a second clock signal CK2 to the data processing unit based on the first clock signal CK and the second clock delay amount B2 (step S05). At this time, the positive edge and/or negative edge of the second clock signal CK2 output by clock delay line 14 will correctly hit the center position of each data point contained in the second data signal D2 output by data delay line 13.

In summary, the data input device 1 of any embodiment of this case can perform the input data processing method of any embodiment on the first data signal D1 and the first clock signal CK, so that the positive edge and/or negative edge of the second clock signal CK2 can hit the center position of each data item contained in the second data signal D2. In addition, even if an offset T2 occurs due to the influence of temperature, voltage and other variations, the data input device 1 performing the input data processing method of any embodiment can correct the offset T2 back without interrupting data transmission, thereby achieving high-speed data transmission.

Although the technical content of this case has been disclosed above by preferred embodiment, it is not intended to limit this case. Any modifications and refinements made by those skilled in this art without departing from the spirit of this case should be included within the scope of this case. Therefore, the scope of protection of this case shall be determined by the scope of the attached patent application.

1: Data Input Device 2: Output Circuit 10: Input Circuit 11: Training Circuit 12: Detection Circuit 13: Data Delay Line 14: Clock Delay Line A: First Delay Setting B: Second Delay Setting A1: First Data Delay Amount A2: First Clock Delay Amount B1: Second Data Delay Amount B2: Second Clock Delay Amount D1: First Data Signal CK: First Clock Signal D2: Second Data Signal CK2: Second Clock Signal S01~S05,S031~S033: Steps D01,D11,D21: Data T1,T2: Offset G1,G2: Indicators T: Clock cycle d: Delayed time interval

Figure 1 is a schematic diagram of one embodiment of the data input device and output circuit. Figure 2 is a flowchart of one embodiment of the input data processing method. Figure 3A is a schematic diagram of one embodiment when the first data signal and the first clock signal are emitted from the output circuit. Figure 3B is a schematic diagram of one embodiment when the first data signal and the first clock signal are received from the input circuit. Figures 4A-4C are schematic diagrams of one embodiment of the training procedure of the training circuit. Figure 5 is a schematic diagram of one embodiment of the first data signal and the first clock signal after the training procedure and after being affected by temperature and voltage. Figure 6 is a schematic diagram of one embodiment of the clock cycle. Figure 7 is a flowchart of one embodiment of step S03.

1: Data Input Device

2: Output circuit

10: Input Circuit

11: Training Circuit

12: Detection Circuit

13: Data Delay Line

14: Clock Delay Line

A: First delay setting

B: Second delay setting

A1: First Data Delay

A2: First pulse delay

B1: Second Data Delay

B2: Second time delay

D1: First Data Signal

CK: First pulse signal

D2: Second Data Signal

CK2: Second pulse signal

Claims (12)

A data input device includes: an input circuit for receiving a first data signal and a first clock signal; a training circuit coupled to the input circuit for setting a first delay setting based on the first data signal and the first clock signal, the first delay setting including a first data delay amount and a first clock delay amount; and a detection circuit coupled to the input circuit and the training circuit for setting a second delay setting based on the first delay setting and a clock cycle of the first clock signal, the second delay setting including a second data delay. The system includes a first data signal and a second clock delay; a data delay line coupled to the input circuit and the detection circuit for outputting a second data signal based on the first data signal and the second data delay; and a clock delay line coupled to the input circuit and the detection circuit for outputting a second clock signal based on the first clock signal and the second clock delay; wherein the clock period includes multiple delay unit time intervals, and the detection circuit is used to set the second delay setting based on the first delay setting and the number of delay unit time intervals included in the clock period. As described in claim 1, in the data input device, when the first delay setting is completed, the detection circuit detects and records the number of delay unit time segments included in the clock cycle as a first number, and then detects the number of delay unit time segments included in the clock cycle in real time. When the detection circuit detects that the number of delay unit time segments included in the clock cycle is different from the first number, the detection circuit records the detected number of delay unit time segments included in the clock cycle as a second number, and sets the second delay setting according to the first delay setting, the first number, and the second number. The data input device as described in claim 2, wherein the first data delay, the first clock delay, the second data delay, and the second clock delay each include multiple delay unit time intervals, the detection circuit adjusts the number of delay unit time intervals of the first data delay according to the first number and the second number to obtain the second data delay, and the detection circuit adjusts the number of delay unit time intervals of the first clock delay according to the first number and the second number to obtain the second clock delay. The data input device as described in claim 3, wherein the detection circuit adjusts the number of delay unit time grids of the first data delay based on the ratio of the second number to the first number to obtain the second data delay, and the detection circuit adjusts the number of delay unit time grids of the first clock delay based on the ratio of the second number to the first number to obtain the second clock delay. The data input device as described in claim 4, wherein the detection circuit obtains the second data delay by multiplying the number of delay unit time grids of the first data delay by the ratio of the second number to the first number, and the detection circuit obtains the second clock delay by multiplying the number of delay unit time grids of the first clock delay by the ratio of the second number to the first number. The data input device as described in claim 5, wherein the delay unit time interval corresponds to a delay unit, which is a buffer. A method for processing input data includes: receiving a first data signal and a first clock signal; setting a first delay setting based on the first data signal and the first clock signal, the first delay setting including a first data delay amount and a first clock delay amount; setting a second delay setting based on the first delay setting and a clock cycle of the first clock signal, the second delay setting including a second data delay amount and a second clock delay amount; and further processing the input data. The system outputs a second data signal based on a first data signal and the second data delay; and outputs a second clock signal based on the first clock signal and the second clock delay; wherein the clock cycle includes multiple delay unit time intervals, and the steps of setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal include: setting the second delay setting based on the first delay setting and the number of delay unit time intervals included in the clock cycle. The input data processing method as described in claim 7, wherein the step of setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal includes: when the first delay setting is completed, detecting and recording the number of delay unit time intervals included in the clock cycle at that time as a first number, and subsequently detecting the time interval in real time. The number of delay unit time intervals included in the clock cycle; when the number of delay unit time intervals included in the clock cycle is detected to be different from the first number, the detected number of delay unit time intervals included in the clock cycle is recorded as a second number; and the second delay setting is set according to the first delay setting, the first number, and the second number. The input data processing method as described in claim 8, wherein the first data delay, the first clock delay, the second data delay, and the second clock delay each include multiple delay unit time intervals, and the step of setting the second delay setting according to the first delay setting, the first number, and the second number includes: adjusting the number of delay unit time intervals of the first data delay according to the first number and the second number to obtain the second data delay; and adjusting the number of delay unit time intervals of the first clock delay according to the first number and the second number to obtain the second clock delay. The method for processing input data as described in claim 9, wherein the step of setting the second delay setting according to the first delay setting, the first number, and the second number includes: adjusting the number of delay unit time grids of the first data delay amount according to the ratio of the second number and the first number to obtain the second data delay amount; and adjusting the number of delay unit time grids of the first clock delay amount according to the ratio of the second number and the first number to obtain the second clock delay amount. The input data processing method as described in claim 10, wherein the step of setting the second delay setting according to the first delay setting, the first number, and the second number includes: multiplying the number of delay unit time grids of the first data delay amount by the ratio of the second number and the first number to obtain the second data delay amount; and multiplying the number of delay unit time grids of the first clock delay amount by the ratio of the second number and the first number to obtain the second clock delay amount. The input data processing method as described in claim 11, wherein the delay unit time grid corresponds to a delay unit, and the delay unit is a buffer.